X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FFPMover.cpp;h=70f203ccca919bf16022d006a4eab88e91f19f12;hb=7c90f73a1b06040d971a3dd95a491031ae6238d5;hp=c319833599838fb54878dd62ceb55fe9c26fa91d;hpb=b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0;p=oota-llvm.git diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp index c3198335998..70f203ccca9 100644 --- a/lib/Target/Sparc/FPMover.cpp +++ b/lib/Target/Sparc/FPMover.cpp @@ -1,4 +1,4 @@ -//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===// +//===-- FPMover.cpp - Sparc double-precision floating point move fixer ----===// // // The LLVM Compiler Infrastructure // @@ -7,21 +7,23 @@ // //===----------------------------------------------------------------------===// // -// Turns FpMOVD instructions into FMOVS pairs after regalloc. +// Expand FpMOVD/FpABSD/FpNEGD instructions into their single-precision pieces. // //===----------------------------------------------------------------------===// -#include "SparcV8.h" +#include "Sparc.h" +#include "SparcSubtarget.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" - +#include using namespace llvm; namespace { - Statistic<> NumFpMOVDs ("fpmover", "# FpMOVD instructions translated"); - Statistic<> SkippedFpMOVDs ("fpmover", "# FpMOVD instructions skipped"); + Statistic<> NumFpDs("fpmover", "Number of instructions translated"); + Statistic<> NoopFpDs("fpmover", "Number of noop instructions removed"); struct FPMover : public MachineFunctionPass { /// Target machine description which we query for reg. names, data @@ -29,77 +31,102 @@ namespace { /// TargetMachine &TM; - FPMover (TargetMachine &tm) : TM (tm) { } - - virtual const char *getPassName () const { - return "SparcV8 Double-FP Move Fixer"; - } + FPMover(TargetMachine &tm) : TM(tm) { } - bool runOnMachineBasicBlock (MachineBasicBlock &MBB); - bool runOnMachineFunction (MachineFunction &F) { - bool Changed = false; - for (MachineFunction::iterator FI = F.begin (), FE = F.end (); - FI != FE; ++FI) - Changed |= runOnMachineBasicBlock (*FI); - return Changed; + virtual const char *getPassName() const { + return "Sparc Double-FP Move Fixer"; } + bool runOnMachineBasicBlock(MachineBasicBlock &MBB); + bool runOnMachineFunction(MachineFunction &F); }; } // end of anonymous namespace -/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD +/// createSparcFPMoverPass - Returns a pass that turns FpMOVD /// instructions into FMOVS instructions /// -FunctionPass *llvm::createSparcV8FPMoverPass (TargetMachine &tm) { - return new FPMover (tm); +FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) { + return new FPMover(tm); } -static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, unsigned &singleReg2) { - const unsigned EvenHalvesOfPairs[] = { V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 }; - const unsigned OddHalvesOfPairs[] = { V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 }; - const unsigned DoubleRegsInOrder[] = { V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 }; +/// getDoubleRegPair - Given a DFP register, return the even and odd FP +/// registers that correspond to it. +static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg, + unsigned &OddReg) { + static const unsigned EvenHalvesOfPairs[] = { + SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14, + SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30 + }; + static const unsigned OddHalvesOfPairs[] = { + SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15, + SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31 + }; + static const unsigned DoubleRegsInOrder[] = { + SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, + SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15 + }; for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i) - if (DoubleRegsInOrder[i] == doubleReg) { - singleReg1 = EvenHalvesOfPairs[i]; - singleReg2 = OddHalvesOfPairs[i]; + if (DoubleRegsInOrder[i] == DoubleReg) { + EvenReg = EvenHalvesOfPairs[i]; + OddReg = OddHalvesOfPairs[i]; return; } - assert (0 && "Can't find reg"); + assert(0 && "Can't find reg"); } /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. /// -bool FPMover::runOnMachineBasicBlock (MachineBasicBlock &MBB) { +bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I) - if (V8::FpMOVD == I->getOpcode ()) { - unsigned NewSrcReg0, NewSrcReg1, NewDestReg0, NewDestReg1; - doubleToSingleRegPair (I->getOperand (0).getReg (), NewDestReg0, - NewDestReg1); - doubleToSingleRegPair (I->getOperand (1).getReg (), NewSrcReg0, - NewSrcReg1); - MachineBasicBlock::iterator J = I; - ++J; - if (!(NewDestReg0 == NewSrcReg0 && NewDestReg1 == NewSrcReg1)) { - I->setOpcode (V8::FMOVS); - I->SetMachineOperandReg (0, NewDestReg0); - I->SetMachineOperandReg (1, NewSrcReg0); - DEBUG (std::cerr << "FPMover: new dest reg. is: " << NewDestReg0 - << "; modified instr is: " << *I); - // Insert copy for the other half of the double: - MachineInstr *MI2 = - BuildMI (MBB, J, V8::FMOVS, 1, NewDestReg1).addReg (NewSrcReg1); - DEBUG (std::cerr << "FPMover: new dest reg. is " << NewDestReg1 - << "; inserted instr is: " << *MI2); - ++NumFpMOVDs; - I = J; - --I; - } else { - MBB.erase (I); - ++SkippedFpMOVDs; - I = J; - } + for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { + MachineInstr *MI = I++; + if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD || + MI->getOpcode() == SP::FpNEGD) { Changed = true; + unsigned DestDReg = MI->getOperand(0).getReg(); + unsigned SrcDReg = MI->getOperand(1).getReg(); + if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) { + MBB.erase(MI); // Eliminate the noop copy. + ++NoopFpDs; + continue; + } + + unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0; + getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg); + getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg); + + if (MI->getOpcode() == SP::FpMOVD) + MI->setOpcode(SP::FMOVS); + else if (MI->getOpcode() == SP::FpNEGD) + MI->setOpcode(SP::FNEGS); + else if (MI->getOpcode() == SP::FpABSD) + MI->setOpcode(SP::FABSS); + else + assert(0 && "Unknown opcode!"); + + MI->SetMachineOperandReg(0, EvenDestReg); + MI->SetMachineOperandReg(1, EvenSrcReg); + DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI); + // Insert copy for the other half of the double. + if (DestDReg != SrcDReg) { + MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg); + DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI); + } + ++NumFpDs; } + } + return Changed; +} + +bool FPMover::runOnMachineFunction(MachineFunction &F) { + // If the target has V9 instructions, the fp-mover pseudos will never be + // emitted. Avoid a scan of the instructions to improve compile time. + if (TM.getSubtarget().isV9()) + return false; + + bool Changed = false; + for (MachineFunction::iterator FI = F.begin(), FE = F.end(); + FI != FE; ++FI) + Changed |= runOnMachineBasicBlock(*FI); return Changed; }