X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FR600%2FSIInstructions.td;h=d437fb252b7dc53a94400df3270f4cc8c72ed7e6;hb=c31aaa5a3fcef2851898fb30c61c16a70564079a;hp=6525b49f3a5155415c7f07f46439a4d4e2410c1e;hpb=ee9772d9ddbc62ca9f965ed2c0b40a3326bcd2b0;p=oota-llvm.git diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 6525b49f3a5..d437fb252b7 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -31,13 +31,17 @@ def isSI : Predicate<"Subtarget.getGeneration() " def isCI : Predicate<"Subtarget.getGeneration() " ">= AMDGPUSubtarget::SEA_ISLANDS">; - -def isCFDepth0 : Predicate<"isCFDepth0()">; +def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">; def WAIT_FLAG : InstFlag<"printWaitFlag">; let SubtargetPredicate = isSI in { -let OtherPredicates = [isCFDepth0] in { + +//===----------------------------------------------------------------------===// +// EXP Instructions +//===----------------------------------------------------------------------===// + +defm EXP : EXP_m; //===----------------------------------------------------------------------===// // SMRD Instructions @@ -83,8 +87,6 @@ defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < // SOP1 Instructions //===----------------------------------------------------------------------===// -let neverHasSideEffects = 1 in { - let isMoveImm = 1 in { def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; @@ -101,21 +103,29 @@ def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", >; def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; -def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; +def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", + [(set i32:$dst, (AMDGPUbrev i32:$src0))] +>; def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; -} // End neverHasSideEffects = 1 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "S_BCNT1_I32_B32", [(set i32:$dst, (ctpop i32:$src0))] >; -////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; -////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; +def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "S_BCNT1_I32_B64", []>; + +////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "S_FF0_I32_B32", []>; ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; -////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; +def S_FF1_I32_B32 : SOP1_32 <0x00000013, "S_FF1_I32_B32", + [(set i32:$dst, (cttz_zero_undef i32:$src0))] +>; ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; -//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; + +def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", + [(set i32:$dst, (ctlz_zero_undef i32:$src0))] +>; + //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; @@ -130,7 +140,11 @@ def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; -def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; +def S_GETPC_B64 : SOP1 < + 0x0000001f, (outs SReg_64:$dst), (ins), "S_GETPC_B64 $dst", [] +> { + let SSRC0 = 0; +} def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; @@ -264,11 +278,15 @@ def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", [(set i64:$dst, (sra i64:$src0, i32:$src1))] >; -} // End AddedComplexity = 1 def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; -def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; +def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", + [(set i32:$dst, (mul i32:$src0, i32:$src1))] +>; + +} // End AddedComplexity = 1 + def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; @@ -324,7 +342,7 @@ def S_CMPK_EQ_I32 : SOPK < >; */ -let isCompare = 1 in { +let isCompare = 1, Defs = [SCC] in { def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; @@ -336,7 +354,7 @@ def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; -} // End isCompare = 1 +} // End isCompare = 1, Defs = [SCC] let Defs = [SCC], isCommutable = 1 in { def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; @@ -350,62 +368,60 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; //def EXP : EXP_ <0x00000000, "EXP", []>; -} // End let OtherPredicates = [isCFDepth0] - //===----------------------------------------------------------------------===// // SOPP Instructions //===----------------------------------------------------------------------===// -def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>; +def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "S_NOP $simm16", []>; let isTerminator = 1 in { def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", [(IL_retflag)]> { - let SIMM16 = 0; + let simm16 = 0; let isBarrier = 1; let hasCtrlDep = 1; } let isBranch = 1 in { def S_BRANCH : SOPP < - 0x00000002, (ins brtarget:$target), "S_BRANCH $target", - [(br bb:$target)]> { + 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16", + [(br bb:$simm16)]> { let isBarrier = 1; } let DisableEncoding = "$scc" in { def S_CBRANCH_SCC0 : SOPP < - 0x00000004, (ins brtarget:$target, SCCReg:$scc), - "S_CBRANCH_SCC0 $target", [] + 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc), + "S_CBRANCH_SCC0 $simm16", [] >; def S_CBRANCH_SCC1 : SOPP < - 0x00000005, (ins brtarget:$target, SCCReg:$scc), - "S_CBRANCH_SCC1 $target", + 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc), + "S_CBRANCH_SCC1 $simm16", [] >; } // End DisableEncoding = "$scc" def S_CBRANCH_VCCZ : SOPP < - 0x00000006, (ins brtarget:$target, VCCReg:$vcc), - "S_CBRANCH_VCCZ $target", + 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc), + "S_CBRANCH_VCCZ $simm16", [] >; def S_CBRANCH_VCCNZ : SOPP < - 0x00000007, (ins brtarget:$target, VCCReg:$vcc), - "S_CBRANCH_VCCNZ $target", + 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc), + "S_CBRANCH_VCCNZ $simm16", [] >; let DisableEncoding = "$exec" in { def S_CBRANCH_EXECZ : SOPP < - 0x00000008, (ins brtarget:$target, EXECReg:$exec), - "S_CBRANCH_EXECZ $target", + 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec), + "S_CBRANCH_EXECZ $simm16", [] >; def S_CBRANCH_EXECNZ : SOPP < - 0x00000009, (ins brtarget:$target, EXECReg:$exec), - "S_CBRANCH_EXECNZ $target", + 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec), + "S_CBRANCH_EXECNZ $simm16", [] >; } // End DisableEncoding = "$exec" @@ -418,7 +434,7 @@ let hasSideEffects = 1 in { def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", [(int_AMDGPU_barrier_local)] > { - let SIMM16 = 0; + let simm16 = 0; let isBarrier = 1; let hasCtrlDep = 1; let mayLoad = 1; @@ -454,257 +470,257 @@ let Uses = [EXEC] in { let isCompare = 1 in { -defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; -defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; -defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; -defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; -defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; -defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; -defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; -defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; -defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; -defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; -defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; -defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; -defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; -defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; -defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; -defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; +defm V_CMP_F_F32 : VOPC_F32 , "V_CMP_F_F32">; +defm V_CMP_LT_F32 : VOPC_F32 , "V_CMP_LT_F32", COND_OLT>; +defm V_CMP_EQ_F32 : VOPC_F32 , "V_CMP_EQ_F32", COND_OEQ>; +defm V_CMP_LE_F32 : VOPC_F32 , "V_CMP_LE_F32", COND_OLE>; +defm V_CMP_GT_F32 : VOPC_F32 , "V_CMP_GT_F32", COND_OGT>; +defm V_CMP_LG_F32 : VOPC_F32 , "V_CMP_LG_F32">; +defm V_CMP_GE_F32 : VOPC_F32 , "V_CMP_GE_F32", COND_OGE>; +defm V_CMP_O_F32 : VOPC_F32 , "V_CMP_O_F32", COND_O>; +defm V_CMP_U_F32 : VOPC_F32 , "V_CMP_U_F32", COND_UO>; +defm V_CMP_NGE_F32 : VOPC_F32 , "V_CMP_NGE_F32">; +defm V_CMP_NLG_F32 : VOPC_F32 , "V_CMP_NLG_F32">; +defm V_CMP_NGT_F32 : VOPC_F32 , "V_CMP_NGT_F32">; +defm V_CMP_NLE_F32 : VOPC_F32 , "V_CMP_NLE_F32">; +defm V_CMP_NEQ_F32 : VOPC_F32 , "V_CMP_NEQ_F32", COND_UNE>; +defm V_CMP_NLT_F32 : VOPC_F32 , "V_CMP_NLT_F32">; +defm V_CMP_TRU_F32 : VOPC_F32 , "V_CMP_TRU_F32">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; -defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; -defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; -defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; -defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; -defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; -defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; -defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; -defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; -defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; -defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; -defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; -defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; -defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; -defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; -defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; +defm V_CMPX_F_F32 : VOPCX_F32 , "V_CMPX_F_F32">; +defm V_CMPX_LT_F32 : VOPCX_F32 , "V_CMPX_LT_F32">; +defm V_CMPX_EQ_F32 : VOPCX_F32 , "V_CMPX_EQ_F32">; +defm V_CMPX_LE_F32 : VOPCX_F32 , "V_CMPX_LE_F32">; +defm V_CMPX_GT_F32 : VOPCX_F32 , "V_CMPX_GT_F32">; +defm V_CMPX_LG_F32 : VOPCX_F32 , "V_CMPX_LG_F32">; +defm V_CMPX_GE_F32 : VOPCX_F32 , "V_CMPX_GE_F32">; +defm V_CMPX_O_F32 : VOPCX_F32 , "V_CMPX_O_F32">; +defm V_CMPX_U_F32 : VOPCX_F32 , "V_CMPX_U_F32">; +defm V_CMPX_NGE_F32 : VOPCX_F32 , "V_CMPX_NGE_F32">; +defm V_CMPX_NLG_F32 : VOPCX_F32 , "V_CMPX_NLG_F32">; +defm V_CMPX_NGT_F32 : VOPCX_F32 , "V_CMPX_NGT_F32">; +defm V_CMPX_NLE_F32 : VOPCX_F32 , "V_CMPX_NLE_F32">; +defm V_CMPX_NEQ_F32 : VOPCX_F32 , "V_CMPX_NEQ_F32">; +defm V_CMPX_NLT_F32 : VOPCX_F32 , "V_CMPX_NLT_F32">; +defm V_CMPX_TRU_F32 : VOPCX_F32 , "V_CMPX_TRU_F32">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; -defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; -defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; -defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; -defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; -defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; -defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; -defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; -defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; -defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; -defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; -defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; -defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; -defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; -defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; -defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; +defm V_CMP_F_F64 : VOPC_F64 , "V_CMP_F_F64">; +defm V_CMP_LT_F64 : VOPC_F64 , "V_CMP_LT_F64", COND_OLT>; +defm V_CMP_EQ_F64 : VOPC_F64 , "V_CMP_EQ_F64", COND_OEQ>; +defm V_CMP_LE_F64 : VOPC_F64 , "V_CMP_LE_F64", COND_OLE>; +defm V_CMP_GT_F64 : VOPC_F64 , "V_CMP_GT_F64", COND_OGT>; +defm V_CMP_LG_F64 : VOPC_F64 , "V_CMP_LG_F64">; +defm V_CMP_GE_F64 : VOPC_F64 , "V_CMP_GE_F64", COND_OGE>; +defm V_CMP_O_F64 : VOPC_F64 , "V_CMP_O_F64", COND_O>; +defm V_CMP_U_F64 : VOPC_F64 , "V_CMP_U_F64", COND_UO>; +defm V_CMP_NGE_F64 : VOPC_F64 , "V_CMP_NGE_F64">; +defm V_CMP_NLG_F64 : VOPC_F64 , "V_CMP_NLG_F64">; +defm V_CMP_NGT_F64 : VOPC_F64 , "V_CMP_NGT_F64">; +defm V_CMP_NLE_F64 : VOPC_F64 , "V_CMP_NLE_F64">; +defm V_CMP_NEQ_F64 : VOPC_F64 , "V_CMP_NEQ_F64", COND_UNE>; +defm V_CMP_NLT_F64 : VOPC_F64 , "V_CMP_NLT_F64">; +defm V_CMP_TRU_F64 : VOPC_F64 , "V_CMP_TRU_F64">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; -defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; -defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; -defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; -defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; -defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; -defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; -defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; -defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; -defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; -defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; -defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; -defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; -defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; -defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; -defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; +defm V_CMPX_F_F64 : VOPCX_F64 , "V_CMPX_F_F64">; +defm V_CMPX_LT_F64 : VOPCX_F64 , "V_CMPX_LT_F64">; +defm V_CMPX_EQ_F64 : VOPCX_F64 , "V_CMPX_EQ_F64">; +defm V_CMPX_LE_F64 : VOPCX_F64 , "V_CMPX_LE_F64">; +defm V_CMPX_GT_F64 : VOPCX_F64 , "V_CMPX_GT_F64">; +defm V_CMPX_LG_F64 : VOPCX_F64 , "V_CMPX_LG_F64">; +defm V_CMPX_GE_F64 : VOPCX_F64 , "V_CMPX_GE_F64">; +defm V_CMPX_O_F64 : VOPCX_F64 , "V_CMPX_O_F64">; +defm V_CMPX_U_F64 : VOPCX_F64 , "V_CMPX_U_F64">; +defm V_CMPX_NGE_F64 : VOPCX_F64 , "V_CMPX_NGE_F64">; +defm V_CMPX_NLG_F64 : VOPCX_F64 , "V_CMPX_NLG_F64">; +defm V_CMPX_NGT_F64 : VOPCX_F64 , "V_CMPX_NGT_F64">; +defm V_CMPX_NLE_F64 : VOPCX_F64 , "V_CMPX_NLE_F64">; +defm V_CMPX_NEQ_F64 : VOPCX_F64 , "V_CMPX_NEQ_F64">; +defm V_CMPX_NLT_F64 : VOPCX_F64 , "V_CMPX_NLT_F64">; +defm V_CMPX_TRU_F64 : VOPCX_F64 , "V_CMPX_TRU_F64">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; -defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; -defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; -defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; -defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; -defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; -defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; -defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; -defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; -defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; -defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; -defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; -defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; -defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; -defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; -defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; +defm V_CMPS_F_F32 : VOPC_F32 , "V_CMPS_F_F32">; +defm V_CMPS_LT_F32 : VOPC_F32 , "V_CMPS_LT_F32">; +defm V_CMPS_EQ_F32 : VOPC_F32 , "V_CMPS_EQ_F32">; +defm V_CMPS_LE_F32 : VOPC_F32 , "V_CMPS_LE_F32">; +defm V_CMPS_GT_F32 : VOPC_F32 , "V_CMPS_GT_F32">; +defm V_CMPS_LG_F32 : VOPC_F32 , "V_CMPS_LG_F32">; +defm V_CMPS_GE_F32 : VOPC_F32 , "V_CMPS_GE_F32">; +defm V_CMPS_O_F32 : VOPC_F32 , "V_CMPS_O_F32">; +defm V_CMPS_U_F32 : VOPC_F32 , "V_CMPS_U_F32">; +defm V_CMPS_NGE_F32 : VOPC_F32 , "V_CMPS_NGE_F32">; +defm V_CMPS_NLG_F32 : VOPC_F32 , "V_CMPS_NLG_F32">; +defm V_CMPS_NGT_F32 : VOPC_F32 , "V_CMPS_NGT_F32">; +defm V_CMPS_NLE_F32 : VOPC_F32 , "V_CMPS_NLE_F32">; +defm V_CMPS_NEQ_F32 : VOPC_F32 , "V_CMPS_NEQ_F32">; +defm V_CMPS_NLT_F32 : VOPC_F32 , "V_CMPS_NLT_F32">; +defm V_CMPS_TRU_F32 : VOPC_F32 , "V_CMPS_TRU_F32">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; -defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; -defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; -defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; -defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; -defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; -defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; -defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; -defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; -defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; -defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; -defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; -defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; -defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; -defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; -defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; +defm V_CMPSX_F_F32 : VOPCX_F32 , "V_CMPSX_F_F32">; +defm V_CMPSX_LT_F32 : VOPCX_F32 , "V_CMPSX_LT_F32">; +defm V_CMPSX_EQ_F32 : VOPCX_F32 , "V_CMPSX_EQ_F32">; +defm V_CMPSX_LE_F32 : VOPCX_F32 , "V_CMPSX_LE_F32">; +defm V_CMPSX_GT_F32 : VOPCX_F32 , "V_CMPSX_GT_F32">; +defm V_CMPSX_LG_F32 : VOPCX_F32 , "V_CMPSX_LG_F32">; +defm V_CMPSX_GE_F32 : VOPCX_F32 , "V_CMPSX_GE_F32">; +defm V_CMPSX_O_F32 : VOPCX_F32 , "V_CMPSX_O_F32">; +defm V_CMPSX_U_F32 : VOPCX_F32 , "V_CMPSX_U_F32">; +defm V_CMPSX_NGE_F32 : VOPCX_F32 , "V_CMPSX_NGE_F32">; +defm V_CMPSX_NLG_F32 : VOPCX_F32 , "V_CMPSX_NLG_F32">; +defm V_CMPSX_NGT_F32 : VOPCX_F32 , "V_CMPSX_NGT_F32">; +defm V_CMPSX_NLE_F32 : VOPCX_F32 , "V_CMPSX_NLE_F32">; +defm V_CMPSX_NEQ_F32 : VOPCX_F32 , "V_CMPSX_NEQ_F32">; +defm V_CMPSX_NLT_F32 : VOPCX_F32 , "V_CMPSX_NLT_F32">; +defm V_CMPSX_TRU_F32 : VOPCX_F32 , "V_CMPSX_TRU_F32">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; -defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; -defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; -defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; -defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; -defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; -defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; -defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; -defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; -defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; -defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; -defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; -defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; -defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; -defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; -defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; +defm V_CMPS_F_F64 : VOPC_F64 , "V_CMPS_F_F64">; +defm V_CMPS_LT_F64 : VOPC_F64 , "V_CMPS_LT_F64">; +defm V_CMPS_EQ_F64 : VOPC_F64 , "V_CMPS_EQ_F64">; +defm V_CMPS_LE_F64 : VOPC_F64 , "V_CMPS_LE_F64">; +defm V_CMPS_GT_F64 : VOPC_F64 , "V_CMPS_GT_F64">; +defm V_CMPS_LG_F64 : VOPC_F64 , "V_CMPS_LG_F64">; +defm V_CMPS_GE_F64 : VOPC_F64 , "V_CMPS_GE_F64">; +defm V_CMPS_O_F64 : VOPC_F64 , "V_CMPS_O_F64">; +defm V_CMPS_U_F64 : VOPC_F64 , "V_CMPS_U_F64">; +defm V_CMPS_NGE_F64 : VOPC_F64 , "V_CMPS_NGE_F64">; +defm V_CMPS_NLG_F64 : VOPC_F64 , "V_CMPS_NLG_F64">; +defm V_CMPS_NGT_F64 : VOPC_F64 , "V_CMPS_NGT_F64">; +defm V_CMPS_NLE_F64 : VOPC_F64 , "V_CMPS_NLE_F64">; +defm V_CMPS_NEQ_F64 : VOPC_F64 , "V_CMPS_NEQ_F64">; +defm V_CMPS_NLT_F64 : VOPC_F64 , "V_CMPS_NLT_F64">; +defm V_CMPS_TRU_F64 : VOPC_F64 , "V_CMPS_TRU_F64">; let hasSideEffects = 1, Defs = [EXEC] in { -defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; -defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; -defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; -defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; -defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; -defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; -defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; -defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; -defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; -defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; -defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; -defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; -defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; -defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; -defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; -defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; +defm V_CMPSX_F_F64 : VOPC_F64 , "V_CMPSX_F_F64">; +defm V_CMPSX_LT_F64 : VOPC_F64 , "V_CMPSX_LT_F64">; +defm V_CMPSX_EQ_F64 : VOPC_F64 , "V_CMPSX_EQ_F64">; +defm V_CMPSX_LE_F64 : VOPC_F64 , "V_CMPSX_LE_F64">; +defm V_CMPSX_GT_F64 : VOPC_F64 , "V_CMPSX_GT_F64">; +defm V_CMPSX_LG_F64 : VOPC_F64 , "V_CMPSX_LG_F64">; +defm V_CMPSX_GE_F64 : VOPC_F64 , "V_CMPSX_GE_F64">; +defm V_CMPSX_O_F64 : VOPC_F64 , "V_CMPSX_O_F64">; +defm V_CMPSX_U_F64 : VOPC_F64 , "V_CMPSX_U_F64">; +defm V_CMPSX_NGE_F64 : VOPC_F64 , "V_CMPSX_NGE_F64">; +defm V_CMPSX_NLG_F64 : VOPC_F64 , "V_CMPSX_NLG_F64">; +defm V_CMPSX_NGT_F64 : VOPC_F64 , "V_CMPSX_NGT_F64">; +defm V_CMPSX_NLE_F64 : VOPC_F64 , "V_CMPSX_NLE_F64">; +defm V_CMPSX_NEQ_F64 : VOPC_F64 , "V_CMPSX_NEQ_F64">; +defm V_CMPSX_NLT_F64 : VOPC_F64 , "V_CMPSX_NLT_F64">; +defm V_CMPSX_TRU_F64 : VOPC_F64 , "V_CMPSX_TRU_F64">; } // End hasSideEffects = 1, Defs = [EXEC] -defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; -defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; -defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; -defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; -defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; -defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; -defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; -defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; +defm V_CMP_F_I32 : VOPC_I32 , "V_CMP_F_I32">; +defm V_CMP_LT_I32 : VOPC_I32 , "V_CMP_LT_I32", COND_SLT>; +defm V_CMP_EQ_I32 : VOPC_I32 , "V_CMP_EQ_I32", COND_EQ>; +defm V_CMP_LE_I32 : VOPC_I32 , "V_CMP_LE_I32", COND_SLE>; +defm V_CMP_GT_I32 : VOPC_I32 , "V_CMP_GT_I32", COND_SGT>; +defm V_CMP_NE_I32 : VOPC_I32 , "V_CMP_NE_I32", COND_NE>; +defm V_CMP_GE_I32 : VOPC_I32 , "V_CMP_GE_I32", COND_SGE>; +defm V_CMP_T_I32 : VOPC_I32 , "V_CMP_T_I32">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; -defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; -defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; -defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; -defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; -defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; -defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; -defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; +defm V_CMPX_F_I32 : VOPCX_I32 , "V_CMPX_F_I32">; +defm V_CMPX_LT_I32 : VOPCX_I32 , "V_CMPX_LT_I32">; +defm V_CMPX_EQ_I32 : VOPCX_I32 , "V_CMPX_EQ_I32">; +defm V_CMPX_LE_I32 : VOPCX_I32 , "V_CMPX_LE_I32">; +defm V_CMPX_GT_I32 : VOPCX_I32 , "V_CMPX_GT_I32">; +defm V_CMPX_NE_I32 : VOPCX_I32 , "V_CMPX_NE_I32">; +defm V_CMPX_GE_I32 : VOPCX_I32 , "V_CMPX_GE_I32">; +defm V_CMPX_T_I32 : VOPCX_I32 , "V_CMPX_T_I32">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; -defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; -defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; -defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; -defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; -defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; -defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; -defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; +defm V_CMP_F_I64 : VOPC_I64 , "V_CMP_F_I64">; +defm V_CMP_LT_I64 : VOPC_I64 , "V_CMP_LT_I64", COND_SLT>; +defm V_CMP_EQ_I64 : VOPC_I64 , "V_CMP_EQ_I64", COND_EQ>; +defm V_CMP_LE_I64 : VOPC_I64 , "V_CMP_LE_I64", COND_SLE>; +defm V_CMP_GT_I64 : VOPC_I64 , "V_CMP_GT_I64", COND_SGT>; +defm V_CMP_NE_I64 : VOPC_I64 , "V_CMP_NE_I64", COND_NE>; +defm V_CMP_GE_I64 : VOPC_I64 , "V_CMP_GE_I64", COND_SGE>; +defm V_CMP_T_I64 : VOPC_I64 , "V_CMP_T_I64">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; -defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; -defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; -defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; -defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; -defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; -defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; -defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; +defm V_CMPX_F_I64 : VOPCX_I64 , "V_CMPX_F_I64">; +defm V_CMPX_LT_I64 : VOPCX_I64 , "V_CMPX_LT_I64">; +defm V_CMPX_EQ_I64 : VOPCX_I64 , "V_CMPX_EQ_I64">; +defm V_CMPX_LE_I64 : VOPCX_I64 , "V_CMPX_LE_I64">; +defm V_CMPX_GT_I64 : VOPCX_I64 , "V_CMPX_GT_I64">; +defm V_CMPX_NE_I64 : VOPCX_I64 , "V_CMPX_NE_I64">; +defm V_CMPX_GE_I64 : VOPCX_I64 , "V_CMPX_GE_I64">; +defm V_CMPX_T_I64 : VOPCX_I64 , "V_CMPX_T_I64">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; -defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; -defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; -defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; -defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; -defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; -defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; -defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; +defm V_CMP_F_U32 : VOPC_I32 , "V_CMP_F_U32">; +defm V_CMP_LT_U32 : VOPC_I32 , "V_CMP_LT_U32", COND_ULT>; +defm V_CMP_EQ_U32 : VOPC_I32 , "V_CMP_EQ_U32", COND_EQ>; +defm V_CMP_LE_U32 : VOPC_I32 , "V_CMP_LE_U32", COND_ULE>; +defm V_CMP_GT_U32 : VOPC_I32 , "V_CMP_GT_U32", COND_UGT>; +defm V_CMP_NE_U32 : VOPC_I32 , "V_CMP_NE_U32", COND_NE>; +defm V_CMP_GE_U32 : VOPC_I32 , "V_CMP_GE_U32", COND_UGE>; +defm V_CMP_T_U32 : VOPC_I32 , "V_CMP_T_U32">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; -defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; -defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; -defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; -defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; -defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; -defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; -defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; +defm V_CMPX_F_U32 : VOPCX_I32 , "V_CMPX_F_U32">; +defm V_CMPX_LT_U32 : VOPCX_I32 , "V_CMPX_LT_U32">; +defm V_CMPX_EQ_U32 : VOPCX_I32 , "V_CMPX_EQ_U32">; +defm V_CMPX_LE_U32 : VOPCX_I32 , "V_CMPX_LE_U32">; +defm V_CMPX_GT_U32 : VOPCX_I32 , "V_CMPX_GT_U32">; +defm V_CMPX_NE_U32 : VOPCX_I32 , "V_CMPX_NE_U32">; +defm V_CMPX_GE_U32 : VOPCX_I32 , "V_CMPX_GE_U32">; +defm V_CMPX_T_U32 : VOPCX_I32 , "V_CMPX_T_U32">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; -defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; -defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; -defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; -defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; -defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; -defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; -defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; +defm V_CMP_F_U64 : VOPC_I64 , "V_CMP_F_U64">; +defm V_CMP_LT_U64 : VOPC_I64 , "V_CMP_LT_U64", COND_ULT>; +defm V_CMP_EQ_U64 : VOPC_I64 , "V_CMP_EQ_U64", COND_EQ>; +defm V_CMP_LE_U64 : VOPC_I64 , "V_CMP_LE_U64", COND_ULE>; +defm V_CMP_GT_U64 : VOPC_I64 , "V_CMP_GT_U64", COND_UGT>; +defm V_CMP_NE_U64 : VOPC_I64 , "V_CMP_NE_U64", COND_NE>; +defm V_CMP_GE_U64 : VOPC_I64 , "V_CMP_GE_U64", COND_UGE>; +defm V_CMP_T_U64 : VOPC_I64 , "V_CMP_T_U64">; -let hasSideEffects = 1, Defs = [EXEC] in { +let hasSideEffects = 1 in { -defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; -defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; -defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; -defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; -defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; -defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; -defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; -defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; +defm V_CMPX_F_U64 : VOPCX_I64 , "V_CMPX_F_U64">; +defm V_CMPX_LT_U64 : VOPCX_I64 , "V_CMPX_LT_U64">; +defm V_CMPX_EQ_U64 : VOPCX_I64 , "V_CMPX_EQ_U64">; +defm V_CMPX_LE_U64 : VOPCX_I64 , "V_CMPX_LE_U64">; +defm V_CMPX_GT_U64 : VOPCX_I64 , "V_CMPX_GT_U64">; +defm V_CMPX_NE_U64 : VOPCX_I64 , "V_CMPX_NE_U64">; +defm V_CMPX_GE_U64 : VOPCX_I64 , "V_CMPX_GE_U64">; +defm V_CMPX_T_U64 : VOPCX_I64 , "V_CMPX_T_U64">; -} // End hasSideEffects = 1, Defs = [EXEC] +} // End hasSideEffects = 1 -defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; +defm V_CMP_CLASS_F32 : VOPC_F32 , "V_CMP_CLASS_F32">; -let hasSideEffects = 1, Defs = [EXEC] in { -defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; -} // End hasSideEffects = 1, Defs = [EXEC] +let hasSideEffects = 1 in { +defm V_CMPX_CLASS_F32 : VOPCX_F32 , "V_CMPX_CLASS_F32">; +} // End hasSideEffects = 1 -defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; +defm V_CMP_CLASS_F64 : VOPC_F64 , "V_CMP_CLASS_F64">; -let hasSideEffects = 1, Defs = [EXEC] in { -defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; -} // End hasSideEffects = 1, Defs = [EXEC] +let hasSideEffects = 1 in { +defm V_CMPX_CLASS_F64 : VOPCX_F64 , "V_CMPX_CLASS_F64">; +} // End hasSideEffects = 1 } // End isCompare = 1 @@ -712,8 +728,97 @@ defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; // DS Instructions //===----------------------------------------------------------------------===// -def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; -def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; + +def DS_ADD_U32 : DS_1A1D_NORET <0x0, "DS_ADD_U32", VReg_32>; +def DS_SUB_U32 : DS_1A1D_NORET <0x1, "DS_SUB_U32", VReg_32>; +def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "DS_RSUB_U32", VReg_32>; +def DS_INC_U32 : DS_1A1D_NORET <0x3, "DS_INC_U32", VReg_32>; +def DS_DEC_U32 : DS_1A1D_NORET <0x4, "DS_DEC_U32", VReg_32>; +def DS_MIN_I32 : DS_1A1D_NORET <0x5, "DS_MIN_I32", VReg_32>; +def DS_MAX_I32 : DS_1A1D_NORET <0x6, "DS_MAX_I32", VReg_32>; +def DS_MIN_U32 : DS_1A1D_NORET <0x7, "DS_MIN_U32", VReg_32>; +def DS_MAX_U32 : DS_1A1D_NORET <0x8, "DS_MAX_U32", VReg_32>; +def DS_AND_B32 : DS_1A1D_NORET <0x9, "DS_AND_B32", VReg_32>; +def DS_OR_B32 : DS_1A1D_NORET <0xa, "DS_OR_B32", VReg_32>; +def DS_XOR_B32 : DS_1A1D_NORET <0xb, "DS_XOR_B32", VReg_32>; +def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "DS_MSKOR_B32", VReg_32>; +def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "DS_CMPST_B32", VReg_32>; +def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "DS_CMPST_F32", VReg_32>; +def DS_MIN_F32 : DS_1A1D_NORET <0x12, "DS_MIN_F32", VReg_32>; +def DS_MAX_F32 : DS_1A1D_NORET <0x13, "DS_MAX_F32", VReg_32>; + +def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "DS_ADD_RTN_U32", VReg_32, "DS_ADD_U32">; +def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "DS_SUB_RTN_U32", VReg_32, "DS_SUB_U32">; +def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "DS_RSUB_RTN_U32", VReg_32, "DS_RSUB_U32">; +def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "DS_INC_RTN_U32", VReg_32, "DS_INC_U32">; +def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "DS_DEC_RTN_U32", VReg_32, "DS_DEC_U32">; +def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "DS_MIN_RTN_I32", VReg_32, "DS_MIN_I32">; +def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "DS_MAX_RTN_I32", VReg_32, "DS_MAX_I32">; +def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "DS_MIN_RTN_U32", VReg_32, "DS_MIN_U32">; +def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "DS_MAX_RTN_U32", VReg_32, "DS_MAX_U32">; +def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "DS_AND_RTN_B32", VReg_32, "DS_AND_B32">; +def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "DS_OR_RTN_B32", VReg_32, "DS_OR_B32">; +def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "DS_XOR_RTN_B32", VReg_32, "DS_XOR_B32">; +def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "DS_MSKOR_RTN_B32", VReg_32, "DS_MSKOR_B32">; +def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "DS_WRXCHG_RTN_B32", VReg_32>; +//def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2_B32">; +//def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "DS_WRXCHG2_RTN_B32", VReg_32, "DS_WRXCHG2ST64_B32">; +def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "DS_CMPST_RTN_B32", VReg_32, "DS_CMPST_B32">; +def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "DS_CMPST_RTN_F32", VReg_32, "DS_CMPST_F32">; +def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "DS_MIN_RTN_F32", VReg_32, "DS_MIN_F32">; +def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "DS_MAX_RTN_F32", VReg_32, "DS_MAX_F32">; + +let SubtargetPredicate = isCI in { +def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "DS_WRAP_RTN_F32", VReg_32, "DS_WRAP_F32">; +} // End isCI + + +def DS_ADD_U64 : DS_1A1D_NORET <0x40, "DS_ADD_U64", VReg_64>; +def DS_SUB_U64 : DS_1A1D_NORET <0x41, "DS_SUB_U64", VReg_64>; +def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "DS_RSUB_U64", VReg_64>; +def DS_INC_U64 : DS_1A1D_NORET <0x43, "DS_INC_U64", VReg_64>; +def DS_DEC_U64 : DS_1A1D_NORET <0x44, "DS_DEC_U64", VReg_64>; +def DS_MIN_I64 : DS_1A1D_NORET <0x45, "DS_MIN_I64", VReg_64>; +def DS_MAX_I64 : DS_1A1D_NORET <0x46, "DS_MAX_I64", VReg_64>; +def DS_MIN_U64 : DS_1A1D_NORET <0x47, "DS_MIN_U64", VReg_64>; +def DS_MAX_U64 : DS_1A1D_NORET <0x48, "DS_MAX_U64", VReg_64>; +def DS_AND_B64 : DS_1A1D_NORET <0x49, "DS_AND_B64", VReg_64>; +def DS_OR_B64 : DS_1A1D_NORET <0x4a, "DS_OR_B64", VReg_64>; +def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "DS_XOR_B64", VReg_64>; +def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "DS_MSKOR_B64", VReg_64>; +def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "DS_CMPST_B64", VReg_64>; +def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "DS_CMPST_F64", VReg_64>; +def DS_MIN_F64 : DS_1A1D_NORET <0x52, "DS_MIN_F64", VReg_64>; +def DS_MAX_F64 : DS_1A1D_NORET <0x53, "DS_MAX_F64", VReg_64>; + +def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "DS_ADD_RTN_U64", VReg_64, "DS_ADD_U64">; +def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "DS_SUB_RTN_U64", VReg_64, "DS_SUB_U64">; +def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "DS_RSUB_RTN_U64", VReg_64, "DS_RSUB_U64">; +def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "DS_INC_RTN_U64", VReg_64, "DS_INC_U64">; +def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "DS_DEC_RTN_U64", VReg_64, "DS_DEC_U64">; +def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "DS_MIN_RTN_I64", VReg_64, "DS_MIN_I64">; +def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "DS_MAX_RTN_I64", VReg_64, "DS_MAX_I64">; +def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "DS_MIN_RTN_U64", VReg_64, "DS_MIN_U64">; +def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "DS_MAX_RTN_U64", VReg_64, "DS_MAX_U64">; +def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "DS_AND_RTN_B64", VReg_64, "DS_AND_B64">; +def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "DS_OR_RTN_B64", VReg_64, "DS_OR_B64">; +def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "DS_XOR_RTN_B64", VReg_64, "DS_XOR_B64">; +def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "DS_MSKOR_RTN_B64", VReg_64, "DS_MSKOR_B64">; +def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "DS_WRXCHG_RTN_B64", VReg_64, "DS_WRXCHG_B64">; +//def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2_B64">; +//def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "DS_WRXCHG2_RTN_B64", VReg_64, "DS_WRXCHG2ST64_B64">; +def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "DS_CMPST_RTN_B64", VReg_64, "DS_CMPST_B64">; +def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "DS_CMPST_RTN_F64", VReg_64, "DS_CMPST_F64">; +def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "DS_MIN_F64", VReg_64, "DS_MIN_F64">; +def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "DS_MAX_F64", VReg_64, "DS_MAX_F64">; + +//let SubtargetPredicate = isCI in { +// DS_CONDXCHG32_RTN_B64 +// DS_CONDXCHG32_RTN_B128 +//} // End isCI + +// TODO: _SRC2_* forms + def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; @@ -727,14 +832,15 @@ def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; def DS_READ_B64 : DS_Load_Helper <0x00000076, "DS_READ_B64", VReg_64>; // 2 forms. -def DS_WRITE2_B32 : DS_Load2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_64>; -def DS_WRITE2_B64 : DS_Load2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_128>; +def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "DS_WRITE2_B32", VReg_32>; +def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "DS_WRITE2ST64_B32", VReg_32>; +def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "DS_WRITE2_B64", VReg_64>; +def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "DS_WRITE2ST64_B64", VReg_64>; def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "DS_READ2_B32", VReg_64>; +def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "DS_READ2ST64_B32", VReg_64>; def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>; - -// TODO: DS_READ2ST64_B32, DS_READ2ST64_B64, -// DS_WRITE2ST64_B32, DS_WRITE2ST64_B64 +def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "DS_READ2ST64_B64", VReg_128>; //===----------------------------------------------------------------------===// // MUBUF Instructions @@ -748,45 +854,80 @@ defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMA //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; -defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; -defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; -defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; -defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; -defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; -defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; -defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; +defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < + 0x00000008, "BUFFER_LOAD_UBYTE", VReg_32, i32, az_extloadi8_global +>; +defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < + 0x00000009, "BUFFER_LOAD_SBYTE", VReg_32, i32, sextloadi8_global +>; +defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < + 0x0000000a, "BUFFER_LOAD_USHORT", VReg_32, i32, az_extloadi16_global +>; +defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < + 0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32, i32, sextloadi16_global +>; +defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < + 0x0000000c, "BUFFER_LOAD_DWORD", VReg_32, i32, global_load +>; +defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < + 0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64, v2i32, global_load +>; +defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < + 0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128, v4i32, global_load +>; -def BUFFER_STORE_BYTE : MUBUF_Store_Helper < - 0x00000018, "BUFFER_STORE_BYTE", VReg_32 +defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < + 0x00000018, "BUFFER_STORE_BYTE", VReg_32, i32, truncstorei8_global >; -def BUFFER_STORE_SHORT : MUBUF_Store_Helper < - 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 +defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < + 0x0000001a, "BUFFER_STORE_SHORT", VReg_32, i32, truncstorei16_global >; -def BUFFER_STORE_DWORD : MUBUF_Store_Helper < - 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 +defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < + 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32, global_store >; -def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < - 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 +defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < + 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, v2i32, global_store >; -def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < - 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 +defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < + 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128, v4i32, global_store >; //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; +defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < + 0x00000030, "BUFFER_ATOMIC_SWAP", VReg_32, i32, atomic_swap_global +>; //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; -//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; -//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; +defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < + 0x00000032, "BUFFER_ATOMIC_ADD", VReg_32, i32, atomic_add_global +>; +defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < + 0x00000033, "BUFFER_ATOMIC_SUB", VReg_32, i32, atomic_sub_global +>; //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; -//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; -//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; -//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; -//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; -//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; -//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; -//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; +defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < + 0x00000035, "BUFFER_ATOMIC_SMIN", VReg_32, i32, atomic_min_global +>; +defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < + 0x00000036, "BUFFER_ATOMIC_UMIN", VReg_32, i32, atomic_umin_global +>; +defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < + 0x00000037, "BUFFER_ATOMIC_SMAX", VReg_32, i32, atomic_max_global +>; +defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < + 0x00000038, "BUFFER_ATOMIC_UMAX", VReg_32, i32, atomic_umax_global +>; +defm BUFFER_ATOMIC_AND : MUBUF_Atomic < + 0x00000039, "BUFFER_ATOMIC_AND", VReg_32, i32, atomic_and_global +>; +defm BUFFER_ATOMIC_OR : MUBUF_Atomic < + 0x0000003a, "BUFFER_ATOMIC_OR", VReg_32, i32, atomic_or_global +>; +defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < + 0x0000003b, "BUFFER_ATOMIC_XOR", VReg_32, i32, atomic_xor_global +>; //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; @@ -819,11 +960,11 @@ def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; -def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; -def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; -def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; -def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; -def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; +defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; +defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; +defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; +defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; +defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; //===----------------------------------------------------------------------===// // MIMG Instructions @@ -857,83 +998,157 @@ defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; -defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; -//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; -defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; -//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; -defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; -defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; -//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; -//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; -defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; -//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; -defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; -//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; -defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; -defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; -//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; -//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; -//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; -//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; -//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; -//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; -//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; -//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; -//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; -//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; -//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; -//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; -//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; -//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; -//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; -//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; -//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; -//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; -//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; -//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; -//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; -//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; -//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; -//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; -//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; -//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; -//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; -//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; -//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; -//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; -//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; -//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; -//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; -//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; -//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; -//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; -//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; -//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; -//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; -//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; -//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; -//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; -//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; -//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; -//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; -//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; -//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; -//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; -//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; -//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; -//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; +defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; +defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "IMAGE_SAMPLE_CL">; +defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; +defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "IMAGE_SAMPLE_D_CL">; +defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; +defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; +defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "IMAGE_SAMPLE_B_CL">; +defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "IMAGE_SAMPLE_LZ">; +defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; +defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "IMAGE_SAMPLE_C_CL">; +defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; +defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "IMAGE_SAMPLE_C_D_CL">; +defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; +defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; +defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "IMAGE_SAMPLE_C_B_CL">; +defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "IMAGE_SAMPLE_C_LZ">; +defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "IMAGE_SAMPLE_O">; +defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "IMAGE_SAMPLE_CL_O">; +defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "IMAGE_SAMPLE_D_O">; +defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "IMAGE_SAMPLE_D_CL_O">; +defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "IMAGE_SAMPLE_L_O">; +defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "IMAGE_SAMPLE_B_O">; +defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "IMAGE_SAMPLE_B_CL_O">; +defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "IMAGE_SAMPLE_LZ_O">; +defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "IMAGE_SAMPLE_C_O">; +defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "IMAGE_SAMPLE_C_CL_O">; +defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "IMAGE_SAMPLE_C_D_O">; +defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "IMAGE_SAMPLE_C_D_CL_O">; +defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "IMAGE_SAMPLE_C_L_O">; +defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "IMAGE_SAMPLE_C_B_O">; +defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "IMAGE_SAMPLE_C_B_CL_O">; +defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "IMAGE_SAMPLE_C_LZ_O">; +defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "IMAGE_GATHER4">; +defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "IMAGE_GATHER4_CL">; +defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "IMAGE_GATHER4_L">; +defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "IMAGE_GATHER4_B">; +defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "IMAGE_GATHER4_B_CL">; +defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "IMAGE_GATHER4_LZ">; +defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "IMAGE_GATHER4_C">; +defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "IMAGE_GATHER4_C_CL">; +defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "IMAGE_GATHER4_C_L">; +defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "IMAGE_GATHER4_C_B">; +defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "IMAGE_GATHER4_C_B_CL">; +defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "IMAGE_GATHER4_C_LZ">; +defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "IMAGE_GATHER4_O">; +defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "IMAGE_GATHER4_CL_O">; +defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "IMAGE_GATHER4_L_O">; +defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "IMAGE_GATHER4_B_O">; +defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "IMAGE_GATHER4_B_CL_O">; +defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "IMAGE_GATHER4_LZ_O">; +defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "IMAGE_GATHER4_C_O">; +defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "IMAGE_GATHER4_C_CL_O">; +defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "IMAGE_GATHER4_C_L_O">; +defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "IMAGE_GATHER4_C_B_O">; +defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "IMAGE_GATHER4_C_B_CL_O">; +defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "IMAGE_GATHER4_C_LZ_O">; +defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "IMAGE_GET_LOD">; +defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "IMAGE_SAMPLE_CD">; +defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "IMAGE_SAMPLE_CD_CL">; +defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "IMAGE_SAMPLE_C_CD">; +defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "IMAGE_SAMPLE_C_CD_CL">; +defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "IMAGE_SAMPLE_CD_O">; +defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "IMAGE_SAMPLE_CD_CL_O">; +defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "IMAGE_SAMPLE_C_CD_O">; +defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "IMAGE_SAMPLE_C_CD_CL_O">; //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; //def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; +//===----------------------------------------------------------------------===// +// Flat Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasFlatAddressSpace] in { +def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "FLAT_LOAD_UBYTE", VReg_32>; +def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "FLAT_LOAD_SBYTE", VReg_32>; +def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "FLAT_LOAD_USHORT", VReg_32>; +def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "FLAT_LOAD_SSHORT", VReg_32>; +def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "FLAT_LOAD_DWORD", VReg_32>; +def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "FLAT_LOAD_DWORDX2", VReg_64>; +def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "FLAT_LOAD_DWORDX4", VReg_128>; +def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "FLAT_LOAD_DWORDX3", VReg_96>; + +def FLAT_STORE_BYTE : FLAT_Store_Helper < + 0x00000018, "FLAT_STORE_BYTE", VReg_32 +>; + +def FLAT_STORE_SHORT : FLAT_Store_Helper < + 0x0000001a, "FLAT_STORE_SHORT", VReg_32 +>; + +def FLAT_STORE_DWORD : FLAT_Store_Helper < + 0x0000001c, "FLAT_STORE_DWORD", VReg_32 +>; + +def FLAT_STORE_DWORDX2 : FLAT_Store_Helper < + 0x0000001d, "FLAT_STORE_DWORDX2", VReg_64 +>; + +def FLAT_STORE_DWORDX4 : FLAT_Store_Helper < + 0x0000001e, "FLAT_STORE_DWORDX4", VReg_128 +>; + +def FLAT_STORE_DWORDX3 : FLAT_Store_Helper < + 0x0000001e, "FLAT_STORE_DWORDX3", VReg_96 +>; + +//def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "FLAT_ATOMIC_SWAP", []>; +//def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "FLAT_ATOMIC_CMPSWAP", []>; +//def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "FLAT_ATOMIC_ADD", []>; +//def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "FLAT_ATOMIC_SUB", []>; +//def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "FLAT_ATOMIC_RSUB", []>; +//def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "FLAT_ATOMIC_SMIN", []>; +//def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "FLAT_ATOMIC_UMIN", []>; +//def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "FLAT_ATOMIC_SMAX", []>; +//def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "FLAT_ATOMIC_UMAX", []>; +//def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "FLAT_ATOMIC_AND", []>; +//def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "FLAT_ATOMIC_OR", []>; +//def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "FLAT_ATOMIC_XOR", []>; +//def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "FLAT_ATOMIC_INC", []>; +//def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "FLAT_ATOMIC_DEC", []>; +//def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "FLAT_ATOMIC_FCMPSWAP", []>; +//def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "FLAT_ATOMIC_FMIN", []>; +//def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "FLAT_ATOMIC_FMAX", []>; +//def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "FLAT_ATOMIC_SWAP_X2", []>; +//def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "FLAT_ATOMIC_CMPSWAP_X2", []>; +//def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "FLAT_ATOMIC_ADD_X2", []>; +//def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "FLAT_ATOMIC_SUB_X2", []>; +//def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "FLAT_ATOMIC_RSUB_X2", []>; +//def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "FLAT_ATOMIC_SMIN_X2", []>; +//def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "FLAT_ATOMIC_UMIN_X2", []>; +//def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "FLAT_ATOMIC_SMAX_X2", []>; +//def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "FLAT_ATOMIC_UMAX_X2", []>; +//def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "FLAT_ATOMIC_AND_X2", []>; +//def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "FLAT_ATOMIC_OR_X2", []>; +//def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "FLAT_ATOMIC_XOR_X2", []>; +//def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "FLAT_ATOMIC_INC_X2", []>; +//def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "FLAT_ATOMIC_DEC_X2", []>; +//def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "FLAT_ATOMIC_FCMPSWAP_X2", []>; +//def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "FLAT_ATOMIC_FMIN_X2", []>; +//def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "FLAT_ATOMIC_FMAX_X2", []>; + +} // End HasFlatAddressSpace predicate //===----------------------------------------------------------------------===// // VOP1 Instructions //===----------------------------------------------------------------------===// //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; -let neverHasSideEffects = 1, isMoveImm = 1 in { -defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; -} // End neverHasSideEffects = 1, isMoveImm = 1 +let isMoveImm = 1 in { +defm V_MOV_B32 : VOP1Inst , "V_MOV_B32", VOP_I32_I32>; +} // End isMoveImm = 1 let Uses = [EXEC] in { @@ -947,113 +1162,133 @@ def V_READFIRSTLANE_B32 : VOP1 < } -defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", - [(set i32:$dst, (fp_to_sint f64:$src0))] +defm V_CVT_I32_F64 : VOP1Inst , "V_CVT_I32_F64", + VOP_I32_F64, fp_to_sint >; -defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", - [(set f64:$dst, (sint_to_fp i32:$src0))] +defm V_CVT_F64_I32 : VOP1Inst , "V_CVT_F64_I32", + VOP_F64_I32, sint_to_fp >; -defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", - [(set f32:$dst, (sint_to_fp i32:$src0))] +defm V_CVT_F32_I32 : VOP1Inst , "V_CVT_F32_I32", + VOP_F32_I32, sint_to_fp >; -defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", - [(set f32:$dst, (uint_to_fp i32:$src0))] +defm V_CVT_F32_U32 : VOP1Inst , "V_CVT_F32_U32", + VOP_F32_I32, uint_to_fp >; -defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", - [(set i32:$dst, (fp_to_uint f32:$src0))] +defm V_CVT_U32_F32 : VOP1Inst , "V_CVT_U32_F32", + VOP_I32_F32, fp_to_uint >; -defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", - [(set i32:$dst, (fp_to_sint f32:$src0))] +defm V_CVT_I32_F32 : VOP1Inst , "V_CVT_I32_F32", + VOP_I32_F32, fp_to_sint +>; +defm V_MOV_FED_B32 : VOP1Inst , "V_MOV_FED_B32", VOP_I32_I32>; +defm V_CVT_F16_F32 : VOP1Inst , "V_CVT_F16_F32", + VOP_I32_F32, fp_to_f16 +>; +defm V_CVT_F32_F16 : VOP1Inst , "V_CVT_F32_F16", + VOP_F32_I32, f16_to_fp >; -defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; -////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; -//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; -defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", - [(set f32:$dst, (fround f64:$src0))] +defm V_CVT_F32_F64 : VOP1Inst , "V_CVT_F32_F64", + VOP_F32_F64, fround +>; +defm V_CVT_F64_F32 : VOP1Inst , "V_CVT_F64_F32", + VOP_F64_F32, fextend +>; +defm V_CVT_F32_UBYTE0 : VOP1Inst , "V_CVT_F32_UBYTE0", + VOP_F32_I32, AMDGPUcvt_f32_ubyte0 +>; +defm V_CVT_F32_UBYTE1 : VOP1Inst , "V_CVT_F32_UBYTE1", + VOP_F32_I32, AMDGPUcvt_f32_ubyte1 +>; +defm V_CVT_F32_UBYTE2 : VOP1Inst , "V_CVT_F32_UBYTE2", + VOP_F32_I32, AMDGPUcvt_f32_ubyte2 >; -defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", - [(set f64:$dst, (fextend f32:$src0))] +defm V_CVT_F32_UBYTE3 : VOP1Inst , "V_CVT_F32_UBYTE3", + VOP_F32_I32, AMDGPUcvt_f32_ubyte3 >; -//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; -//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; -//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; -//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; -defm V_CVT_U32_F64 : VOP1_32_64 <0x00000015, "V_CVT_U32_F64", - [(set i32:$dst, (fp_to_uint f64:$src0))] +defm V_CVT_U32_F64 : VOP1Inst , "V_CVT_U32_F64", + VOP_I32_F64, fp_to_uint >; -defm V_CVT_F64_U32 : VOP1_64_32 <0x00000016, "V_CVT_F64_U32", - [(set f64:$dst, (uint_to_fp i32:$src0))] +defm V_CVT_F64_U32 : VOP1Inst , "V_CVT_F64_U32", + VOP_F64_I32, uint_to_fp >; -defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", - [(set f32:$dst, (AMDGPUfract f32:$src0))] +defm V_FRACT_F32 : VOP1Inst , "V_FRACT_F32", + VOP_F32_F32, AMDGPUfract >; -defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", - [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] +defm V_TRUNC_F32 : VOP1Inst , "V_TRUNC_F32", + VOP_F32_F32, ftrunc >; -defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", - [(set f32:$dst, (fceil f32:$src0))] +defm V_CEIL_F32 : VOP1Inst , "V_CEIL_F32", + VOP_F32_F32, fceil >; -defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", - [(set f32:$dst, (frint f32:$src0))] +defm V_RNDNE_F32 : VOP1Inst , "V_RNDNE_F32", + VOP_F32_F32, frint +>; +defm V_FLOOR_F32 : VOP1Inst , "V_FLOOR_F32", + VOP_F32_F32, ffloor +>; +defm V_EXP_F32 : VOP1Inst , "V_EXP_F32", + VOP_F32_F32, fexp2 +>; +defm V_LOG_CLAMP_F32 : VOP1Inst , "V_LOG_CLAMP_F32", VOP_F32_F32>; +defm V_LOG_F32 : VOP1Inst , "V_LOG_F32", + VOP_F32_F32, flog2 +>; + +defm V_RCP_CLAMP_F32 : VOP1Inst , "V_RCP_CLAMP_F32", VOP_F32_F32>; +defm V_RCP_LEGACY_F32 : VOP1Inst , "V_RCP_LEGACY_F32", VOP_F32_F32>; +defm V_RCP_F32 : VOP1Inst , "V_RCP_F32", + VOP_F32_F32, AMDGPUrcp >; -defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", - [(set f32:$dst, (ffloor f32:$src0))] +defm V_RCP_IFLAG_F32 : VOP1Inst , "V_RCP_IFLAG_F32", VOP_F32_F32>; +defm V_RSQ_CLAMP_F32 : VOP1Inst , "V_RSQ_CLAMP_F32", + VOP_F32_F32, AMDGPUrsq_clamped >; -defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", - [(set f32:$dst, (fexp2 f32:$src0))] +defm V_RSQ_LEGACY_F32 : VOP1Inst , "V_RSQ_LEGACY_F32", + VOP_F32_F32, AMDGPUrsq_legacy >; -defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; -defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", - [(set f32:$dst, (flog2 f32:$src0))] +defm V_RSQ_F32 : VOP1Inst , "V_RSQ_F32", + VOP_F32_F32, AMDGPUrsq >; -defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; -defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; -defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", - [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] +defm V_RCP_F64 : VOP1Inst , "V_RCP_F64", + VOP_F64_F64, AMDGPUrcp >; -defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; -defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; -defm V_RSQ_LEGACY_F32 : VOP1_32 < - 0x0000002d, "V_RSQ_LEGACY_F32", - [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] +defm V_RCP_CLAMP_F64 : VOP1Inst , "V_RCP_CLAMP_F64", VOP_F64_F64>; +defm V_RSQ_F64 : VOP1Inst , "V_RSQ_F64", + VOP_F64_F64, AMDGPUrsq >; -defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", - [(set f32:$dst, (fdiv FP_ONE, (fsqrt f32:$src0)))] +defm V_RSQ_CLAMP_F64 : VOP1Inst , "V_RSQ_CLAMP_F64", + VOP_F64_F64, AMDGPUrsq_clamped >; -defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", - [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] +defm V_SQRT_F32 : VOP1Inst , "V_SQRT_F32", + VOP_F32_F32, fsqrt >; -defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; -defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", - [(set f64:$dst, (fdiv FP_ONE, (fsqrt f64:$src0)))] +defm V_SQRT_F64 : VOP1Inst , "V_SQRT_F64", + VOP_F64_F64, fsqrt >; -defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; -defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", - [(set f32:$dst, (fsqrt f32:$src0))] +defm V_SIN_F32 : VOP1Inst , "V_SIN_F32", + VOP_F32_F32, AMDGPUsin >; -defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", - [(set f64:$dst, (fsqrt f64:$src0))] +defm V_COS_F32 : VOP1Inst , "V_COS_F32", + VOP_F32_F32, AMDGPUcos >; -defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; -defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; -defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; -defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; -defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; -defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; -defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; -//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; -defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; -defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; -//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; -defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; +defm V_NOT_B32 : VOP1Inst , "V_NOT_B32", VOP_I32_I32>; +defm V_BFREV_B32 : VOP1Inst , "V_BFREV_B32", VOP_I32_I32>; +defm V_FFBH_U32 : VOP1Inst , "V_FFBH_U32", VOP_I32_I32>; +defm V_FFBL_B32 : VOP1Inst , "V_FFBL_B32", VOP_I32_I32>; +defm V_FFBH_I32 : VOP1Inst , "V_FFBH_I32", VOP_I32_I32>; +//defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>; +defm V_FREXP_MANT_F64 : VOP1Inst , "V_FREXP_MANT_F64", VOP_F64_F64>; +defm V_FRACT_F64 : VOP1Inst , "V_FRACT_F64", VOP_F64_F64>; +//defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>; +defm V_FREXP_MANT_F32 : VOP1Inst , "V_FREXP_MANT_F32", VOP_F32_F32>; //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; -defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; -defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; -defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; +defm V_MOVRELD_B32 : VOP1Inst , "V_MOVRELD_B32", VOP_I32_I32>; +defm V_MOVRELS_B32 : VOP1Inst , "V_MOVRELS_B32", VOP_I32_I32>; +defm V_MOVRELSD_B32 : VOP1Inst , "V_MOVRELSD_B32", VOP_I32_I32>; //===----------------------------------------------------------------------===// @@ -1103,9 +1338,8 @@ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), } def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), - (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, - InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), - "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", + (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2), + "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2", [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] > { let src0_modifiers = 0; @@ -1130,125 +1364,137 @@ def V_WRITELANE_B32 : VOP2 < >; let isCommutable = 1 in { -defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", - [(set f32:$dst, (fadd f32:$src0, f32:$src1))] +defm V_ADD_F32 : VOP2Inst , "V_ADD_F32", + VOP_F32_F32_F32, fadd >; -defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", - [(set f32:$dst, (fsub f32:$src0, f32:$src1))] +defm V_SUB_F32 : VOP2Inst , "V_SUB_F32", VOP_F32_F32_F32, fsub>; +defm V_SUBREV_F32 : VOP2Inst , "V_SUBREV_F32", + VOP_F32_F32_F32, null_frag, "V_SUB_F32" >; -defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; } // End isCommutable = 1 -defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; +defm V_MAC_LEGACY_F32 : VOP2Inst , "V_MAC_LEGACY_F32", + VOP_F32_F32_F32 +>; let isCommutable = 1 in { -defm V_MUL_LEGACY_F32 : VOP2_32 < - 0x00000007, "V_MUL_LEGACY_F32", - [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] +defm V_MUL_LEGACY_F32 : VOP2Inst , "V_MUL_LEGACY_F32", + VOP_F32_F32_F32, int_AMDGPU_mul >; -defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", - [(set f32:$dst, (fmul f32:$src0, f32:$src1))] +defm V_MUL_F32 : VOP2Inst , "V_MUL_F32", + VOP_F32_F32_F32, fmul >; -defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", - [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))] +defm V_MUL_I32_I24 : VOP2Inst , "V_MUL_I32_I24", + VOP_I32_I32_I32, AMDGPUmul_i24 >; //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; -defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", - [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))] +defm V_MUL_U32_U24 : VOP2Inst , "V_MUL_U32_U24", + VOP_I32_I32_I32, AMDGPUmul_u24 >; //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; -defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", - [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] +defm V_MIN_LEGACY_F32 : VOP2Inst , "V_MIN_LEGACY_F32", + VOP_F32_F32_F32, AMDGPUfmin >; -defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", - [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] +defm V_MAX_LEGACY_F32 : VOP2Inst , "V_MAX_LEGACY_F32", + VOP_F32_F32_F32, AMDGPUfmax >; -defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; -defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; -defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", - [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]>; -defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", - [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]>; -defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", - [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]>; -defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", - [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]>; +defm V_MIN_F32 : VOP2Inst , "V_MIN_F32", VOP_F32_F32_F32, fminnum>; +defm V_MAX_F32 : VOP2Inst , "V_MAX_F32", VOP_F32_F32_F32, fmaxnum>; +defm V_MIN_I32 : VOP2Inst , "V_MIN_I32", VOP_I32_I32_I32, AMDGPUsmin>; +defm V_MAX_I32 : VOP2Inst , "V_MAX_I32", VOP_I32_I32_I32, AMDGPUsmax>; +defm V_MIN_U32 : VOP2Inst , "V_MIN_U32", VOP_I32_I32_I32, AMDGPUumin>; +defm V_MAX_U32 : VOP2Inst , "V_MAX_U32", VOP_I32_I32_I32, AMDGPUumax>; -defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", - [(set i32:$dst, (srl i32:$src0, i32:$src1))] ->; +defm V_LSHR_B32 : VOP2Inst , "V_LSHR_B32", VOP_I32_I32_I32, srl>; -defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; +defm V_LSHRREV_B32 : VOP2Inst < + vop2<0x16>, "V_LSHRREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHR_B32" +>; -defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", - [(set i32:$dst, (sra i32:$src0, i32:$src1))] +defm V_ASHR_I32 : VOP2Inst , "V_ASHR_I32", + VOP_I32_I32_I32, sra +>; +defm V_ASHRREV_I32 : VOP2Inst < + vop2<0x18>, "V_ASHRREV_I32", VOP_I32_I32_I32, null_frag, "V_ASHR_I32" >; -defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; let hasPostISelHook = 1 in { -defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", - [(set i32:$dst, (shl i32:$src0, i32:$src1))] ->; +defm V_LSHL_B32 : VOP2Inst , "V_LSHL_B32", VOP_I32_I32_I32, shl>; } -defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; +defm V_LSHLREV_B32 : VOP2Inst < + vop2<0x1a>, "V_LSHLREV_B32", VOP_I32_I32_I32, null_frag, "V_LSHL_B32" +>; -defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", - [(set i32:$dst, (and i32:$src0, i32:$src1))]>; -defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", - [(set i32:$dst, (or i32:$src0, i32:$src1))] +defm V_AND_B32 : VOP2Inst , "V_AND_B32", + VOP_I32_I32_I32, and>; +defm V_OR_B32 : VOP2Inst , "V_OR_B32", + VOP_I32_I32_I32, or >; -defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", - [(set i32:$dst, (xor i32:$src0, i32:$src1))] +defm V_XOR_B32 : VOP2Inst , "V_XOR_B32", + VOP_I32_I32_I32, xor >; } // End isCommutable = 1 -defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", - [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; -defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; -defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; -defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; -defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; -defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; -defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; +defm V_BFM_B32 : VOP2Inst , "V_BFM_B32", + VOP_I32_I32_I32, AMDGPUbfm>; +defm V_MAC_F32 : VOP2Inst , "V_MAC_F32", VOP_F32_F32_F32>; +defm V_MADMK_F32 : VOP2Inst , "V_MADMK_F32", VOP_F32_F32_F32>; +defm V_MADAK_F32 : VOP2Inst , "V_MADAK_F32", VOP_F32_F32_F32>; +defm V_BCNT_U32_B32 : VOP2Inst , "V_BCNT_U32_B32", VOP_I32_I32_I32>; +defm V_MBCNT_LO_U32_B32 : VOP2Inst , "V_MBCNT_LO_U32_B32", + VOP_I32_I32_I32 +>; +defm V_MBCNT_HI_U32_B32 : VOP2Inst , "V_MBCNT_HI_U32_B32", + VOP_I32_I32_I32 +>; let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC // No patterns so that the scalar instructions are always selected. // The scalar versions will be replaced with vector when needed later. -defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", - [(set i32:$dst, (add i32:$src0, i32:$src1))], VSrc_32>; -defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", - [(set i32:$dst, (sub i32:$src0, i32:$src1))], VSrc_32>; -defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32, - "V_SUB_I32">; +defm V_ADD_I32 : VOP2bInst , "V_ADD_I32", + VOP_I32_I32_I32, add +>; +defm V_SUB_I32 : VOP2bInst , "V_SUB_I32", + VOP_I32_I32_I32, sub +>; +defm V_SUBREV_I32 : VOP2bInst , "V_SUBREV_I32", + VOP_I32_I32_I32, null_frag, "V_SUB_I32" +>; let Uses = [VCC] in { // Carry-in comes from VCC -defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", - [(set i32:$dst, (adde i32:$src0, i32:$src1))], VReg_32>; -defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", - [(set i32:$dst, (sube i32:$src0, i32:$src1))], VReg_32>; -defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32, - "V_SUBB_U32">; +defm V_ADDC_U32 : VOP2bInst , "V_ADDC_U32", + VOP_I32_I32_I32_VCC, adde +>; +defm V_SUBB_U32 : VOP2bInst , "V_SUBB_U32", + VOP_I32_I32_I32_VCC, sube +>; +defm V_SUBBREV_U32 : VOP2bInst , "V_SUBBREV_U32", + VOP_I32_I32_I32_VCC, null_frag, "V_SUBB_U32" +>; + } // End Uses = [VCC] } // End isCommutable = 1, Defs = [VCC] -defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; +defm V_LDEXP_F32 : VOP2Inst , "V_LDEXP_F32", + VOP_F32_F32_I32, AMDGPUldexp +>; ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; -defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", - [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] +defm V_CVT_PKRTZ_F16_F32 : VOP2Inst , "V_CVT_PKRTZ_F16_F32", + VOP_I32_F32_F32, int_SI_packf16 >; ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; @@ -1257,46 +1503,55 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", // VOP3 Instructions //===----------------------------------------------------------------------===// -let neverHasSideEffects = 1 in { - -defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; -defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", - [(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))] +defm V_MAD_LEGACY_F32 : VOP3Inst , "V_MAD_LEGACY_F32", + VOP_F32_F32_F32_F32 >; -defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", - [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))] +defm V_MAD_F32 : VOP3Inst , "V_MAD_F32", + VOP_F32_F32_F32_F32, fmad >; -defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", - [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))] +defm V_MAD_I32_I24 : VOP3Inst , "V_MAD_I32_I24", + VOP_I32_I32_I32_I32, AMDGPUmad_i24 +>; +defm V_MAD_U32_U24 : VOP3Inst , "V_MAD_U32_U24", + VOP_I32_I32_I32_I32, AMDGPUmad_u24 >; -} // End neverHasSideEffects - -defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; -defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; -defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; -defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; - -let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in { -defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", - [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>; -defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", - [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>; -} - -defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", - [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>; -defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", - [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] +defm V_CUBEID_F32 : VOP3Inst , "V_CUBEID_F32", + VOP_F32_F32_F32_F32 +>; +defm V_CUBESC_F32 : VOP3Inst , "V_CUBESC_F32", + VOP_F32_F32_F32_F32 +>; +defm V_CUBETC_F32 : VOP3Inst , "V_CUBETC_F32", + VOP_F32_F32_F32_F32 +>; +defm V_CUBEMA_F32 : VOP3Inst , "V_CUBEMA_F32", + VOP_F32_F32_F32_F32 +>; +defm V_BFE_U32 : VOP3Inst , "V_BFE_U32", + VOP_I32_I32_I32_I32, AMDGPUbfe_u32 >; -def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", - [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] +defm V_BFE_I32 : VOP3Inst , "V_BFE_I32", + VOP_I32_I32_I32_I32, AMDGPUbfe_i32 +>; +defm V_BFI_B32 : VOP3Inst , "V_BFI_B32", + VOP_I32_I32_I32_I32, AMDGPUbfi +>; +defm V_FMA_F32 : VOP3Inst , "V_FMA_F32", + VOP_F32_F32_F32_F32, fma +>; +defm V_FMA_F64 : VOP3Inst , "V_FMA_F64", + VOP_F64_F64_F64_F64, fma >; //def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; -defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; - -defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; -defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; +defm V_ALIGNBIT_B32 : VOP3Inst , "V_ALIGNBIT_B32", + VOP_I32_I32_I32_I32 +>; +defm V_ALIGNBYTE_B32 : VOP3Inst , "V_ALIGNBYTE_B32", + VOP_I32_I32_I32_I32 +>; +defm V_MULLIT_F32 : VOP3Inst , "V_MULLIT_F32", + VOP_F32_F32_F32_F32>; ////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; ////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; ////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; @@ -1309,49 +1564,83 @@ defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; //def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; //def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; -defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; +defm V_SAD_U32 : VOP3Inst , "V_SAD_U32", + VOP_I32_I32_I32_I32 +>; ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; -defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; -def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; +defm V_DIV_FIXUP_F32 : VOP3Inst < + vop3<0x15f>, "V_DIV_FIXUP_F32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup +>; +defm V_DIV_FIXUP_F64 : VOP3Inst < + vop3<0x160>, "V_DIV_FIXUP_F64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup +>; -def V_LSHL_B64 : VOP3_64_32 <0x00000161, "V_LSHL_B64", - [(set i64:$dst, (shl i64:$src0, i32:$src1))] +defm V_LSHL_B64 : VOP3Inst , "V_LSHL_B64", + VOP_I64_I64_I32, shl >; -def V_LSHR_B64 : VOP3_64_32 <0x00000162, "V_LSHR_B64", - [(set i64:$dst, (srl i64:$src0, i32:$src1))] +defm V_LSHR_B64 : VOP3Inst , "V_LSHR_B64", + VOP_I64_I64_I32, srl >; -def V_ASHR_I64 : VOP3_64_32 <0x00000163, "V_ASHR_I64", - [(set i64:$dst, (sra i64:$src0, i32:$src1))] +defm V_ASHR_I64 : VOP3Inst , "V_ASHR_I64", + VOP_I64_I64_I32, sra >; let isCommutable = 1 in { -def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; -def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; -def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; -def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; +defm V_ADD_F64 : VOP3Inst , "V_ADD_F64", + VOP_F64_F64_F64, fadd +>; +defm V_MUL_F64 : VOP3Inst , "V_MUL_F64", + VOP_F64_F64_F64, fmul +>; + +defm V_MIN_F64 : VOP3Inst , "V_MIN_F64", + VOP_F64_F64_F64, fminnum +>; +defm V_MAX_F64 : VOP3Inst , "V_MAX_F64", + VOP_F64_F64_F64, fmaxnum +>; } // isCommutable = 1 -def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; +defm V_LDEXP_F64 : VOP3Inst , "V_LDEXP_F64", + VOP_F64_F64_I32, AMDGPUldexp +>; let isCommutable = 1 in { -defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; -defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; -defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; -defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; +defm V_MUL_LO_U32 : VOP3Inst , "V_MUL_LO_U32", + VOP_I32_I32_I32 +>; +defm V_MUL_HI_U32 : VOP3Inst , "V_MUL_HI_U32", + VOP_I32_I32_I32 +>; +defm V_MUL_LO_I32 : VOP3Inst , "V_MUL_LO_I32", + VOP_I32_I32_I32 +>; +defm V_MUL_HI_I32 : VOP3Inst , "V_MUL_HI_I32", + VOP_I32_I32_I32 +>; } // isCommutable = 1 -defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; -def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; -defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; -def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; +defm V_DIV_SCALE_F32 : VOP3b_32 , "V_DIV_SCALE_F32", []>; + +// Double precision division pre-scale. +defm V_DIV_SCALE_F64 : VOP3b_64 , "V_DIV_SCALE_F64", []>; + +defm V_DIV_FMAS_F32 : VOP3Inst , "V_DIV_FMAS_F32", + VOP_F32_F32_F32_F32, AMDGPUdiv_fmas +>; +defm V_DIV_FMAS_F64 : VOP3Inst , "V_DIV_FMAS_F64", + VOP_F64_F64_F64_F64, AMDGPUdiv_fmas +>; //def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; //def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; -def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; +defm V_TRIG_PREOP_F64 : VOP3Inst < + vop3<0x174>, "V_TRIG_PREOP_F64", VOP_F64_F64_I32, AMDGPUtrig_preop +>; //===----------------------------------------------------------------------===// // Pseudo Instructions @@ -1375,6 +1664,15 @@ def V_OR_I1 : InstSI < [(set i1:$dst, (or i1:$src0, i1:$src1))] >; +def V_XOR_I1 : InstSI < + (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "", + [(set i1:$dst, (xor i1:$src0, i1:$src1))] +>; + +let hasSideEffects = 1 in { +def SGPR_USE : InstSI <(outs),(ins), "", []>; +} + // SI pseudo instructions. These are used by the CFG structurizer pass // and should be lowered to ISA instructions prior to codegen. @@ -1508,7 +1806,7 @@ let usesCustomInserter = 1 in { // constant that can be used with the ADDR64 MUBUF instructions. def SI_ADDR64_RSRC : InstSI < (outs SReg_128:$srsrc), - (ins SReg_64:$ptr), + (ins SSrc_64:$ptr), "", [] >; @@ -1516,7 +1814,7 @@ def V_SUB_F64 : InstSI < (outs VReg_64:$dst), (ins VReg_64:$src0, VReg_64:$src1), "V_SUB_F64 $dst, $src0, $src1", - [] + [(set f64:$dst, (fsub f64:$src0, f64:$src1))] >; } // end usesCustomInserter @@ -1524,24 +1822,56 @@ def V_SUB_F64 : InstSI < multiclass SI_SPILL_SGPR { def _SAVE : InstSI < - (outs VReg_32:$dst), + (outs), (ins sgpr_class:$src, i32imm:$frame_idx), "", [] >; def _RESTORE : InstSI < (outs sgpr_class:$dst), - (ins VReg_32:$src, i32imm:$frame_idx), + (ins i32imm:$frame_idx), "", [] >; } +defm SI_SPILL_S32 : SI_SPILL_SGPR ; defm SI_SPILL_S64 : SI_SPILL_SGPR ; defm SI_SPILL_S128 : SI_SPILL_SGPR ; defm SI_SPILL_S256 : SI_SPILL_SGPR ; defm SI_SPILL_S512 : SI_SPILL_SGPR ; +multiclass SI_SPILL_VGPR { + def _SAVE : InstSI < + (outs), + (ins vgpr_class:$src, i32imm:$frame_idx), + "", [] + >; + + def _RESTORE : InstSI < + (outs vgpr_class:$dst), + (ins i32imm:$frame_idx), + "", [] + >; +} + +defm SI_SPILL_V32 : SI_SPILL_VGPR ; +defm SI_SPILL_V64 : SI_SPILL_VGPR ; +defm SI_SPILL_V96 : SI_SPILL_VGPR ; +defm SI_SPILL_V128 : SI_SPILL_VGPR ; +defm SI_SPILL_V256 : SI_SPILL_VGPR ; +defm SI_SPILL_V512 : SI_SPILL_VGPR ; + +let Defs = [SCC] in { + +def SI_CONSTDATA_PTR : InstSI < + (outs SReg_64:$dst), + (ins), + "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))] +>; + +} // End Defs = [SCC] + } // end IsCodeGenOnly, isPseudo } // end SubtargetPredicate = SI @@ -1550,7 +1880,9 @@ let Predicates = [isSI] in { def : Pat< (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), - (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) + (V_CNDMASK_B32_e64 $src2, $src1, + (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0, + DSTCLAMP.NONE, DSTOMOD.NONE)) >; def : Pat < @@ -1560,7 +1892,7 @@ def : Pat < /* int_SI_vs_load_input */ def : Pat< - (SIload_input v4i32:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), + (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) >; @@ -1572,11 +1904,6 @@ def : Pat < $src0, $src1, $src2, $src3) >; -def : Pat < - (f64 (fsub f64:$src0, f64:$src1)), - (V_SUB_F64 $src0, $src1) ->; - //===----------------------------------------------------------------------===// // SMRD Patterns //===----------------------------------------------------------------------===// @@ -1604,7 +1931,6 @@ multiclass SMRD_Pattern { defm : SMRD_Pattern ; defm : SMRD_Pattern ; -defm : SMRD_Pattern ; defm : SMRD_Pattern ; defm : SMRD_Pattern ; defm : SMRD_Pattern ; @@ -1623,40 +1949,193 @@ def : Pat < (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) >; +} // Predicates = [isSI] in { + //===----------------------------------------------------------------------===// -// SOP2 Patterns +// SOP1 Patterns //===----------------------------------------------------------------------===// def : Pat < - (i1 (xor i1:$src0, i1:$src1)), - (S_XOR_B64 $src0, $src1) + (i64 (ctpop i64:$src)), + (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (S_BCNT1_I32_B64 $src), sub0), + (S_MOV_B32 0), sub1) >; //===----------------------------------------------------------------------===// -// VOP2 Patterns +// SOP2 Patterns //===----------------------------------------------------------------------===// +// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector +// case, the sgpr-copies pass will fix this to use the vector version. def : Pat < - (or i64:$src0, i64:$src1), - (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), - (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub0), - (EXTRACT_SUBREG i64:$src1, sub0)), sub0), - (V_OR_B32_e32 (EXTRACT_SUBREG i64:$src0, sub1), - (EXTRACT_SUBREG i64:$src1, sub1)), sub1) + (i32 (addc i32:$src0, i32:$src1)), + (S_ADD_U32 $src0, $src1) >; -class SextInReg : Pat < - (sext_inreg i32:$src0, vt), - (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0)) +let Predicates = [isSI] in { + +//===----------------------------------------------------------------------===// +// SOPP Patterns +//===----------------------------------------------------------------------===// + +def : Pat < + (int_AMDGPU_barrier_global), + (S_BARRIER) >; -def : SextInReg ; -def : SextInReg ; +//===----------------------------------------------------------------------===// +// VOP1 Patterns +//===----------------------------------------------------------------------===// + +let Predicates = [UnsafeFPMath] in { +def : RcpPat; +defm : RsqPat; +defm : RsqPat; +} + +//===----------------------------------------------------------------------===// +// VOP2 Patterns +//===----------------------------------------------------------------------===// + +def : Pat < + (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), + (V_BCNT_U32_B32_e64 $popcnt, $val) +>; /********** ======================= **********/ /********** Image sampling patterns **********/ /********** ======================= **********/ +// Image + sampler +class SampleRawPattern : Pat < + (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, + i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), + (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da), + (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc), + $addr, $rsrc, $sampler) +>; + +multiclass SampleRawPatterns { + def : SampleRawPattern(opcode # _V4_V1), i32>; + def : SampleRawPattern(opcode # _V4_V2), v2i32>; + def : SampleRawPattern(opcode # _V4_V4), v4i32>; + def : SampleRawPattern(opcode # _V4_V8), v8i32>; + def : SampleRawPattern(opcode # _V4_V16), v16i32>; +} + +// Image only +class ImagePattern : Pat < + (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm, + i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), + (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da), + (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc), + $addr, $rsrc) +>; + +multiclass ImagePatterns { + def : ImagePattern(opcode # _V4_V1), i32>; + def : ImagePattern(opcode # _V4_V2), v2i32>; + def : ImagePattern(opcode # _V4_V4), v4i32>; +} + +// Basic sample +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; + +// Sample with comparison +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; + +// Sample with offsets +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; + +// Sample with comparison and offsets +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; +defm : SampleRawPatterns; + +// Gather opcodes +// Only the variants which make sense are defined. +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; + +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; + +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; + +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; + +def : SampleRawPattern; +def : SampleRawPattern; +def : SampleRawPattern; + +def : ImagePattern; +defm : ImagePatterns; +defm : ImagePatterns; + /* SIsample for simple 1D texture lookup */ def : Pat < (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm), @@ -1872,7 +2351,10 @@ def : BitConvert ; def : BitConvert ; def : BitConvert ; def : BitConvert ; - +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; +def : BitConvert ; def : BitConvert ; def : BitConvert ; @@ -1902,7 +2384,7 @@ def FCLAMP_SI : AMDGPUShaderInst < } def : Pat < - (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), + (AMDGPUclamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), (FCLAMP_SI f32:$src) >; @@ -1910,44 +2392,50 @@ def : Pat < /********** Floating point absolute/negative **********/ /********** ================================ **********/ -// Manipulate the sign bit directly, as e.g. using the source negation modifier -// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0, -// breaking the piglit *s-floatBitsToInt-neg* tests - -// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly -// removing these patterns +// Prevent expanding both fneg and fabs. +// FIXME: Should use S_OR_B32 def : Pat < (fneg (fabs f32:$src)), (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ >; -def FABS_SI : AMDGPUShaderInst < - (outs VReg_32:$dst), - (ins VSrc_32:$src0), - "FABS_SI $dst, $src0", - [] -> { - let usesCustomInserter = 1; -} +// FIXME: Should use S_OR_B32 +def : Pat < + (fneg (fabs f64:$src)), + (f64 (INSERT_SUBREG + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), + (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0), + (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), + (V_MOV_B32_e32 0x80000000)), sub1)) // Set sign bit. +>; def : Pat < (fabs f32:$src), - (FABS_SI f32:$src) + (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) >; -def FNEG_SI : AMDGPUShaderInst < - (outs VReg_32:$dst), - (ins VSrc_32:$src0), - "FNEG_SI $dst, $src0", - [] -> { - let usesCustomInserter = 1; -} - def : Pat < (fneg f32:$src), - (FNEG_SI f32:$src) + (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) +>; + +def : Pat < + (fabs f64:$src), + (f64 (INSERT_SUBREG + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), + (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0), + (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), + (V_MOV_B32_e32 0x7fffffff)), sub1)) // Set sign bit. +>; + +def : Pat < + (fneg f64:$src), + (f64 (INSERT_SUBREG + (INSERT_SUBREG (f64 (IMPLICIT_DEF)), + (i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0), + (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), + (V_MOV_B32_e32 0x80000000)), sub1)) >; /********** ================== **********/ @@ -2008,45 +2496,36 @@ def : Pat < (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) >; -def : Pat< - (fdiv f32:$src0, f32:$src1), - (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) ->; - def : Pat< (fdiv f64:$src0, f64:$src1), - (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) ->; - -def : Pat < - (fcos f32:$src0), - (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) ->; - -def : Pat < - (fsin f32:$src0), - (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) + (V_MUL_F64 0 /* src0_modifiers */, $src0, + 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1), + 0 /* clamp */, 0 /* omod */) >; def : Pat < (int_AMDGPU_cube v4f32:$src), (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), - (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub0), - (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub1), - (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub2), - (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), - (EXTRACT_SUBREG $src, sub1), - (EXTRACT_SUBREG $src, sub2)), - sub3) + (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1), + 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub0), + (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), + 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub1), + (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub2), + (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), + 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), + 0 /* clamp */, 0 /* omod */), + sub3) >; def : Pat < @@ -2065,7 +2544,7 @@ def : Ext32Pat ; // Offset in an 32Bit VGPR def : Pat < (SIload_constant v4i32:$sbase, i32:$voff), - (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0) + (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0) >; // The multiplication scales from [0,1] to the unsigned integer range @@ -2079,7 +2558,7 @@ def : Pat < def : Pat < (int_SI_tid), (V_MBCNT_HI_U32_B32_e32 0xffffffff, - (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0)) + (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) >; //===----------------------------------------------------------------------===// @@ -2089,31 +2568,19 @@ def : Pat < def : IMad24Pat; def : UMad24Pat; -def : Pat < - (fadd f64:$src0, f64:$src1), - (V_ADD_F64 $src0, $src1, (i64 0)) ->; - -def : Pat < - (fmul f64:$src0, f64:$src1), - (V_MUL_F64 $src0, $src1, (i64 0)) ->; - -def : Pat < - (mul i32:$src0, i32:$src1), - (V_MUL_LO_I32 $src0, $src1, (i32 0)) ->; - def : Pat < (mulhu i32:$src0, i32:$src1), - (V_MUL_HI_U32 $src0, $src1, (i32 0)) + (V_MUL_HI_U32 $src0, $src1) >; def : Pat < (mulhs i32:$src0, i32:$src1), - (V_MUL_HI_I32 $src0, $src1, (i32 0)) + (V_MUL_HI_I32 $src0, $src1) >; +def : Vop3ModPat; + + defm : BFIPatterns ; def : ROTRPattern ; @@ -2121,146 +2588,168 @@ def : ROTRPattern ; /********** Load/Store Patterns **********/ /********** ======================= **********/ -multiclass DSReadPat { - def : Pat < - (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))), - (inst (i1 0), $ptr, (as_i16imm $offset)) - >; +class DSReadPat : Pat < + (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), + (inst (i1 0), $ptr, (as_i16imm $offset)) +>; - def : Pat < - (frag i32:$src0), - (vt (inst 0, $src0, 0)) - >; -} +def : DSReadPat ; +def : DSReadPat ; +def : DSReadPat ; +def : DSReadPat ; +def : DSReadPat ; -defm : DSReadPat ; -defm : DSReadPat ; -defm : DSReadPat ; -defm : DSReadPat ; -defm : DSReadPat ; -defm : DSReadPat ; +let AddedComplexity = 100 in { -multiclass DSWritePat { - def : Pat < - (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))), - (inst (i1 0), $ptr, $value, (as_i16imm $offset)) - >; +def : DSReadPat ; - def : Pat < - (frag vt:$val, i32:$ptr), - (inst 0, $ptr, $val, 0) - >; -} +} // End AddedComplexity = 100 -defm : DSWritePat ; -defm : DSWritePat ; -defm : DSWritePat ; -defm : DSWritePat ; +def : Pat < + (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, + i8:$offset1))), + (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1) +>; -def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), - (DS_ADD_U32_RTN 0, $ptr, $val, 0)>; +class DSWritePat : Pat < + (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), + (inst (i1 0), $ptr, $value, (as_i16imm $offset)) +>; -def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), - (DS_SUB_U32_RTN 0, $ptr, $val, 0)>; +def : DSWritePat ; +def : DSWritePat ; +def : DSWritePat ; -//===----------------------------------------------------------------------===// -// MUBUF Patterns -//===----------------------------------------------------------------------===// +let AddedComplexity = 100 in { -multiclass MUBUFLoad_Pattern { - def : Pat < - (vt (global_ld (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset))), - (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset)) - >; +def : DSWritePat ; +} // End AddedComplexity = 100 - def : Pat < - (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), - (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) - >; +def : Pat < + (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, + i8:$offset1)), + (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0), + (EXTRACT_SUBREG $value, sub1), $offset0, $offset1) +>; - def : Pat < - (vt (global_ld i64:$ptr)), - (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) - >; +class DSAtomicRetPat : Pat < + (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), + (inst (i1 0), $ptr, $value, (as_i16imm $offset)) +>; - def : Pat < - (vt (global_ld (add i64:$ptr, i64:$offset))), - (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) - >; +// Special case of DSAtomicRetPat for add / sub 1 -> inc / dec +// +// We need to use something for the data0, so we set a register to +// -1. For the non-rtn variants, the manual says it does +// DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max +// will always do the increment so I'm assuming it's the same. +// +// We also load this -1 with s_mov_b32 / s_mov_b64 even though this +// needs to be a VGPR. The SGPR copy pass will fix this, and it's +// easier since there is no v_mov_b64. +class DSAtomicIncRetPat : Pat < + (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)), + (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset)) +>; - def : Pat < - (vt (constant_ld (add i64:$ptr, i64:$offset))), - (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) - >; -} -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; -defm : MUBUFLoad_Pattern ; - -multiclass MUBUFStore_Pattern { +class DSAtomicCmpXChg : Pat < + (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), + (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset)) +>; - def : Pat < - (st vt:$value, (mubuf_vaddr_offset i64:$ptr, i64:$offset, IMM12bit:$imm_offset)), - (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, (as_i16imm $imm_offset)) - >; - def : Pat < - (st vt:$value, (add i64:$ptr, IMM12bit:$offset)), - (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) - >; +// 32-bit atomics. +def : DSAtomicIncRetPat; +def : DSAtomicIncRetPat; - def : Pat < - (st vt:$value, i64:$ptr), - (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) - >; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; + +def : DSAtomicCmpXChg; + +// 64-bit atomics. +def : DSAtomicIncRetPat; +def : DSAtomicIncRetPat; + +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; +def : DSAtomicRetPat; + +def : DSAtomicCmpXChg; + + +//===----------------------------------------------------------------------===// +// MUBUF Patterns +//===----------------------------------------------------------------------===// +multiclass MUBUFLoad_Pattern { def : Pat < - (st vt:$value, (add i64:$ptr, i64:$offset)), - (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) - >; + (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))), + (Instr_ADDR64 $srsrc, $vaddr, $offset) + >; } -defm : MUBUFStore_Pattern ; -defm : MUBUFStore_Pattern ; -defm : MUBUFStore_Pattern ; -defm : MUBUFStore_Pattern ; -defm : MUBUFStore_Pattern ; -defm : MUBUFStore_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; +defm : MUBUFLoad_Pattern ; + +class MUBUFScratchLoadPat : Pat < + (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, + i32:$soffset, u16imm:$offset))), + (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0) +>; + +def : MUBUFScratchLoadPat ; +def : MUBUFScratchLoadPat ; +def : MUBUFScratchLoadPat ; +def : MUBUFScratchLoadPat ; +def : MUBUFScratchLoadPat ; +def : MUBUFScratchLoadPat ; +def : MUBUFScratchLoadPat ; // BUFFER_LOAD_DWORD*, addr64=0 multiclass MUBUF_Load_Dword { def : Pat < - (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, + (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, imm:$offset, 0, 0, imm:$glc, imm:$slc, imm:$tfe)), - (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), + (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc), (as_i1imm $slc), (as_i1imm $tfe)) >; def : Pat < (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, - imm, 1, 0, imm:$glc, imm:$slc, + imm:$offset, 1, 0, imm:$glc, imm:$slc, imm:$tfe)), - (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), + (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), (as_i1imm $tfe)) >; @@ -2288,6 +2777,32 @@ defm : MUBUF_Load_Dword ; +class MUBUFScratchStorePat : Pat < + (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, + u16imm:$offset)), + (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0) +>; + +def : MUBUFScratchStorePat ; +def : MUBUFScratchStorePat ; +def : MUBUFScratchStorePat ; +def : MUBUFScratchStorePat ; +def : MUBUFScratchStorePat ; + +/* +class MUBUFStore_Pattern : Pat < + (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)), + (Instr $value, $srsrc, $vaddr, $offset) +>; + +def : MUBUFStore_Pattern ; +def : MUBUFStore_Pattern ; +def : MUBUFStore_Pattern ; +def : MUBUFStore_Pattern ; +def : MUBUFStore_Pattern ; + +*/ + //===----------------------------------------------------------------------===// // MTBUF Patterns //===----------------------------------------------------------------------===// @@ -2309,31 +2824,39 @@ def : MTBUF_StoreResource ; def : MTBUF_StoreResource ; def : MTBUF_StoreResource ; -let Predicates = [isCI] in { +let SubtargetPredicate = isCI in { // Sea island new arithmetic instructinos -let neverHasSideEffects = 1 in { -defm V_TRUNC_F64 : VOP1_64 <0x00000017, "V_TRUNC_F64", - [(set f64:$dst, (ftrunc f64:$src0))] +defm V_TRUNC_F64 : VOP1Inst , "V_TRUNC_F64", + VOP_F64_F64, ftrunc >; -defm V_CEIL_F64 : VOP1_64 <0x00000018, "V_CEIL_F64", - [(set f64:$dst, (fceil f64:$src0))] +defm V_CEIL_F64 : VOP1Inst , "V_CEIL_F64", + VOP_F64_F64, fceil >; -defm V_FLOOR_F64 : VOP1_64 <0x0000001A, "V_FLOOR_F64", - [(set f64:$dst, (ffloor f64:$src0))] +defm V_FLOOR_F64 : VOP1Inst , "V_FLOOR_F64", + VOP_F64_F64, ffloor >; -defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64", - [(set f64:$dst, (frint f64:$src0))] +defm V_RNDNE_F64 : VOP1Inst , "V_RNDNE_F64", + VOP_F64_F64, frint >; -defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>; -defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>; -defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>; -def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>; +defm V_QSAD_PK_U16_U8 : VOP3Inst , "V_QSAD_PK_U16_U8", + VOP_I32_I32_I32 +>; +defm V_MQSAD_U16_U8 : VOP3Inst , "V_MQSAD_U16_U8", + VOP_I32_I32_I32 +>; +defm V_MQSAD_U32_U8 : VOP3Inst , "V_MQSAD_U32_U8", + VOP_I32_I32_I32 +>; +defm V_MAD_U64_U32 : VOP3Inst , "V_MAD_U64_U32", + VOP_I64_I32_I32_I64 +>; // XXX - Does this set VCC? -def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>; -} // End neverHasSideEffects = 1 +defm V_MAD_I64_I32 : VOP3Inst , "V_MAD_I64_I32", + VOP_I64_I32_I32_I64 +>; // Remaining instructions: // FLAT_* @@ -2356,8 +2879,39 @@ def V_MAD_I64_I32 : VOP3_64 <0x00000177, "V_MAD_I64_I32", []>; // BUFFER_LOAD_DWORDX3 // BUFFER_STORE_DWORDX3 -} // End Predicates = [isCI] +} // End iSCI +//===----------------------------------------------------------------------===// +// Flat Patterns +//===----------------------------------------------------------------------===// + +class FLATLoad_Pattern : + Pat <(vt (flat_ld i64:$ptr)), + (Instr_ADDR64 $ptr) +>; + +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; +def : FLATLoad_Pattern ; + +class FLATStore_Pattern : + Pat <(st vt:$value, i64:$ptr), + (Instr $value, $ptr) + >; + +def : FLATStore_Pattern ; +def : FLATStore_Pattern ; +def : FLATStore_Pattern ; +def : FLATStore_Pattern ; +def : FLATStore_Pattern ; +def : FLATStore_Pattern ; /********** ====================== **********/ /********** Indirect adressing **********/ @@ -2368,13 +2922,13 @@ multiclass SI_INDIRECT_Pattern ; // 2. Extract without offset def : Pat< (vector_extract vt:$vec, i32:$idx), - (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) + (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) >; // 3. Insert with offset @@ -2500,25 +3054,20 @@ def : Pat < def : Pat < (i1 (trunc i32:$a)), - (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1) ->; - -// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector -// case, the sgpr-copies pass will fix this to use the vector version. -def : Pat < - (i32 (addc i32:$src0, i32:$src1)), - (S_ADD_I32 $src0, $src1) + (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1) >; def : Pat < - (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), - (V_BCNT_U32_B32_e32 $popcnt, $val) + (i32 (bswap i32:$a)), + (V_BFI_B32 (S_MOV_B32 0x00ff00ff), + (V_ALIGNBIT_B32 $a, $a, 24), + (V_ALIGNBIT_B32 $a, $a, 8)) >; //============================================================================// // Miscellaneous Optimization Patterns //============================================================================// -def : SHA256MaPattern ; +def : SHA256MaPattern ; } // End isSI predicate