X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCTargetMachine.h;h=51bacb7fd8ba6bd48dee1d1f8f5a6ee968c938ff;hb=00e08fcaa02286dd7da9cf9a8d158545532ab832;hp=3b2e481c7b5fae0e5379b9d31468f043b9e4dd8b;hpb=bc641b9d8b5ecafe0137c1a49f4777608981d81b;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 3b2e481c7b5..51bacb7fd8b 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -1,9 +1,9 @@ -//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=// +//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -11,54 +11,60 @@ // //===----------------------------------------------------------------------===// -#ifndef PPC_TARGETMACHINE_H -#define PPC_TARGETMACHINE_H +#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H +#define LLVM_LIB_TARGET_POWERPC_PPCTARGETMACHINE_H -#include "PPCFrameInfo.h" -#include "PPCSubtarget.h" -#include "PPCJITInfo.h" #include "PPCInstrInfo.h" -#include "PPCISelLowering.h" +#include "PPCSubtarget.h" +#include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" namespace llvm { -class PassManager; -class GlobalValue; -class PPCTargetMachine : public TargetMachine { - PPCInstrInfo InstrInfo; - PPCSubtarget Subtarget; - PPCFrameInfo FrameInfo; - PPCJITInfo JITInfo; - PPCTargetLowering TLInfo; - InstrItineraryData InstrItins; +/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets. +/// +class PPCTargetMachine : public LLVMTargetMachine { + PPCSubtarget Subtarget; + public: - PPCTargetMachine(const Module &M, const std::string &FS); + PPCTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); + + const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; } + + // Pass Pipeline Configuration + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + bool addCodeEmitter(PassManagerBase &PM, + JITCodeEmitter &JCE) override; - virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } - virtual TargetJITInfo *getJITInfo() { return &JITInfo; } - virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual PPCTargetLowering *getTargetLowering() { return &TLInfo; } - virtual const MRegisterInfo *getRegisterInfo() const { - return &InstrInfo.getRegisterInfo(); - } - virtual const InstrItineraryData getInstrItineraryData() const { - return InstrItins; - } - + /// \brief Register PPC analysis passes with a pass manager. + void addAnalysisPasses(PassManagerBase &PM) override; +}; - static unsigned getJITMatchQuality(); +/// PPC32TargetMachine - PowerPC 32-bit target machine. +/// +class PPC32TargetMachine : public PPCTargetMachine { + virtual void anchor(); +public: + PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); +}; - static unsigned getModuleMatchQuality(const Module &M); - - virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out, - CodeGenFileType FileType, bool Fast); - - bool addPassesToEmitMachineCode(FunctionPassManager &PM, - MachineCodeEmitter &MCE); +/// PPC64TargetMachine - PowerPC 64-bit target machine. +/// +class PPC64TargetMachine : public PPCTargetMachine { + virtual void anchor(); +public: + PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); }; - + } // end namespace llvm #endif