X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCTargetMachine.cpp;h=f5be148399965bcbe13d6e37e84a4c540bd2d729;hb=061efcfb3e79899493d857f49e50d09f29037e0a;hp=c174e264ce24ea12b79486662130dc2fca447ccd;hpb=b1d26f66658cff3ceb7d44a72fbc8c8e975532f9;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index c174e264ce2..f5be1483999 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -12,181 +12,111 @@ //===----------------------------------------------------------------------===// #include "PPC.h" -#include "PPCFrameInfo.h" #include "PPCTargetMachine.h" -#include "PPCJITInfo.h" -#include "llvm/Module.h" #include "llvm/PassManager.h" -#include "llvm/Analysis/Verifier.h" -#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetMachineRegistry.h" -#include "llvm/Transforms/Scalar.h" -#include "llvm/Support/CommandLine.h" -#include +#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" using namespace llvm; -namespace { +extern "C" void LLVMInitializePowerPCTarget() { // Register the targets - RegisterTarget - X("ppc32", " PowerPC 32"); - RegisterTarget - Y("ppc64", " PowerPC 64"); -} - -unsigned PPC32TargetMachine::getJITMatchQuality() { -#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) - if (sizeof(void*) == 4) - return 10; -#else - return 0; -#endif -} -unsigned PPC64TargetMachine::getJITMatchQuality() { -#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) - if (sizeof(void*) == 8) - return 10 * 0/*FIXME: not PPC64-JIT support yet! */; -#endif - return 0; -} - -unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) { - // We strongly match "powerpc-*". - std::string TT = M.getTargetTriple(); - if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-") - return 20; - - if (M.getEndianness() == Module::BigEndian && - M.getPointerSize() == Module::Pointer32) - return 10; // Weak match - else if (M.getEndianness() != Module::AnyEndianness || - M.getPointerSize() != Module::AnyPointerSize) - return 0; // Match for some other target - - return getJITMatchQuality()/2; -} - -unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) { - // We strongly match "powerpc64-*". - std::string TT = M.getTargetTriple(); - if (TT.size() >= 10 && std::string(TT.begin(), TT.begin()+10) == "powerpc64-") - return 20; - - if (M.getEndianness() == Module::BigEndian && - M.getPointerSize() == Module::Pointer64) - return 10; // Weak match - else if (M.getEndianness() != Module::AnyEndianness || - M.getPointerSize() != Module::AnyPointerSize) - return 0; // Match for some other target - - return getJITMatchQuality()/2; + RegisterTargetMachine A(ThePPC32Target); + RegisterTargetMachine B(ThePPC64Target); } - -PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS, +PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL, bool is64Bit) - : TargetMachine("PowerPC"), Subtarget(M, FS, is64Bit), + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), - FrameInfo(*this, false), JITInfo(*this), TLInfo(*this), + FrameLowering(Subtarget), JITInfo(*this, is64Bit), + TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - - if (getRelocationModel() == Reloc::Default) - if (Subtarget.isDarwin()) - setRelocationModel(Reloc::DynamicNoPIC); - else - setRelocationModel(Reloc::PIC); } -PPC32TargetMachine::PPC32TargetMachine(const Module &M, const std::string &FS) - : PPCTargetMachine(M, FS, false) { +void PPC32TargetMachine::anchor() { } + +PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { } +void PPC64TargetMachine::anchor() { } -PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS) - : PPCTargetMachine(M, FS, true) { +PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { } -/// addPassesToEmitFile - Add passes to the specified pass manager to implement -/// a static compiler for this target. -/// -bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM, - std::ostream &Out, - CodeGenFileType FileType, - bool Fast) { - if (FileType != TargetMachine::AssemblyFile) return true; - - // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo)); - - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); - - // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); - - // Clean up after other passes, e.g. merging critical edges. - if (!Fast) PM.add(createCFGSimplificationPass()); - - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); - - // Install an instruction selector. - PM.add(createPPCISelDag(*this)); - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +//===----------------------------------------------------------------------===// +// Pass Pipeline Configuration +//===----------------------------------------------------------------------===// - PM.add(createRegisterAllocator()); +namespace { +/// PPC Code Generator Pass Configuration Options. +class PPCPassConfig : public TargetPassConfig { +public: + PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + PPCTargetMachine &getPPCTargetMachine() const { + return getTM(); + } + + virtual bool addInstSelector(); + virtual bool getEnableTailMergeDefault() const; + virtual bool addPreEmitPass(); +}; +} // namespace + +TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { + return new PPCPassConfig(this, PM); +} - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +bool PPCPassConfig::addInstSelector() { + // Install an instruction selector. + PM.add(createPPCISelDag(getPPCTargetMachine())); + return false; +} - PM.add(createPrologEpilogCodeInserter()); +/// Override this for PowerPC. Tail merging happily breaks up instruction issue +/// groups, which typically degrades performance. +bool PPCPassConfig::getEnableTailMergeDefault() const { return false; } - // Must run branch selection immediately preceding the asm printer +bool PPCPassConfig::addPreEmitPass() { + // Must run branch selection immediately preceding the asm printer. PM.add(createPPCBranchSelectionPass()); - - // Decide which asm printer to use. If the user has not specified one on - // the command line, choose whichever one matches the default (current host). - if (Subtarget.isAIX()) - PM.add(createAIXAsmPrinter(Out, *this)); - else - PM.add(createDarwinAsmPrinter(Out, *this)); - - PM.add(createMachineCodeDeleter()); return false; } -void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) { - // The JIT should use the static relocation model. - TM.setRelocationModel(Reloc::Static); - - // Run loop strength reduction before anything else. - PM.add(createLoopStrengthReducePass(TM.getTargetLowering())); - - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, + JITCodeEmitter &JCE) { + // FIXME: This should be moved to TargetJITInfo!! + if (Subtarget.isPPC64()) + // Temporary workaround for the inability of PPC64 JIT to handle jump + // tables. + Options.DisableJumpTables = true; - // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); + // Inform the subtarget that we are in JIT mode. FIXME: does this break macho + // writing? + Subtarget.SetJITMode(); - // Clean up after other passes, e.g. merging critical edges. - PM.add(createCFGSimplificationPass()); + // Machine code emitter pass for PowerPC. + PM.add(createPPCJITCodeEmitterPass(*this, JCE)); - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); - - // Install an instruction selector. - PM.add(createPPCISelDag(TM)); - - PM.add(createRegisterAllocator()); - PM.add(createPrologEpilogCodeInserter()); - - // Must run branch selection immediately preceding the asm printer - PM.add(createPPCBranchSelectionPass()); - - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); + return false; } -