X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCTargetMachine.cpp;h=f56167e39018909991dc3d47d250b5329255c9a9;hb=64cc97212346992892b6c92158c08cd93149a882;hp=94136a456962b19723798366552af9583c221460;hpb=957e1674e797c8880114fb27a3aa1c32f9967329;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 94136a45696..f56167e3901 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -12,151 +12,187 @@ //===----------------------------------------------------------------------===// #include "PPC.h" -#include "PPCFrameInfo.h" +#include "PPCTargetAsmInfo.h" #include "PPCTargetMachine.h" -#include "PPCJITInfo.h" #include "llvm/Module.h" #include "llvm/PassManager.h" -#include "llvm/Analysis/Verifier.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetMachineRegistry.h" -#include "llvm/Transforms/Scalar.h" -#include "llvm/Support/CommandLine.h" -#include +#include "llvm/Target/TargetOptions.h" +#include "llvm/Support/FormattedStream.h" using namespace llvm; -namespace { - // Register the targets - RegisterTarget - X("ppc32", " PowerPC"); -} +// Register the targets +extern Target ThePPC32Target; +static RegisterTarget +X(ThePPC32Target, "ppc32", "PowerPC 32"); -unsigned PPCTargetMachine::getJITMatchQuality() { -#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) - return 10; -#else - return 0; -#endif -} +extern Target ThePPC64Target; +static RegisterTarget +Y(ThePPC64Target, "ppc64", "PowerPC 64"); -unsigned PPCTargetMachine::getModuleMatchQuality(const Module &M) { - // We strongly match "powerpc-*". - std::string TT = M.getTargetTriple(); - if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-") - return 20; - - if (M.getEndianness() == Module::BigEndian && - M.getPointerSize() == Module::Pointer32) - return 10; // Weak match - else if (M.getEndianness() != Module::AnyEndianness || - M.getPointerSize() != Module::AnyPointerSize) - return 0; // Match for some other target - - return getJITMatchQuality()/2; +// Force static initialization. +extern "C" void LLVMInitializePowerPCTarget() { } + +const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const { + if (Subtarget.isDarwin()) + return new PPCDarwinTargetAsmInfo(*this); + else + return new PPCLinuxTargetAsmInfo(*this); } -PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS) -: TargetMachine("PowerPC", false, 4, 4, 4, 4, 4, 4, 2, 1, 1), - Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this), - TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - if (TargetDefault == PPCTarget) { - if (Subtarget.isAIX()) PPCTarget = TargetAIX; - if (Subtarget.isDarwin()) PPCTarget = TargetDarwin; - } - if (getRelocationModel() == Reloc::Default) +PPCTargetMachine::PPCTargetMachine(const Target&T, const Module &M, + const std::string &FS, bool is64Bit) + : LLVMTargetMachine(T), + Subtarget(*this, M, FS, is64Bit), + DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), + FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this), + InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) { + + if (getRelocationModel() == Reloc::Default) { if (Subtarget.isDarwin()) setRelocationModel(Reloc::DynamicNoPIC); else - setRelocationModel(Reloc::PIC); + setRelocationModel(Reloc::Static); + } } -/// addPassesToEmitFile - Add passes to the specified pass manager to implement -/// a static compiler for this target. -/// -bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM, - std::ostream &Out, - CodeGenFileType FileType, - bool Fast) { - if (FileType != TargetMachine::AssemblyFile) return true; - - // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo)); - - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); +/// Override this for PowerPC. Tail merging happily breaks up instruction issue +/// groups, which typically degrades performance. +bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } - // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); - - // Clean up after other passes, e.g. merging critical edges. - if (!Fast) PM.add(createCFGSimplificationPass()); - - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); +PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Module &M, + const std::string &FS) + : PPCTargetMachine(T, M, FS, false) { +} - // Install an instruction selector. - PM.add(createPPCISelDag(*this)); - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Module &M, + const std::string &FS) + : PPCTargetMachine(T, M, FS, true) { +} - PM.add(createRegisterAllocator()); - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +//===----------------------------------------------------------------------===// +// Pass Pipeline Configuration +//===----------------------------------------------------------------------===// - PM.add(createPrologEpilogCodeInserter()); +bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { + // Install an instruction selector. + PM.add(createPPCISelDag(*this)); + return false; +} - // Must run branch selection immediately preceding the asm printer +bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, + CodeGenOpt::Level OptLevel) { + // Must run branch selection immediately preceding the asm printer. PM.add(createPPCBranchSelectionPass()); + return false; +} - // Decide which asm printer to use. If the user has not specified one on - // the command line, choose whichever one matches the default (current host). - switch (PPCTarget) { - case TargetAIX: - PM.add(createAIXAsmPrinter(Out, *this)); - break; - case TargetDefault: - case TargetDarwin: - PM.add(createDarwinAsmPrinter(Out, *this)); - break; +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + MachineCodeEmitter &MCE) { + // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. + // FIXME: This should be moved to TargetJITInfo!! + if (Subtarget.isPPC64()) { + // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many + // instructions to materialize arbitrary global variable + function + + // constant pool addresses. + setRelocationModel(Reloc::PIC_); + // Temporary workaround for the inability of PPC64 JIT to handle jump + // tables. + DisableJumpTables = true; + } else { + setRelocationModel(Reloc::Static); } + + // Inform the subtarget that we are in JIT mode. FIXME: does this break macho + // writing? + Subtarget.SetJITMode(); + + // Machine code emitter pass for PowerPC. + PM.add(createPPCCodeEmitterPass(*this, MCE)); - PM.add(createMachineCodeDeleter()); return false; } -void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) { - // The JIT should use dynamic-no-pic relocation model. - TM.setRelocationModel(Reloc::DynamicNoPIC); - - // Run loop strength reduction before anything else. - PM.add(createLoopStrengthReducePass(TM.getTargetLowering())); - - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); - - // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass()); +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + JITCodeEmitter &JCE) { + // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. + // FIXME: This should be moved to TargetJITInfo!! + if (Subtarget.isPPC64()) { + // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many + // instructions to materialize arbitrary global variable + function + + // constant pool addresses. + setRelocationModel(Reloc::PIC_); + // Temporary workaround for the inability of PPC64 JIT to handle jump + // tables. + DisableJumpTables = true; + } else { + setRelocationModel(Reloc::Static); + } + + // Inform the subtarget that we are in JIT mode. FIXME: does this break macho + // writing? + Subtarget.SetJITMode(); + + // Machine code emitter pass for PowerPC. + PM.add(createPPCJITCodeEmitterPass(*this, JCE)); - // Clean up after other passes, e.g. merging critical edges. - PM.add(createCFGSimplificationPass()); + return false; +} - // Make sure that no unreachable blocks are instruction selected. - PM.add(createUnreachableBlockEliminationPass()); +bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + ObjectCodeEmitter &OCE) { + // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. + // FIXME: This should be moved to TargetJITInfo!! + if (Subtarget.isPPC64()) { + // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many + // instructions to materialize arbitrary global variable + function + + // constant pool addresses. + setRelocationModel(Reloc::PIC_); + // Temporary workaround for the inability of PPC64 JIT to handle jump + // tables. + DisableJumpTables = true; + } else { + setRelocationModel(Reloc::Static); + } + + // Inform the subtarget that we are in JIT mode. FIXME: does this break macho + // writing? + Subtarget.SetJITMode(); + + // Machine code emitter pass for PowerPC. + PM.add(createPPCObjectCodeEmitterPass(*this, OCE)); - // Install an instruction selector. - PM.add(createPPCISelDag(TM)); + return false; +} - PM.add(createRegisterAllocator()); - PM.add(createPrologEpilogCodeInserter()); +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + MachineCodeEmitter &MCE) { + // Machine code emitter pass for PowerPC. + PM.add(createPPCCodeEmitterPass(*this, MCE)); + return false; +} - // Must run branch selection immediately preceding the asm printer - PM.add(createPPCBranchSelectionPass()); +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + JITCodeEmitter &JCE) { + // Machine code emitter pass for PowerPC. + PM.add(createPPCJITCodeEmitterPass(*this, JCE)); + return false; +} - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(&std::cerr)); +bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, + CodeGenOpt::Level OptLevel, + ObjectCodeEmitter &OCE) { + // Machine code emitter pass for PowerPC. + PM.add(createPPCObjectCodeEmitterPass(*this, OCE)); + return false; } +