X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCTargetMachine.cpp;h=b0bfaab125de118f59b77b6b96d9452e96f06252;hb=63c2f3292eb39599313d64c639014f4422a28b45;hp=7946837e06c4ff64da3e0bfc459c54f08b7824ae;hpb=5ffe38ef6ae3427b39b2d866ab8d1a73f9f69e56;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 7946837e06c..b0bfaab125d 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -11,112 +11,207 @@ // //===----------------------------------------------------------------------===// -#include "PPC.h" -#include "PPCMCAsmInfo.h" #include "PPCTargetMachine.h" +#include "PPC.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/IR/Function.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/PassManager.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegistry.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Target/TargetOptions.h" using namespace llvm; -static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { - Triple TheTriple(TT); - bool isPPC64 = TheTriple.getArch() == Triple::ppc64; - if (TheTriple.getOS() == Triple::Darwin) - return new PPCMCAsmInfoDarwin(isPPC64); - return new PPCLinuxMCAsmInfo(isPPC64); - -} +static cl:: +opt DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, + cl::desc("Disable CTR loops for PPC")); + +static cl::opt +VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", + cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early")); extern "C" void LLVMInitializePowerPCTarget() { // Register the targets - RegisterTargetMachine A(ThePPC32Target); + RegisterTargetMachine A(ThePPC32Target); RegisterTargetMachine B(ThePPC64Target); - - RegisterAsmInfoFn C(ThePPC32Target, createMCAsmInfo); - RegisterAsmInfoFn D(ThePPC64Target, createMCAsmInfo); - - // Register the MC Code Emitter - TargetRegistry::RegisterCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter); - TargetRegistry::RegisterCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter); + RegisterTargetMachine C(ThePPC64LETarget); } +static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) { + std::string FullFS = FS; + Triple TargetTriple(TT); -PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool is64Bit) - : LLVMTargetMachine(T, TT), - Subtarget(TT, FS, is64Bit), - DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), - FrameInfo(Subtarget), JITInfo(*this, is64Bit), - TLInfo(*this), TSInfo(*this), - InstrItins(Subtarget.getInstrItineraryData()) { + // Make sure 64-bit features are available when CPUname is generic + if (TargetTriple.getArch() == Triple::ppc64 || + TargetTriple.getArch() == Triple::ppc64le) { + if (!FullFS.empty()) + FullFS = "+64bit," + FullFS; + else + FullFS = "+64bit"; + } - if (getRelocationModel() == Reloc::Default) { - if (Subtarget.isDarwin()) - setRelocationModel(Reloc::DynamicNoPIC); + if (OL >= CodeGenOpt::Default) { + if (!FullFS.empty()) + FullFS = "+crbits," + FullFS; else - setRelocationModel(Reloc::Static); + FullFS = "+crbits"; } + return FullFS; +} + +// The FeatureString here is a little subtle. We are modifying the feature string +// with what are (currently) non-function specific overrides as it goes into the +// LLVMTargetMachine constructor and then using the stored value in the +// Subtarget constructor below it. +PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM, + CM, OL), + Subtarget(TT, CPU, TargetFS, *this) { + initAsmInfo(); } -/// Override this for PowerPC. Tail merging happily breaks up instruction issue -/// groups, which typically degrades performance. -bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } +void PPC32TargetMachine::anchor() { } -PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT, - const std::string &FS) - : PPCTargetMachine(T, TT, FS, false) { +PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { } +void PPC64TargetMachine::anchor() { } -PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT, - const std::string &FS) - : PPCTargetMachine(T, TT, FS, true) { +PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) { } +const PPCSubtarget * +PPCTargetMachine::getSubtargetImpl(const Function &F) const { + AttributeSet FnAttrs = F.getAttributes(); + Attribute CPUAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu"); + Attribute FSAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features"); + + std::string CPU = !CPUAttr.hasAttribute(Attribute::None) + ? CPUAttr.getValueAsString().str() + : TargetCPU; + std::string FS = !FSAttr.hasAttribute(Attribute::None) + ? FSAttr.getValueAsString().str() + : TargetFS; + + auto &I = SubtargetMap[CPU + FS]; + if (!I) { + // This needs to be done before we create a new subtarget since any + // creation will depend on the TM and the code generation flags on the + // function that reside in TargetOptions. + resetTargetOptions(F); + I = llvm::make_unique(TargetTriple, CPU, FS, *this); + } + return I.get(); +} //===----------------------------------------------------------------------===// // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { +namespace { +/// PPC Code Generator Pass Configuration Options. +class PPCPassConfig : public TargetPassConfig { +public: + PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + PPCTargetMachine &getPPCTargetMachine() const { + return getTM(); + } + + const PPCSubtarget &getPPCSubtarget() const { + return *getPPCTargetMachine().getSubtargetImpl(); + } + + void addIRPasses() override; + bool addPreISel() override; + bool addILPOpts() override; + bool addInstSelector() override; + bool addPreRegAlloc() override; + bool addPreSched2() override; + bool addPreEmitPass() override; +}; +} // namespace + +TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { + return new PPCPassConfig(this, PM); +} + +void PPCPassConfig::addIRPasses() { + addPass(createAtomicExpandPass(&getPPCTargetMachine())); + TargetPassConfig::addIRPasses(); +} + +bool PPCPassConfig::addPreISel() { + if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) + addPass(createPPCCTRLoops(getPPCTargetMachine())); + + return false; +} + +bool PPCPassConfig::addILPOpts() { + addPass(&EarlyIfConverterID); + return true; +} + +bool PPCPassConfig::addInstSelector() { // Install an instruction selector. - PM.add(createPPCISelDag(*this)); + addPass(createPPCISelDag(getPPCTargetMachine())); + +#ifndef NDEBUG + if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None) + addPass(createPPCCTRLoopsVerify()); +#endif + + addPass(createPPCVSXCopyPass()); return false; } -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { - // Must run branch selection immediately preceding the asm printer. - PM.add(createPPCBranchSelectionPass()); +bool PPCPassConfig::addPreRegAlloc() { + initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry()); + insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID, + &PPCVSXFMAMutateID); return false; } -bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, - CodeGenOpt::Level OptLevel, - JITCodeEmitter &JCE) { - // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64. - // FIXME: This should be moved to TargetJITInfo!! - if (Subtarget.isPPC64()) { - // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many - // instructions to materialize arbitrary global variable + function + - // constant pool addresses. - setRelocationModel(Reloc::PIC_); - // Temporary workaround for the inability of PPC64 JIT to handle jump - // tables. - DisableJumpTables = true; - } else { - setRelocationModel(Reloc::Static); - } - - // Inform the subtarget that we are in JIT mode. FIXME: does this break macho - // writing? - Subtarget.SetJITMode(); - - // Machine code emitter pass for PowerPC. - PM.add(createPPCJITCodeEmitterPass(*this, JCE)); +bool PPCPassConfig::addPreSched2() { + addPass(createPPCVSXCopyCleanupPass()); + + if (getOptLevel() != CodeGenOpt::None) + addPass(&IfConverterID); + + return true; +} +bool PPCPassConfig::addPreEmitPass() { + if (getOptLevel() != CodeGenOpt::None) + addPass(createPPCEarlyReturnPass()); + // Must run branch selection immediately preceding the asm printer. + addPass(createPPCBranchSelectionPass()); return false; } + +void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) { + // Add first the target-independent BasicTTI pass, then our PPC pass. This + // allows the PPC pass to delegate to the target independent layer when + // appropriate. + PM.add(createBasicTargetTransformInfoPass(this)); + PM.add(createPPCTargetTransformInfoPass(this)); +} +