X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FPowerPC%2FPPCInstrAltivec.td;h=9eb18c3724dc4762508c424a40cdbefb2500553e;hb=3f0b7ff39fcf50fc2b57718cd2264137f11614b6;hp=35fed0f5310b2466c1fda2a6ef5fb6f84808dddf;hpb=6cea814f2c2268f19b28ea1443cd5f55f932bb1e;p=oota-llvm.git diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 35fed0f5310..9eb18c3724d 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -15,14 +15,25 @@ // Altivec transformation functions and pattern fragments. // -// VSPLT_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. -def VSPLT_get_imm : SDNodeXForm; - -def VSPLT_shuffle_mask : PatLeaf<(build_vector), [{ - return PPC::isSplatShuffleMask(N); -}], VSPLT_get_imm>; +def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N, 1); +}], VSPLTB_get_imm>; +def VSPLTH_get_imm : SDNodeXForm; +def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N, 2); +}], VSPLTH_get_imm>; +def VSPLTW_get_imm : SDNodeXForm; +def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{ + return PPC::isSplatShuffleMask(N, 4); +}], VSPLTW_get_imm>; // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. @@ -55,11 +66,6 @@ def vecspltisw : PatLeaf<(build_vector), [{ return PPC::isVecSplatImm(N, 4); }], VSPLTISW_get_imm>; -class isVDOT { // vector dot instruction. - list Defs = [CR6]; - bit RC = 1; -} - //===----------------------------------------------------------------------===// // Helpers for defining instructions that directly correspond to intrinsics. @@ -156,10 +162,6 @@ def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH), imm:$SH))]>; // VX-Form instructions. AltiVec arithmetic ops. -def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddcuw $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>; def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vaddfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; @@ -174,31 +176,15 @@ def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vadduwm $vD, $vA, $vB", VecGeneral, [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; -def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddsbs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>; -def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddshs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>; -def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddsws $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>; +def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>; +def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>; +def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>; +def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>; +def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>; +def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; +def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; + -def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vaddubs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>; -def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vadduhs $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>; -def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vadduws $vD, $vA, $vB", VecFP, - [(set VRRC:$vD, - (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>; def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vand $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; @@ -220,18 +206,30 @@ def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vctuxs $vD, $vB, $UIMM", VecFP, []>; -def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB), - "vexptefp $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vexptefp VRRC:$vB))]>; -def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB), - "vlogefp $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vlogefp VRRC:$vB))]>; -def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vmaxfp $vD, $vA, $vB", VecFP, - []>; -def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), - "vminfp $vD, $vA, $vB", VecFP, - []>; +def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; +def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; + +def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>; +def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>; +def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>; +def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>; +def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>; +def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>; + +def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; +def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; +def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; +def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; +def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; +def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; +def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; +def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; +def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; +def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; +def VMINSW : VX1_Int< 896, "vminsw", int_ppc_altivec_vminsw>; +def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; +def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; +def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>; def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>; @@ -308,14 +306,16 @@ def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltb $vD, $vB, $UIMM", VecPerm, - []>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLTB_shuffle_mask:$UIMM))]>; def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vsplth $vD, $vB, $UIMM", VecPerm, - []>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLTH_shuffle_mask:$UIMM))]>; def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB), "vspltw $vD, $vB, $UIMM", VecPerm, - [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef), - VSPLT_shuffle_mask:$UIMM))]>; + [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef), + VSPLTW_shuffle_mask:$UIMM))]>; def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>; def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>; @@ -353,24 +353,12 @@ def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; // Vector Unpack. -def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB), - "vupkhpx $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupkhpx VRRC:$vB))]>; -def VUPKHSB : VXForm_2<526, (ops VRRC:$vD, VRRC:$vB), - "vupkhsb $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupkhsb VRRC:$vB))]>; -def VUPKHSH : VXForm_2<590, (ops VRRC:$vD, VRRC:$vB), - "vupkhsh $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupkhsh VRRC:$vB))]>; -def VUPKLPX : VXForm_2<974, (ops VRRC:$vD, VRRC:$vB), - "vupklpx $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupklpx VRRC:$vB))]>; -def VUPKLSB : VXForm_2<654, (ops VRRC:$vD, VRRC:$vB), - "vupklsb $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupklsb VRRC:$vB))]>; -def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB), - "vupklsh $vD, $vB", VecFP, - [(set VRRC:$vD, (int_ppc_altivec_vupklsh VRRC:$vB))]>; +def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>; +def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>; +def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>; +def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>; +def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>; +def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; // Altivec Comparisons. @@ -380,7 +368,10 @@ class VCMP xo, string asmstr, ValueType Ty> [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; class VCMPo xo, string asmstr, ValueType Ty> : VXRForm_1,isVDOT; + [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { + let Defs = [CR6]; + let RC = 1; +} // f32 element comparisons.0 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; @@ -480,6 +471,10 @@ def : Pat<(v4i32 vecspltish:$invec), (v4i32 (VSPLTISH vecspltish:$invec))>; def : Pat<(v4i32 vecspltisw:$invec), (v4i32 (VSPLTISW vecspltisw:$invec))>; // Logical Operations +def : Pat<(v16i8 (vnot VRRC:$vA)), (v16i8 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v8i16 (vnot VRRC:$vA)), (v8i16 (VNOR VRRC:$vA, VRRC:$vA))>; +def : Pat<(v4i32 (vnot VRRC:$vA)), (v4i32 (VNOR VRRC:$vA, VRRC:$vA))>; + def : Pat<(v16i8 (and VRRC:$A, VRRC:$B)), (v16i8 (VAND VRRC:$A, VRRC:$B))>; def : Pat<(v8i16 (and VRRC:$A, VRRC:$B)), (v8i16 (VAND VRRC:$A, VRRC:$B))>; def : Pat<(v16i8 (or VRRC:$A, VRRC:$B)), (v16i8 (VOR VRRC:$A, VRRC:$B))>; @@ -508,14 +503,6 @@ def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C), (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; -def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM), - (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>; - -def : Pat<(PPCvperm (v4i32 VRRC:$vA), VRRC:$vB, VRRC:$vC), - (v4i32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; -def : Pat<(PPCvperm (v4f32 VRRC:$vA), VRRC:$vB, VRRC:$vC), - (v4f32 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; -def : Pat<(PPCvperm (v8i16 VRRC:$vA), VRRC:$vB, VRRC:$vC), - (v8i16 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>; + def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), (v16i8 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC))>;