X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsSubtarget.h;h=fbb01fe7702945c0ea6df78b771ba84246af58a7;hb=8b170f7f290843dc3849eaa75b6f74a87a7a2de6;hp=f3264621a70063d61b19332aa689400f2fdb78bd;hpb=84d236137fcf0b77d4a3010e884d94b9020dab51;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index f3264621a70..fbb01fe7702 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -11,17 +11,17 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSUBTARGET_H -#define MIPSSUBTARGET_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H +#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H +#include "MCTargetDesc/MipsABIInfo.h" #include "MipsFrameLowering.h" #include "MipsISelLowering.h" #include "MipsInstrInfo.h" -#include "MipsJITInfo.h" -#include "MipsSelectionDAGInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetSelectionDAGInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" #include @@ -36,27 +36,27 @@ class MipsTargetMachine; class MipsSubtarget : public MipsGenSubtargetInfo { virtual void anchor(); -public: - // NOTE: O64 will not be supported. - enum MipsABIEnum { - UnknownABI, O32, N32, N64, EABI - }; - -protected: enum MipsArchEnum { - Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64, - Mips64r2, Mips64r6 + MipsDefault, + Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max, + Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 }; + enum class CPU { P5600 }; + // Mips architecture version MipsArchEnum MipsArchVersion; - // Mips supported ABIs - MipsABIEnum MipsABI; + // Processor implementation (unused but required to exist by + // tablegen-erated code). + CPU ProcImpl; // IsLittle - The target is Little Endian bool IsLittle; + // IsSoftFloat - The target does not support any floating point instructions. + bool IsSoftFloat; + // IsSingleFloat - The target only supports single precision float // point operations. This enable the target to use all 32 32-bit // floating point registers instead of only using even ones. @@ -65,6 +65,9 @@ protected: // IsFPXX - MIPS O32 modeless ABI. bool IsFPXX; + // NoABICalls - Disable SVR4-style position-independent code. + bool NoABICalls; + // IsFP64bit - The target processor has 64-bit floating point registers. bool IsFP64bit; @@ -119,8 +122,8 @@ protected: // InMicroMips -- can process MicroMips instructions bool InMicroMipsMode; - // HasDSP, HasDSPR2 -- supports DSP ASE. - bool HasDSP, HasDSPR2; + // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE. + bool HasDSP, HasDSPR2, HasDSPR3; // Allow mixed Mips16 and Mips32 in one source file bool AllowMixed16_32; @@ -133,41 +136,45 @@ protected: // HasMSA -- supports MSA ASE. bool HasMSA; + // UseTCCInDIV -- Enables the use of trapping in the assembler. + bool UseTCCInDIV; + + // HasEVA -- supports EVA ASE. + bool HasEVA; + InstrItineraryData InstrItins; // We can override the determination of whether we are in mips16 mode // as from the command line enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; - MipsTargetMachine *TM; + const MipsTargetMachine &TM; Triple TargetTriple; - const DataLayout DL; // Calculates type size & alignment - const MipsSelectionDAGInfo TSInfo; - MipsJITInfo JITInfo; + const TargetSelectionDAGInfo TSInfo; std::unique_ptr InstrInfo; std::unique_ptr FrameLowering; std::unique_ptr TLInfo; public: /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. - bool enablePostMachineScheduler() const override; + bool enablePostRAScheduler() const override; void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; /// Only O32 and EABI supported right now. - bool isABI_EABI() const { return MipsABI == EABI; } - bool isABI_N64() const { return MipsABI == N64; } - bool isABI_N32() const { return MipsABI == N32; } - bool isABI_O32() const { return MipsABI == O32; } + bool isABI_EABI() const; + bool isABI_N64() const; + bool isABI_N32() const; + bool isABI_O32() const; + const MipsABIInfo &getABI() const; bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } - unsigned getTargetABI() const { return MipsABI; } /// This constructor initializes the data members to match that /// of the specified triple. - MipsSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool little, MipsTargetMachine *TM); + MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + bool little, const MipsTargetMachine &TM); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. @@ -181,35 +188,44 @@ public: bool hasMips4_32() const { return HasMips4_32; } bool hasMips4_32r2() const { return HasMips4_32r2; } bool hasMips32() const { - return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 && - MipsArchVersion != Mips4 && MipsArchVersion != Mips5; + return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) || + hasMips64(); } bool hasMips32r2() const { - return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 || - MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; + return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) || + hasMips64r2(); + } + bool hasMips32r3() const { + return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || + hasMips64r2(); + } + bool hasMips32r5() const { + return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || + hasMips64r5(); } bool hasMips32r6() const { - return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6; + return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || + hasMips64r6(); } bool hasMips64() const { return MipsArchVersion >= Mips64; } - bool hasMips64r2() const { - return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; - } - bool hasMips64r6() const { return MipsArchVersion == Mips64r6; } + bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } + bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } + bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; } + bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } bool hasCnMips() const { return HasCnMips; } bool isLittle() const { return IsLittle; } + bool isABICalls() const { return !NoABICalls; } bool isFPXX() const { return IsFPXX; } bool isFP64bit() const { return IsFP64bit; } bool useOddSPReg() const { return UseOddSPReg; } bool noOddSPReg() const { return !UseOddSPReg; } bool isNaN2008() const { return IsNaN2008bit; } - bool isNotFP64bit() const { return !IsFP64bit; } bool isGP64bit() const { return IsGP64bit; } bool isGP32bit() const { return !IsGP64bit; } + unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } bool isSingleFloat() const { return IsSingleFloat; } - bool isNotSingleFloat() const { return !IsSingleFloat; } bool hasVFPU() const { return HasVFPU; } bool inMips16Mode() const { return InMips16Mode; } bool inMips16ModeDefault() const { @@ -223,15 +239,18 @@ public: return inMips16Mode() && InMips16HardFloat; } bool inMicroMipsMode() const { return InMicroMipsMode; } + bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } + bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); } bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } + bool hasDSPR3() const { return HasDSPR3; } bool hasMSA() const { return HasMSA; } - bool isLinux() const { return IsLinux; } + bool hasEVA() const { return HasEVA; } bool useSmallSection() const { return UseSmallSection; } bool hasStandardEncoding() const { return !inMips16Mode(); } - bool abiUsesSoftFloat() const; + bool useSoftFloat() const { return IsSoftFloat; } bool enableLongBranchPass() const { return hasStandardEncoding() || allowMixed16_32(); @@ -241,14 +260,12 @@ public: bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } bool hasMTHC1() const { return hasMips32r2(); } - const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } bool allowMixed16_32() const { return inMips16ModeDefault() | - AllowMixed16_32;} + AllowMixed16_32; } - bool os16() const { return Os16;}; + bool os16() const { return Os16; } bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } - bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); } // for now constant islands are on for the whole compilation unit but we only // really use them if in addition we are in mips16 mode @@ -260,7 +277,7 @@ public: Reloc::Model getRelocationModel() const; MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, - const TargetMachine *TM); + const TargetMachine &TM); /// Does the system support unaligned memory access. /// @@ -273,17 +290,22 @@ public: void setHelperClassesMips16(); void setHelperClassesMipsSE(); - MipsJITInfo *getJITInfo() { return &JITInfo; } - const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } - const DataLayout *getDataLayout() const { return &DL; } - const MipsInstrInfo *getInstrInfo() const { return InstrInfo.get(); } - const TargetFrameLowering *getFrameLowering() const { + const TargetSelectionDAGInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } + const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } + const TargetFrameLowering *getFrameLowering() const override { return FrameLowering.get(); } - const MipsRegisterInfo *getRegisterInfo() const { + const MipsRegisterInfo *getRegisterInfo() const override { return &InstrInfo->getRegisterInfo(); } - const MipsTargetLowering *getTargetLowering() const { return TLInfo.get(); } + const MipsTargetLowering *getTargetLowering() const override { + return TLInfo.get(); + } + const InstrItineraryData *getInstrItineraryData() const override { + return &InstrItins; + } }; } // End llvm namespace