X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsSubtarget.h;h=fbb01fe7702945c0ea6df78b771ba84246af58a7;hb=8b170f7f290843dc3849eaa75b6f74a87a7a2de6;hp=1c37b84940ec6e73155a25c1c80dd643d05512ff;hpb=2992ea0cb5437b2eeddd75e738b3651bd7ba6cea;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 1c37b84940e..fbb01fe7702 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -14,15 +14,15 @@ #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H +#include "MCTargetDesc/MipsABIInfo.h" #include "MipsFrameLowering.h" #include "MipsISelLowering.h" #include "MipsInstrInfo.h" -#include "MipsSelectionDAGInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetSelectionDAGInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" -#include "MipsABIInfo.h" #include #define GET_SUBTARGETINFO_HEADER @@ -37,19 +37,26 @@ class MipsSubtarget : public MipsGenSubtargetInfo { virtual void anchor(); enum MipsArchEnum { - Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64, - Mips64r2, Mips64r6 + MipsDefault, + Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max, + Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 }; + enum class CPU { P5600 }; + // Mips architecture version MipsArchEnum MipsArchVersion; - // Selected ABI - MipsABIInfo ABI; + // Processor implementation (unused but required to exist by + // tablegen-erated code). + CPU ProcImpl; // IsLittle - The target is Little Endian bool IsLittle; + // IsSoftFloat - The target does not support any floating point instructions. + bool IsSoftFloat; + // IsSingleFloat - The target only supports single precision float // point operations. This enable the target to use all 32 32-bit // floating point registers instead of only using even ones. @@ -115,8 +122,8 @@ class MipsSubtarget : public MipsGenSubtargetInfo { // InMicroMips -- can process MicroMips instructions bool InMicroMipsMode; - // HasDSP, HasDSPR2 -- supports DSP ASE. - bool HasDSP, HasDSPR2; + // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE. + bool HasDSP, HasDSPR2, HasDSPR3; // Allow mixed Mips16 and Mips32 in one source file bool AllowMixed16_32; @@ -129,41 +136,45 @@ class MipsSubtarget : public MipsGenSubtargetInfo { // HasMSA -- supports MSA ASE. bool HasMSA; + // UseTCCInDIV -- Enables the use of trapping in the assembler. + bool UseTCCInDIV; + + // HasEVA -- supports EVA ASE. + bool HasEVA; + InstrItineraryData InstrItins; // We can override the determination of whether we are in mips16 mode // as from the command line enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; - const MipsTargetMachine *TM; + const MipsTargetMachine &TM; Triple TargetTriple; - const DataLayout DL; // Calculates type size & alignment - const MipsSelectionDAGInfo TSInfo; + const TargetSelectionDAGInfo TSInfo; std::unique_ptr InstrInfo; std::unique_ptr FrameLowering; std::unique_ptr TLInfo; public: /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. - bool enablePostMachineScheduler() const override; + bool enablePostRAScheduler() const override; void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; /// Only O32 and EABI supported right now. - bool isABI_EABI() const { return ABI.IsEABI(); } - bool isABI_N64() const { return ABI.IsN64(); } - bool isABI_N32() const { return ABI.IsN32(); } - bool isABI_O32() const { return ABI.IsO32(); } + bool isABI_EABI() const; + bool isABI_N64() const; + bool isABI_N32() const; + bool isABI_O32() const; + const MipsABIInfo &getABI() const; bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } - const MipsABIInfo &getABI() const { return ABI; } /// This constructor initializes the data members to match that /// of the specified triple. - MipsSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool little, - const MipsTargetMachine *TM); + MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, + bool little, const MipsTargetMachine &TM); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. @@ -177,21 +188,30 @@ public: bool hasMips4_32() const { return HasMips4_32; } bool hasMips4_32r2() const { return HasMips4_32r2; } bool hasMips32() const { - return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 && - MipsArchVersion != Mips4 && MipsArchVersion != Mips5; + return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) || + hasMips64(); } bool hasMips32r2() const { - return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 || - MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; + return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) || + hasMips64r2(); + } + bool hasMips32r3() const { + return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || + hasMips64r2(); + } + bool hasMips32r5() const { + return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || + hasMips64r5(); } bool hasMips32r6() const { - return MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r6; + return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || + hasMips64r6(); } bool hasMips64() const { return MipsArchVersion >= Mips64; } - bool hasMips64r2() const { - return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; - } - bool hasMips64r6() const { return MipsArchVersion == Mips64r6; } + bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } + bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } + bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; } + bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } bool hasCnMips() const { return HasCnMips; } @@ -219,15 +239,18 @@ public: return inMips16Mode() && InMips16HardFloat; } bool inMicroMipsMode() const { return InMicroMipsMode; } + bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } + bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); } bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } + bool hasDSPR3() const { return HasDSPR3; } bool hasMSA() const { return HasMSA; } - bool isLinux() const { return IsLinux; } + bool hasEVA() const { return HasEVA; } bool useSmallSection() const { return UseSmallSection; } bool hasStandardEncoding() const { return !inMips16Mode(); } - bool abiUsesSoftFloat() const; + bool useSoftFloat() const { return IsSoftFloat; } bool enableLongBranchPass() const { return hasStandardEncoding() || allowMixed16_32(); @@ -238,9 +261,9 @@ public: bool hasMTHC1() const { return hasMips32r2(); } bool allowMixed16_32() const { return inMips16ModeDefault() | - AllowMixed16_32;} + AllowMixed16_32; } - bool os16() const { return Os16;}; + bool os16() const { return Os16; } bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } @@ -254,7 +277,7 @@ public: Reloc::Model getRelocationModel() const; MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, - const TargetMachine *TM); + const TargetMachine &TM); /// Does the system support unaligned memory access. /// @@ -267,10 +290,9 @@ public: void setHelperClassesMips16(); void setHelperClassesMipsSE(); - const MipsSelectionDAGInfo *getSelectionDAGInfo() const override { + const TargetSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; } - const DataLayout *getDataLayout() const override { return &DL; } const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } const TargetFrameLowering *getFrameLowering() const override { return FrameLowering.get();