X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsSEFrameLowering.cpp;h=67f96d16fd0eed1c7871a1e558a62e207623505e;hb=6035518e3bd06cef0515af5a319fbe2cea7df6d4;hp=f2276f19afa160df8a742bd1fcf24d8a2bfeefeb;hpb=fce699d88ac8640f97e6fe3fe3f3e17000d1be1c;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index f2276f19afa..67f96d16fd0 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -66,6 +66,8 @@ private: unsigned MFLoOpc); bool expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const; + bool expandExtractElementF64(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, bool FP64) const; MachineFunction &MF; MachineRegisterInfo &MRI; @@ -118,6 +120,14 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { if (expandBuildPairF64(MBB, I, true)) MBB.erase(I); return false; + case Mips::ExtractElementF64: + if (expandExtractElementF64(MBB, I, false)) + MBB.erase(I); + return false; + case Mips::ExtractElementF64_64: + if (expandExtractElementF64(MBB, I, true)) + MBB.erase(I); + return false; case TargetOpcode::COPY: if (!expandCopy(MBB, I)) return false; @@ -137,9 +147,9 @@ void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); @@ -157,9 +167,9 @@ void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); @@ -180,9 +190,9 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); @@ -210,9 +220,9 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); @@ -245,9 +255,9 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, // copy dst_hi, $vr1 const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; @@ -269,9 +279,10 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, } /// This method expands the same instruction that MipsSEInstrInfo:: -/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is -/// not available. It is implemented here because frame indexes are -/// eliminated before MipsSEInstrInfo::expandBuildPairF64 is called. +/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not +/// available and the case where the ABI is FP64A. It is implemented here +/// because frame indexes are eliminated before MipsSEInstrInfo:: +/// expandBuildPairF64 is called. bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const { @@ -280,27 +291,40 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, // // The case where dmtc1 is available doesn't need to be handled here // because it never creates a BuildPairF64 node. + // + // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence + // for odd-numbered double precision values (because the lower 32-bits is + // transferred with mtc1 which is redirected to the upper half of the even + // register). Unfortunately, we have to make this decision before register + // allocation so for now we use a spill/reload sequence for all + // double-precision values in regardless of being an odd/even register. const TargetMachine &TM = MF.getTarget(); - if (TM.getSubtarget().isABI_FPXX() - && !TM.getSubtarget().hasMTHC1()) { - const MipsSEInstrInfo &TII = - *static_cast(TM.getInstrInfo()); - const MipsRegisterInfo &TRI = - *static_cast(TM.getRegisterInfo()); + const MipsSubtarget &Subtarget = TM.getSubtarget(); + if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || + (FP64 && !Subtarget.useOddSPReg())) { + const MipsSEInstrInfo &TII = *static_cast( + TM.getSubtargetImpl()->getInstrInfo()); + const MipsRegisterInfo &TRI = *static_cast( + TM.getSubtargetImpl()->getRegisterInfo()); unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(); unsigned HiReg = I->getOperand(2).getReg(); // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are - // the cases where mthc1 is not available). - assert(!TM.getSubtarget().isFP64bit()); + // the cases where mthc1 is not available). 64-bit architectures and + // MIPS32r2 or later can use FGR64 though. + assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || + !Subtarget.isFP64bit()); const TargetRegisterClass *RC = &Mips::GPR32RegClass; - const TargetRegisterClass *RC2 = &Mips::AFGR64RegClass; + const TargetRegisterClass *RC2 = + FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; - int FI = MF.getInfo()->getBuildPairF64_FI(RC2); + // We re-use the same spill slot each time so that the stack frame doesn't + // grow too much in functions with a large number of moves. + int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC2); TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI, 0); TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI, @@ -312,6 +336,62 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, return false; } +/// This method expands the same instruction that MipsSEInstrInfo:: +/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not +/// available and the case where the ABI is FP64A. It is implemented here +/// because frame indexes are eliminated before MipsSEInstrInfo:: +/// expandExtractElementF64 is called. +bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + bool FP64) const { + // For fpxx and when mfhc1 is not available, use: + // spill + reload via ldc1 + // + // The case where dmfc1 is available doesn't need to be handled here + // because it never creates a ExtractElementF64 node. + // + // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence + // for odd-numbered double precision values (because the lower 32-bits is + // transferred with mfc1 which is redirected to the upper half of the even + // register). Unfortunately, we have to make this decision before register + // allocation so for now we use a spill/reload sequence for all + // double-precision values in regardless of being an odd/even register. + + const TargetMachine &TM = MF.getTarget(); + const MipsSubtarget &Subtarget = TM.getSubtarget(); + if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || + (FP64 && !Subtarget.useOddSPReg())) { + const MipsSEInstrInfo &TII = *static_cast( + TM.getSubtargetImpl()->getInstrInfo()); + const MipsRegisterInfo &TRI = *static_cast( + TM.getSubtargetImpl()->getRegisterInfo()); + + unsigned DstReg = I->getOperand(0).getReg(); + unsigned SrcReg = I->getOperand(1).getReg(); + unsigned N = I->getOperand(2).getImm(); + + // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are + // the cases where mfhc1 is not available). 64-bit architectures and + // MIPS32r2 or later can use FGR64 though. + assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || + !Subtarget.isFP64bit()); + + const TargetRegisterClass *RC = + FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; + const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; + + // We re-use the same spill slot each time so that the stack frame doesn't + // grow too much in functions with a large number of moves. + int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC); + TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI, + 0); + TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, N * 4); + return true; + } + + return false; +} + MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) : MipsFrameLowering(STI, STI.stackAlignment()) {} @@ -332,9 +412,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MipsFunctionInfo *MipsFI = MF.getInfo(); const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -467,9 +547,9 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MipsFunctionInfo *MipsFI = MF.getInfo(); const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast(MF.getTarget().getRegisterInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast( + MF.getSubtarget().getRegisterInfo()); DebugLoc dl = MBBI->getDebugLoc(); unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; @@ -522,7 +602,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); MachineBasicBlock *EntryBlock = MF->begin(); - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is @@ -563,7 +643,7 @@ void MipsSEFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const MipsSEInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); + *static_cast(MF.getSubtarget().getInstrInfo()); if (!hasReservedCallFrame(MF)) { int64_t Amount = I->getOperand(0).getImm();