X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsMSAInstrInfo.td;h=82c51a6473daa536ddc3c7f1ed7d833f5bea2ddd;hb=26651c7a6602626cf13ff3cda13f3ec2401bf790;hp=f16977dde53c30f9d6a1380b9e78fcc8d423134c;hpb=45ecbfc8e58923131068dced0cf89348ac61208f;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index f16977dde53..82c51a6473d 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -61,16 +61,35 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", // Operands -def uimm3 : Operand { +def uimm2 : Operand { let PrintMethod = "printUnsignedImm"; } -def uimm4 : Operand { +// The immediate of an LSA instruction needs special handling +// as the encoded value should be subtracted by one. +def uimm2LSAAsmOperand : AsmOperandClass { + let Name = "LSAImm"; + let ParserMethod = "parseLSAImm"; + let RenderMethod = "addImmOperands"; +} + +def LSAImm : Operand { let PrintMethod = "printUnsignedImm"; + let EncoderMethod = "getLSAImmEncoding"; + let DecoderMethod = "DecodeLSAImm"; + let ParserMatchClass = uimm2LSAAsmOperand; +} + +def uimm3 : Operand { + let PrintMethod = "printUnsignedImm8"; +} + +def uimm4 : Operand { + let PrintMethod = "printUnsignedImm8"; } def uimm8 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUnsignedImm8"; } def simm5 : Operand; @@ -86,29 +105,31 @@ def vsplat_uimm2 : Operand { } def vsplat_uimm3 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUnsignedImm8"; } def vsplat_uimm4 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUnsignedImm8"; } def vsplat_uimm5 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUnsignedImm8"; } def vsplat_uimm6 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUnsignedImm8"; } def vsplat_uimm8 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUnsignedImm8"; } def vsplat_simm5 : Operand; def vsplat_simm10 : Operand; +def immZExt2Lsa : ImmLeaf(Imm - 1);}]>; + // Pattern fragments def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), (MipsVExtractSExt node:$vec, node:$idx, i8)>; @@ -212,6 +233,20 @@ def vsplati32 : PatFrag<(ops node:$e0), node:$e0, node:$e0))>; def vsplati64 : PatFrag<(ops node:$e0), (v2i64 (build_vector:$v0 node:$e0, node:$e0))>; +def vsplatf32 : PatFrag<(ops node:$e0), + (v4f32 (build_vector node:$e0, node:$e0, + node:$e0, node:$e0))>; +def vsplatf64 : PatFrag<(ops node:$e0), + (v2f64 (build_vector node:$e0, node:$e0))>; + +def vsplati8_elt : PatFrag<(ops node:$v, node:$i), + (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; +def vsplati16_elt : PatFrag<(ops node:$v, node:$i), + (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; +def vsplati32_elt : PatFrag<(ops node:$v, node:$i), + (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; +def vsplati64_elt : PatFrag<(ops node:$v, node:$i), + (MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>; class SplatPatLeaf @@ -295,6 +330,78 @@ def vsplati64_simm5 : SplatComplexPattern; +// Any build_vector that is a constant splat with a value that is the bitwise +// inverse of an exact power of 2 +def vsplat_uimm_inv_pow2 : ComplexPattern; + +// Any build_vector that is a constant splat with only a consecutive sequence +// of left-most bits set. +def vsplat_maskl_bits : SplatComplexPattern; + +// Any build_vector that is a constant splat with only a consecutive sequence +// of right-most bits set. +def vsplat_maskr_bits : SplatComplexPattern; + +// Any build_vector that is a constant splat with a value that equals 1 +// FIXME: These should be a ComplexPattern but we can't use them because the +// ISel generator requires the uses to have a name, but providing a name +// causes other errors ("used in pattern but not operand list") +def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ + APInt Imm; + EVT EltTy = N->getValueType(0).getVectorElementType(); + + return selectVSplat (N, Imm) && + Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; +}]>; + +def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ + APInt Imm; + SDNode *BV = N->getOperand(0).getNode(); + EVT EltTy = N->getValueType(0).getVectorElementType(); + + return selectVSplat (BV, Imm) && + Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; +}]>; + +def vbclr_b : PatFrag<(ops node:$ws, node:$wt), + (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), + immAllOnesV))>; +def vbclr_h : PatFrag<(ops node:$ws, node:$wt), + (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), + immAllOnesV))>; +def vbclr_w : PatFrag<(ops node:$ws, node:$wt), + (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), + immAllOnesV))>; +def vbclr_d : PatFrag<(ops node:$ws, node:$wt), + (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), + node:$wt), + (bitconvert (v4i32 immAllOnesV))))>; + +def vbneg_b : PatFrag<(ops node:$ws, node:$wt), + (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; +def vbneg_h : PatFrag<(ops node:$ws, node:$wt), + (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; +def vbneg_w : PatFrag<(ops node:$ws, node:$wt), + (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; +def vbneg_d : PatFrag<(ops node:$ws, node:$wt), + (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), + node:$wt))>; + +def vbset_b : PatFrag<(ops node:$ws, node:$wt), + (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; +def vbset_h : PatFrag<(ops node:$ws, node:$wt), + (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; +def vbset_w : PatFrag<(ops node:$ws, node:$wt), + (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; +def vbset_d : PatFrag<(ops node:$ws, node:$wt), + (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), + node:$wt))>; + def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt), (fsub node:$wd, (fmul node:$ws, node:$wt))>; @@ -304,6 +411,9 @@ def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), (sub node:$wd, (mul node:$ws, node:$wt))>; +def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), + (fmul node:$ws, (fexp2 node:$wt))>; + // Immediates def immSExt5 : ImmLeaf(Imm);}]>; def immSExt10: ImmLeaf(Imm);}]>; @@ -421,14 +531,14 @@ class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; -class BNZ_B_ENC : MSA_I10_FMT<0b000, 0b00, 0b001100>; -class BNZ_H_ENC : MSA_I10_FMT<0b000, 0b01, 0b001100>; -class BNZ_W_ENC : MSA_I10_FMT<0b000, 0b10, 0b001100>; -class BNZ_D_ENC : MSA_I10_FMT<0b000, 0b11, 0b001100>; +class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; +class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; +class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; +class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; -class BNZ_V_ENC : MSA_VEC_FMT<0b01000, 0b011110>; +class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; -class BSEL_V_ENC : MSA_VECS10_FMT<0b00110, 0b011110>; +class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; @@ -442,12 +552,12 @@ class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; -class BZ_B_ENC : MSA_I10_FMT<0b001, 0b00, 0b001100>; -class BZ_H_ENC : MSA_I10_FMT<0b001, 0b01, 0b001100>; -class BZ_W_ENC : MSA_I10_FMT<0b001, 0b10, 0b001100>; -class BZ_D_ENC : MSA_I10_FMT<0b001, 0b11, 0b001100>; +class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; +class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; +class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; +class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; -class BZ_V_ENC : MSA_VECS10_FMT<0b01001, 0b011110>; +class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; @@ -459,7 +569,7 @@ class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; -class CFCMSA_ENC : MSA_ELM_FMT<0b0001111110, 0b011001>; +class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; @@ -501,15 +611,15 @@ class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; -class COPY_S_B_ENC : MSA_ELM_B_FMT<0b0010, 0b011001>; -class COPY_S_H_ENC : MSA_ELM_H_FMT<0b0010, 0b011001>; -class COPY_S_W_ENC : MSA_ELM_W_FMT<0b0010, 0b011001>; +class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; +class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; +class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; -class COPY_U_B_ENC : MSA_ELM_B_FMT<0b0011, 0b011001>; -class COPY_U_H_ENC : MSA_ELM_H_FMT<0b0011, 0b011001>; -class COPY_U_W_ENC : MSA_ELM_W_FMT<0b0011, 0b011001>; +class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; +class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; +class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; -class CTCMSA_ENC : MSA_ELM_FMT<0b0000111110, 0b011001>; +class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; @@ -687,12 +797,6 @@ class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; -class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; -class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; - -class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; -class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; - class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; @@ -702,6 +806,12 @@ class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; +class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; +class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; + +class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; +class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; + class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; @@ -747,20 +857,17 @@ class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; -class LD_B_ENC : MSA_I5_FMT<0b110, 0b00, 0b000111>; -class LD_H_ENC : MSA_I5_FMT<0b110, 0b01, 0b000111>; -class LD_W_ENC : MSA_I5_FMT<0b110, 0b10, 0b000111>; -class LD_D_ENC : MSA_I5_FMT<0b110, 0b11, 0b000111>; +class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; +class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; +class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; +class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; -class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>; -class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>; -class LDI_W_ENC : MSA_I10_FMT<0b010, 0b10, 0b001100>; -class LDI_D_ENC : MSA_I10_FMT<0b010, 0b11, 0b001100>; +class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; +class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; +class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; +class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; -class LDX_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001111>; -class LDX_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001111>; -class LDX_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001111>; -class LDX_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001111>; +class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; @@ -904,10 +1011,10 @@ class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; -class SLD_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010100>; -class SLD_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010100>; -class SLD_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010100>; -class SLD_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010100>; +class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; +class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; +class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; +class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; @@ -924,10 +1031,10 @@ class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; -class SPLAT_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010100>; -class SPLAT_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010100>; -class SPLAT_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010100>; -class SPLAT_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010100>; +class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; +class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; +class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; +class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; @@ -974,15 +1081,10 @@ class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; -class ST_B_ENC : MSA_I5_FMT<0b111, 0b00, 0b000111>; -class ST_H_ENC : MSA_I5_FMT<0b111, 0b01, 0b000111>; -class ST_W_ENC : MSA_I5_FMT<0b111, 0b10, 0b000111>; -class ST_D_ENC : MSA_I5_FMT<0b111, 0b11, 0b000111>; - -class STX_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001111>; -class STX_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001111>; -class STX_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001111>; -class STX_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001111>; +class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; +class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; +class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; +class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; @@ -1025,63 +1127,147 @@ class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; // Instruction desc. class MSA_BIT_B_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, uimm3:$u3); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u3"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt3:$u3))]; + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; InstrItinClass Itinerary = itin; } class MSA_BIT_H_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, uimm4:$u4); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u4"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt4:$u4))]; + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; InstrItinClass Itinerary = itin; } class MSA_BIT_W_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, uimm5:$u5); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u5"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt5:$u5))]; + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; InstrItinClass Itinerary = itin; } class MSA_BIT_D_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, uimm6:$u6); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u6"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, immZExt6:$u6))]; + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; + InstrItinClass Itinerary = itin; +} + +// This class is deprecated and will be removed soon. +class MSA_BIT_B_X_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, uimm3:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))]; InstrItinClass Itinerary = itin; } +// This class is deprecated and will be removed soon. +class MSA_BIT_H_X_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, uimm4:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))]; + InstrItinClass Itinerary = itin; +} + +// This class is deprecated and will be removed soon. +class MSA_BIT_W_X_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, uimm5:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))]; + InstrItinClass Itinerary = itin; +} + +// This class is deprecated and will be removed soon. +class MSA_BIT_D_X_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, uimm6:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))]; + InstrItinClass Itinerary = itin; +} + +class MSA_BIT_BINSXI_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$wd_in), + ROWS:$ws))]; + InstrItinClass Itinerary = itin; + string Constraints = "$wd = $wd_in"; +} + +class MSA_BIT_BINSLI_DESC_BASE : + MSA_BIT_BINSXI_DESC_BASE; + +class MSA_BIT_BINSRI_DESC_BASE : + MSA_BIT_BINSXI_DESC_BASE; + class MSA_BIT_SPLAT_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, SplatImm.OpClass:$u); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, SplatImm:$u))]; + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; InstrItinClass Itinerary = itin; } class MSA_COPY_DESC_BASE { - dag OutOperandList = (outs RCD:$rd); - dag InOperandList = (ins RCWS:$ws, uimm4:$n); + dag OutOperandList = (outs ROD:$rd); + dag InOperandList = (ins ROWS:$ws, uimm4:$n); string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); - list Pattern = [(set RCD:$rd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]; + list Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4:$n))]; + InstrItinClass Itinerary = itin; +} + +class MSA_ELM_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, uimm4:$n); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$n))]; InstrItinClass Itinerary = itin; } @@ -1135,11 +1321,11 @@ class MSA_I8_SHF_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins vsplat_simm10:$i10); - string AsmString = !strconcat(instr_asm, "\t$wd, $i10"); + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins vsplat_simm10:$s10); + string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp list Pattern = []; bit hasSideEffects = 0; @@ -1158,15 +1344,22 @@ class MSA_2R_DESC_BASE { dag OutOperandList = (outs ROWD:$wd); - dag InOperandList = (ins ROWS:$rs); + dag InOperandList = (ins ROS:$rs); string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); - list Pattern = [(set ROWD:$wd, (VT (OpNode ROWS:$rs)))]; + list Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; InstrItinClass Itinerary = itin; } +class MSA_2R_FILL_PSEUDO_BASE : + MipsPseudo<(outs RCWD:$wd), (ins RCWS:$fs), + [(set RCWD:$wd, (OpNode RCWS:$fs))]> { + let usesCustomInserter = 1; +} + class MSA_2RF_DESC_BASE { @@ -1188,6 +1381,29 @@ class MSA_3R_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); + list Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, + ROWT:$wt))]; + string Constraints = "$wd = $wd_in"; + InstrItinClass Itinerary = itin; +} + +class MSA_3R_SPLAT_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, GPR32:$rt); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))]; + InstrItinClass Itinerary = itin; +} + class MSA_3R_VSHF_DESC_BASE { + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, GPR32:$rt); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32:$rt))]; + InstrItinClass Itinerary = itin; +} + class MSA_3R_4R_DESC_BASE : MSA_3R_4R_DESC_BASE; -class MSA_CBRANCH_DESC_BASE { +class MSA_CBRANCH_DESC_BASE { dag OutOperandList = (outs); - dag InOperandList = (ins RCWD:$wd, brtarget:$offset); - string AsmString = !strconcat(instr_asm, "\t$wd, $offset"); + dag InOperandList = (ins ROWD:$wt, brtarget:$offset); + string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); list Pattern = []; InstrItinClass Itinerary = IIBranch; bit isBranch = 1; @@ -1252,55 +1478,55 @@ class MSA_INSERT_DESC_BASE : - MipsPseudo<(outs RCWD:$wd), (ins RCWD:$wd_in, uimm6:$n, RCFS:$fs), - [(set RCWD:$wd, (OpNode (Ty RCWD:$wd_in), RCFS:$fs, + RegisterOperand ROWD, RegisterOperand ROFS> : + MipsPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs), + [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, immZExt6:$n))]> { bit usesCustomInserter = 1; string Constraints = "$wd = $wd_in"; } class MSA_INSVE_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWD:$wd_in, uimm6:$n, RCWS:$ws); + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws); string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]"); - list Pattern = [(set RCWD:$wd, (OpNode RCWD:$wd_in, + list Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, immZExt6:$n, - RCWS:$ws))]; + ROWS:$ws))]; InstrItinClass Itinerary = itin; string Constraints = "$wd = $wd_in"; } class MSA_VEC_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, RCWT:$wt); + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, ROWT:$wt); string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); - list Pattern = [(set RCWD:$wd, (OpNode RCWS:$ws, RCWT:$wt))]; + list Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; InstrItinClass Itinerary = itin; } class MSA_ELM_SPLAT_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins RCWS:$ws, SplatImm.OpClass:$u3); - string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$u3]"); - list Pattern = [(set RCWD:$wd, (MipsVSHF SplatImm:$u3, RCWS:$ws, - RCWS:$ws))]; + dag OutOperandList = (outs ROWD:$wd); + dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); + string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); + list Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, + ROWS:$ws))]; InstrItinClass Itinerary = itin; } -class MSA_VEC_PSEUDO_BASE : - MipsPseudo<(outs RCWD:$wd), (ins RCWS:$ws, RCWT:$wt), - [(set RCWD:$wd, (OpNode RCWS:$ws, RCWT:$wt))]>; +class MSA_VEC_PSEUDO_BASE : + MipsPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), + [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, IsCommutable; @@ -1352,10 +1578,10 @@ class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, MSA128DOpnd>; -class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128B>; -class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; +class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, MSA128BOpnd>; @@ -1414,76 +1640,121 @@ class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, MSA128DOpnd>, IsCommutable; -class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", int_mips_bclr_b, MSA128BOpnd>; -class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", int_mips_bclr_h, MSA128HOpnd>; -class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", int_mips_bclr_w, MSA128WOpnd>; -class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", int_mips_bclr_d, MSA128DOpnd>; - -class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", int_mips_bclri_b, MSA128B>; -class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", int_mips_bclri_h, MSA128H>; -class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w, MSA128W>; -class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d, MSA128D>; - -class BINSL_B_DESC : MSA_3R_DESC_BASE<"binsl.b", int_mips_binsl_b, MSA128BOpnd>; -class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>; -class BINSL_W_DESC : MSA_3R_DESC_BASE<"binsl.w", int_mips_binsl_w, MSA128WOpnd>; -class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>; - -class BINSLI_B_DESC : MSA_BIT_B_DESC_BASE<"binsli.b", int_mips_binsli_b, - MSA128B>; -class BINSLI_H_DESC : MSA_BIT_H_DESC_BASE<"binsli.h", int_mips_binsli_h, - MSA128H>; -class BINSLI_W_DESC : MSA_BIT_W_DESC_BASE<"binsli.w", int_mips_binsli_w, - MSA128W>; -class BINSLI_D_DESC : MSA_BIT_D_DESC_BASE<"binsli.d", int_mips_binsli_d, - MSA128D>; - -class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>; -class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>; -class BINSR_W_DESC : MSA_3R_DESC_BASE<"binsr.w", int_mips_binsr_w, MSA128WOpnd>; -class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>; - -class BINSRI_B_DESC : MSA_BIT_B_DESC_BASE<"binsri.b", int_mips_binsri_b, - MSA128B>; -class BINSRI_H_DESC : MSA_BIT_H_DESC_BASE<"binsri.h", int_mips_binsri_h, - MSA128H>; -class BINSRI_W_DESC : MSA_BIT_W_DESC_BASE<"binsri.w", int_mips_binsri_w, - MSA128W>; -class BINSRI_D_DESC : MSA_BIT_D_DESC_BASE<"binsri.d", int_mips_binsri_d, - MSA128D>; - -class BMNZ_V_DESC : MSA_VEC_DESC_BASE<"bmnz.v", int_mips_bmnz_v, MSA128B>; - -class BMNZI_B_DESC : MSA_I8_X_DESC_BASE<"bmnzi.b", int_mips_bmnzi_b, - MSA128BOpnd>; - -class BMZ_V_DESC : MSA_VEC_DESC_BASE<"bmz.v", int_mips_bmz_v, MSA128B>; - -class BMZI_B_DESC : MSA_I8_X_DESC_BASE<"bmzi.b", int_mips_bmzi_b, MSA128BOpnd>; - -class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", int_mips_bneg_b, MSA128BOpnd>; -class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", int_mips_bneg_h, MSA128HOpnd>; -class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", int_mips_bneg_w, MSA128WOpnd>; -class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", int_mips_bneg_d, MSA128DOpnd>; - -class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", int_mips_bnegi_b, MSA128B>; -class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", int_mips_bnegi_h, MSA128H>; -class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", int_mips_bnegi_w, MSA128W>; -class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", int_mips_bnegi_d, MSA128D>; - -class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128B>; -class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128H>; -class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128W>; -class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128D>; - -class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128B>; +class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; +class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; +class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; +class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; + +class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, + MSA128BOpnd>; +class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, + MSA128HOpnd>; +class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, + MSA128WOpnd>; +class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, + MSA128DOpnd>; + +class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, + MSA128BOpnd>; +class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, + MSA128HOpnd>; +class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, + MSA128WOpnd>; +class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, + MSA128DOpnd>; + +class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>; +class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>; +class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>; +class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>; + +class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, + MSA128BOpnd>; +class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, + MSA128HOpnd>; +class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, + MSA128WOpnd>; +class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, + MSA128DOpnd>; + +class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>; +class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>; +class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>; +class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>; + +class BMNZ_V_DESC { + dag OutOperandList = (outs MSA128BOpnd:$wd); + dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, + MSA128BOpnd:$wt); + string AsmString = "bmnz.v\t$wd, $ws, $wt"; + list Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, + MSA128BOpnd:$ws, + MSA128BOpnd:$wd_in))]; + InstrItinClass Itinerary = NoItinerary; + string Constraints = "$wd = $wd_in"; +} + +class BMNZI_B_DESC { + dag OutOperandList = (outs MSA128BOpnd:$wd); + dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, + vsplat_uimm8:$u8); + string AsmString = "bmnzi.b\t$wd, $ws, $u8"; + list Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, + MSA128BOpnd:$ws, + MSA128BOpnd:$wd_in))]; + InstrItinClass Itinerary = NoItinerary; + string Constraints = "$wd = $wd_in"; +} + +class BMZ_V_DESC { + dag OutOperandList = (outs MSA128BOpnd:$wd); + dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, + MSA128BOpnd:$wt); + string AsmString = "bmz.v\t$wd, $ws, $wt"; + list Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, + MSA128BOpnd:$wd_in, + MSA128BOpnd:$ws))]; + InstrItinClass Itinerary = NoItinerary; + string Constraints = "$wd = $wd_in"; +} + +class BMZI_B_DESC { + dag OutOperandList = (outs MSA128BOpnd:$wd); + dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, + vsplat_uimm8:$u8); + string AsmString = "bmzi.b\t$wd, $ws, $u8"; + list Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, + MSA128BOpnd:$wd_in, + MSA128BOpnd:$ws))]; + InstrItinClass Itinerary = NoItinerary; + string Constraints = "$wd = $wd_in"; +} + +class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; +class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; +class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; +class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; + +class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, MSA128BOpnd>; +class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, MSA128HOpnd>; +class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, MSA128WOpnd>; +class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, MSA128DOpnd>; + +class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; +class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; +class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; +class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; + +class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; class BSEL_V_DESC { - dag OutOperandList = (outs MSA128B:$wd); - dag InOperandList = (ins MSA128B:$wd_in, MSA128B:$ws, MSA128B:$wt); + dag OutOperandList = (outs MSA128BOpnd:$wd); + dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, + MSA128BOpnd:$wt); string AsmString = "bsel.v\t$wd, $ws, $wt"; - list Pattern = [(set MSA128B:$wd, (vselect MSA128B:$wd_in, MSA128B:$ws, - MSA128B:$wt))]; + list Pattern = [(set MSA128BOpnd:$wd, + (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, + MSA128BOpnd:$wt))]; InstrItinClass Itinerary = NoItinerary; string Constraints = "$wd = $wd_in"; } @@ -1500,22 +1771,26 @@ class BSELI_B_DESC { string Constraints = "$wd = $wd_in"; } -class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", int_mips_bset_b, MSA128BOpnd>; -class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", int_mips_bset_h, MSA128HOpnd>; -class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", int_mips_bset_w, MSA128WOpnd>; -class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", int_mips_bset_d, MSA128DOpnd>; +class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; +class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; +class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; +class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; -class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", int_mips_bseti_b, MSA128B>; -class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", int_mips_bseti_h, MSA128H>; -class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", int_mips_bseti_w, MSA128W>; -class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", int_mips_bseti_d, MSA128D>; +class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, + MSA128BOpnd>; +class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, + MSA128HOpnd>; +class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, + MSA128WOpnd>; +class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, + MSA128DOpnd>; -class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128B>; -class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128H>; -class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128W>; -class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128D>; +class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; +class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; +class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; +class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; -class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128B>; +class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, IsCommutable; @@ -1536,8 +1811,8 @@ class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, MSA128DOpnd>; class CFCMSA_DESC { - dag OutOperandList = (outs GPR32:$rd); - dag InOperandList = (ins MSACtrl:$cs); + dag OutOperandList = (outs GPR32Opnd:$rd); + dag InOperandList = (ins MSA128CROpnd:$cs); string AsmString = "cfcmsa\t$rd, $cs"; InstrItinClass Itinerary = NoItinerary; bit hasSideEffects = 1; @@ -1600,18 +1875,18 @@ class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, vsplati64_uimm5, MSA128DOpnd>; class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, - GPR32, MSA128B>; + GPR32Opnd, MSA128BOpnd>; class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, - GPR32, MSA128H>; + GPR32Opnd, MSA128HOpnd>; class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, - GPR32, MSA128W>; + GPR32Opnd, MSA128WOpnd>; class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, - GPR32, MSA128B>; + GPR32Opnd, MSA128BOpnd>; class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, - GPR32, MSA128H>; + GPR32Opnd, MSA128HOpnd>; class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, - GPR32, MSA128W>; + GPR32Opnd, MSA128WOpnd>; class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE; @@ -1620,7 +1895,7 @@ class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE; -class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", int_mips_fexp2_w, - MSA128WOpnd>; -class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", int_mips_fexp2_d, - MSA128DOpnd>; +// The fexp2.df instruction multiplies the first operand by 2 to the power of +// the second operand. We therefore need a pseudo-insn in order to invent the +// 1.0 when we only need to match ISD::FEXP2. +class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; +class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; +let usesCustomInserter = 1 in { + class FEXP2_W_1_PSEUDO_DESC : + MipsPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), + [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; + class FEXP2_D_1_PSEUDO_DESC : + MipsPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), + [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; +} class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, MSA128WOpnd, MSA128HOpnd>; @@ -1803,6 +2087,11 @@ class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, MSA128WOpnd, GPR32Opnd>; +class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE; +class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE; + class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; @@ -1891,16 +2180,6 @@ class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, MSA128DOpnd>; -class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, - MSA128WOpnd>; -class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, - MSA128DOpnd>; - -class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, - MSA128WOpnd>; -class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, - MSA128DOpnd>; - class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, MSA128WOpnd>; class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, @@ -1916,6 +2195,16 @@ class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; +class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, + MSA128WOpnd>; +class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, + MSA128DOpnd>; + +class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, + MSA128WOpnd>; +class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, + MSA128DOpnd>; + class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, @@ -1972,52 +2261,51 @@ class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, MSA128WOpnd, GPR32Opnd>; class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE; + MSA128WOpnd, FGR32Opnd>; class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE; + MSA128DOpnd, FGR64Opnd>; -class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b, MSA128B>; -class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h, MSA128H>; -class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w, MSA128W>; -class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, MSA128D>; +class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b, + MSA128BOpnd>; +class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h, + MSA128HOpnd>; +class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w, + MSA128WOpnd>; +class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, + MSA128DOpnd>; class LD_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); + dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addr); string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); - list Pattern = [(set RCWD:$wd, (TyNode (OpNode Addr:$addr)))]; + list Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; InstrItinClass Itinerary = itin; + string DecoderMethod = "DecodeMSA128Mem"; } -class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128B>; -class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128H>; -class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128W>; -class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128D>; - -class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128B>; -class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128H>; -class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128W>; -class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128D>; - -class LDX_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); - dag InOperandList = (ins MemOpnd:$addr); - string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); - list Pattern = [(set RCWD:$wd, (TyNode (OpNode Addr:$addr)))]; - InstrItinClass Itinerary = itin; +class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>; +class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>; +class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>; +class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>; + +class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; +class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; +class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; +class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; + +class LSA_DESC { + dag OutOperandList = (outs GPR32Opnd:$rd); + dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, LSAImm:$sa); + string AsmString = "lsa\t$rd, $rs, $rt, $sa"; + list Pattern = [(set GPR32Opnd:$rd, (add GPR32Opnd:$rs, + (shl GPR32Opnd:$rt, + immZExt2Lsa:$sa)))]; + InstrItinClass Itinerary = NoItinerary; } -class LDX_B_DESC : LDX_DESC_BASE<"ldx.b", load, v16i8, MSA128B>; -class LDX_H_DESC : LDX_DESC_BASE<"ldx.h", load, v8i16, MSA128H>; -class LDX_W_DESC : LDX_DESC_BASE<"ldx.w", load, v4i32, MSA128W>; -class LDX_D_DESC : LDX_DESC_BASE<"ldx.d", load, v2i64, MSA128D>; - class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, MSA128HOpnd>; class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, @@ -2110,8 +2398,8 @@ class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; class MOVE_V_DESC { - dag OutOperandList = (outs MSA128B:$wd); - dag InOperandList = (ins MSA128B:$ws); + dag OutOperandList = (outs MSA128BOpnd:$wd); + dag InOperandList = (ins MSA128BOpnd:$ws); string AsmString = "move.v\t$wd, $ws"; list Pattern = []; InstrItinClass Itinerary = NoItinerary; @@ -2157,18 +2445,18 @@ class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; -class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128B>; -class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; +class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, MSA128BOpnd>; -class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128B>; -class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; +class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; @@ -2187,29 +2475,37 @@ class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; -class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b, MSA128B>; -class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h, MSA128H>; -class SAT_S_W_DESC : MSA_BIT_W_DESC_BASE<"sat_s.w", int_mips_sat_s_w, MSA128W>; -class SAT_S_D_DESC : MSA_BIT_D_DESC_BASE<"sat_s.d", int_mips_sat_s_d, MSA128D>; +class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, + MSA128BOpnd>; +class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, + MSA128HOpnd>; +class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, + MSA128WOpnd>; +class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, + MSA128DOpnd>; -class SAT_U_B_DESC : MSA_BIT_B_DESC_BASE<"sat_u.b", int_mips_sat_u_b, MSA128B>; -class SAT_U_H_DESC : MSA_BIT_H_DESC_BASE<"sat_u.h", int_mips_sat_u_h, MSA128H>; -class SAT_U_W_DESC : MSA_BIT_W_DESC_BASE<"sat_u.w", int_mips_sat_u_w, MSA128W>; -class SAT_U_D_DESC : MSA_BIT_D_DESC_BASE<"sat_u.d", int_mips_sat_u_d, MSA128D>; +class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, + MSA128BOpnd>; +class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, + MSA128HOpnd>; +class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, + MSA128WOpnd>; +class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, + MSA128DOpnd>; class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; -class SLD_B_DESC : MSA_3R_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; -class SLD_H_DESC : MSA_3R_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; -class SLD_W_DESC : MSA_3R_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; -class SLD_D_DESC : MSA_3R_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; +class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; +class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; +class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; +class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; -class SLDI_B_DESC : MSA_BIT_B_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128B>; -class SLDI_H_DESC : MSA_BIT_H_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128H>; -class SLDI_W_DESC : MSA_BIT_W_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128W>; -class SLDI_D_DESC : MSA_BIT_D_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128D>; +class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>; +class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>; +class SLDI_W_DESC : MSA_ELM_DESC_BASE<"sldi.w", int_mips_sldi_w, MSA128WOpnd>; +class SLDI_D_DESC : MSA_ELM_DESC_BASE<"sldi.d", int_mips_sldi_d, MSA128DOpnd>; class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; @@ -2217,31 +2513,31 @@ class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, - MSA128B>; + MSA128BOpnd>; class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, - MSA128H>; + MSA128HOpnd>; class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, - MSA128W>; + MSA128WOpnd>; class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, - MSA128D>; + MSA128DOpnd>; -class SPLAT_B_DESC : MSA_3R_DESC_BASE<"splat.b", int_mips_splat_b, MSA128BOpnd, - MSA128BOpnd, GPR32Opnd>; -class SPLAT_H_DESC : MSA_3R_DESC_BASE<"splat.h", int_mips_splat_h, MSA128HOpnd, - MSA128HOpnd, GPR32Opnd>; -class SPLAT_W_DESC : MSA_3R_DESC_BASE<"splat.w", int_mips_splat_w, MSA128WOpnd, - MSA128WOpnd, GPR32Opnd>; -class SPLAT_D_DESC : MSA_3R_DESC_BASE<"splat.d", int_mips_splat_d, MSA128DOpnd, - MSA128DOpnd, GPR32Opnd>; +class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, + MSA128BOpnd>; +class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, + MSA128HOpnd>; +class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, + MSA128WOpnd>; +class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, + MSA128DOpnd>; class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, - MSA128B>; + MSA128BOpnd>; class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, - MSA128H>; + MSA128HOpnd>; class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, - MSA128W>; + MSA128WOpnd>; class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, - MSA128D>; + MSA128DOpnd>; class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; @@ -2249,23 +2545,27 @@ class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, - MSA128B>; + MSA128BOpnd>; class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, - MSA128H>; + MSA128HOpnd>; class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, - MSA128W>; + MSA128WOpnd>; class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, - MSA128D>; + MSA128DOpnd>; class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; -class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b, MSA128B>; -class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h, MSA128H>; -class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w, MSA128W>; -class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d, MSA128D>; +class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b, + MSA128BOpnd>; +class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h, + MSA128HOpnd>; +class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w, + MSA128WOpnd>; +class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d, + MSA128DOpnd>; class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; @@ -2273,55 +2573,44 @@ class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, - MSA128B>; + MSA128BOpnd>; class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, - MSA128H>; + MSA128HOpnd>; class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, - MSA128W>; + MSA128WOpnd>; class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, - MSA128D>; + MSA128DOpnd>; class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; -class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b, MSA128B>; -class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h, MSA128H>; -class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w, MSA128W>; -class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d, MSA128D>; +class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b, + MSA128BOpnd>; +class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h, + MSA128HOpnd>; +class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w, + MSA128WOpnd>; +class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d, + MSA128DOpnd>; class ST_DESC_BASE { dag OutOperandList = (outs); - dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr); - string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); - list Pattern = [(OpNode (TyNode RCWD:$wd), Addr:$addr)]; - InstrItinClass Itinerary = itin; -} - -class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128B>; -class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128H>; -class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128W>; -class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128D>; - -class STX_DESC_BASE { - dag OutOperandList = (outs); - dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr); + dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); - list Pattern = [(OpNode (TyNode RCWD:$wd), Addr:$addr)]; + list Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; InstrItinClass Itinerary = itin; + string DecoderMethod = "DecodeMSA128Mem"; } -class STX_B_DESC : STX_DESC_BASE<"stx.b", store, v16i8, MSA128B>; -class STX_H_DESC : STX_DESC_BASE<"stx.h", store, v8i16, MSA128H>; -class STX_W_DESC : STX_DESC_BASE<"stx.w", store, v4i32, MSA128W>; -class STX_D_DESC : STX_DESC_BASE<"stx.d", store, v2i64, MSA128D>; +class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>; +class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>; +class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>; +class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>; class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, MSA128BOpnd>; @@ -2378,10 +2667,10 @@ class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; -class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128B>; -class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; -class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; +class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; +class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE; class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, MSA128BOpnd>; @@ -2419,14 +2708,17 @@ def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; def AND_V : AND_V_ENC, AND_V_DESC; def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, - PseudoInstExpansion<(AND_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, - PseudoInstExpansion<(AND_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, - PseudoInstExpansion<(AND_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; @@ -2517,19 +2809,19 @@ def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; -class MSA_BSEL_PSEUDO_BASE : - MipsPseudo<(outs RC:$wd), (ins RC:$wd_in, RC:$ws, RC:$wt), - [(set RC:$wd, (Ty (vselect RC:$wd_in, RC:$ws, RC:$wt)))]>, - PseudoInstExpansion<(BSEL_V MSA128B:$wd, MSA128B:$wd_in, MSA128B:$ws, - MSA128B:$wt)> { +class MSA_BSEL_PSEUDO_BASE : + MipsPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), + [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$ws, RO:$wt)))]>, + PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, + MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { let Constraints = "$wd_in = $wd"; } -def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE; -def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE; -def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE; -def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE; -def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE; +def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE; +def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE; +def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE; +def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE; +def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE; def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; @@ -2696,6 +2988,8 @@ def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; +def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; +def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; @@ -2718,6 +3012,8 @@ def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; def FILL_B : FILL_B_ENC, FILL_B_DESC; def FILL_H : FILL_H_ENC, FILL_H_DESC; def FILL_W : FILL_W_ENC, FILL_W_DESC; +def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; +def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; @@ -2791,12 +3087,6 @@ def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; -def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; -def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; - -def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; -def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; - def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; @@ -2806,6 +3096,12 @@ def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; +def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; +def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; + +def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; +def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; + def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; @@ -2867,10 +3163,7 @@ def LDI_H : LDI_H_ENC, LDI_H_DESC; def LDI_W : LDI_W_ENC, LDI_W_DESC; def LDI_D : LDI_D_ENC, LDI_D_DESC; -def LDX_B: LDX_B_ENC, LDX_B_DESC; -def LDX_H: LDX_H_ENC, LDX_H_DESC; -def LDX_W: LDX_W_ENC, LDX_W_DESC; -def LDX_D: LDX_D_ENC, LDX_D_DESC; +def LSA : LSA_ENC, LSA_DESC; def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; @@ -2979,27 +3272,33 @@ def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; def NOR_V : NOR_V_ENC, NOR_V_DESC; def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, - PseudoInstExpansion<(NOR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, - PseudoInstExpansion<(NOR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, - PseudoInstExpansion<(NOR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def NORI_B : NORI_B_ENC, NORI_B_DESC; def OR_V : OR_V_ENC, OR_V_DESC; def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, - PseudoInstExpansion<(OR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, - PseudoInstExpansion<(OR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, - PseudoInstExpansion<(OR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def ORI_B : ORI_B_ENC, ORI_B_DESC; @@ -3107,11 +3406,6 @@ def ST_H: ST_H_ENC, ST_H_DESC; def ST_W: ST_W_ENC, ST_W_DESC; def ST_D: ST_D_ENC, ST_D_DESC; -def STX_B: STX_B_ENC, STX_B_DESC; -def STX_H: STX_H_ENC, STX_H_DESC; -def STX_W: STX_W_ENC, STX_W_DESC; -def STX_D: STX_D_ENC, STX_D_DESC; - def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; @@ -3149,14 +3443,17 @@ def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; def XOR_V : XOR_V_ENC, XOR_V_DESC; def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, - PseudoInstExpansion<(XOR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, - PseudoInstExpansion<(XOR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, - PseudoInstExpansion<(XOR_V MSA128B:$wd, - MSA128B:$ws, MSA128B:$wt)>; + PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, + MSA128BOpnd:$ws, + MSA128BOpnd:$wt)>; def XORI_B : XORI_B_ENC, XORI_B_DESC;