X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsMCInstLower.cpp;h=8bdcfd9bc25e6cb727e502036e2d98fb69e2511f;hb=4147e4d054b62eb2ea8259db0385791ec23c460b;hp=6fc2af1a77159bdb33717ae390eb481554d6e432;hpb=421455f1ea081e2e1767e782ac0d57ca55976e9b;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsMCInstLower.cpp b/lib/Target/Mips/MipsMCInstLower.cpp index 6fc2af1a771..8bdcfd9bc25 100644 --- a/lib/Target/Mips/MipsMCInstLower.cpp +++ b/lib/Target/Mips/MipsMCInstLower.cpp @@ -12,9 +12,9 @@ // //===----------------------------------------------------------------------===// +#include "MipsMCInstLower.h" #include "MipsAsmPrinter.h" #include "MipsInstrInfo.h" -#include "MipsMCInstLower.h" #include "MCTargetDesc/MipsBaseInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" @@ -26,9 +26,13 @@ using namespace llvm; -MipsMCInstLower::MipsMCInstLower(Mangler *mang, const MachineFunction &mf, - MipsAsmPrinter &asmprinter) - : Ctx(mf.getContext()), Mang(mang), AsmPrinter(asmprinter) {} +MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter) + : AsmPrinter(asmprinter) {} + +void MipsMCInstLower::Initialize(Mangler *M, MCContext* C) { + Mang = M; + Ctx = C; +} MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, MachineOperandType MOTy, @@ -37,22 +41,26 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, const MCSymbol *Symbol; switch(MO.getTargetFlags()) { - default: assert(0 && "Invalid target flag!"); - case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break; - case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break; - case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break; - case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break; - case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break; - case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break; - case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break; - case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break; - case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break; - case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break; - case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break; - case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break; - case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break; - case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break; - case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break; + default: llvm_unreachable("Invalid target flag!"); + case MipsII::MO_NO_FLAG: Kind = MCSymbolRefExpr::VK_None; break; + case MipsII::MO_GPREL: Kind = MCSymbolRefExpr::VK_Mips_GPREL; break; + case MipsII::MO_GOT_CALL: Kind = MCSymbolRefExpr::VK_Mips_GOT_CALL; break; + case MipsII::MO_GOT16: Kind = MCSymbolRefExpr::VK_Mips_GOT16; break; + case MipsII::MO_GOT: Kind = MCSymbolRefExpr::VK_Mips_GOT; break; + case MipsII::MO_ABS_HI: Kind = MCSymbolRefExpr::VK_Mips_ABS_HI; break; + case MipsII::MO_ABS_LO: Kind = MCSymbolRefExpr::VK_Mips_ABS_LO; break; + case MipsII::MO_TLSGD: Kind = MCSymbolRefExpr::VK_Mips_TLSGD; break; + case MipsII::MO_TLSLDM: Kind = MCSymbolRefExpr::VK_Mips_TLSLDM; break; + case MipsII::MO_DTPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_HI; break; + case MipsII::MO_DTPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_DTPREL_LO; break; + case MipsII::MO_GOTTPREL: Kind = MCSymbolRefExpr::VK_Mips_GOTTPREL; break; + case MipsII::MO_TPREL_HI: Kind = MCSymbolRefExpr::VK_Mips_TPREL_HI; break; + case MipsII::MO_TPREL_LO: Kind = MCSymbolRefExpr::VK_Mips_TPREL_LO; break; + case MipsII::MO_GPOFF_HI: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_HI; break; + case MipsII::MO_GPOFF_LO: Kind = MCSymbolRefExpr::VK_Mips_GPOFF_LO; break; + case MipsII::MO_GOT_DISP: Kind = MCSymbolRefExpr::VK_Mips_GOT_DISP; break; + case MipsII::MO_GOT_PAGE: Kind = MCSymbolRefExpr::VK_Mips_GOT_PAGE; break; + case MipsII::MO_GOT_OFST: Kind = MCSymbolRefExpr::VK_Mips_GOT_OFST; break; } switch (MOTy) { @@ -85,75 +93,86 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO, default: llvm_unreachable(""); } - - const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, Ctx); + + const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, *Ctx); if (!Offset) return MCOperand::CreateExpr(MCSym); // Assume offset is never negative. assert(Offset > 0); - - const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx); - const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, Ctx); + + const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, *Ctx); + const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, *Ctx); return MCOperand::CreateExpr(AddExpr); } +static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0, + const MCOperand& Opnd1, + const MCOperand& Opnd2 = MCOperand()) { + Inst.setOpcode(Opc); + Inst.addOperand(Opnd0); + Inst.addOperand(Opnd1); + if (Opnd2.isValid()) + Inst.addOperand(Opnd2); +} + // Lower ".cpload $reg" to // "lui $gp, %hi(_gp_disp)" // "addiu $gp, $gp, %lo(_gp_disp)" -// "addu $gp. $gp, $reg" -void MipsMCInstLower::LowerCPLOAD(const MachineInstr *MI, - SmallVector& MCInsts) { - MCInst Lui, Addiu, Addu; +// "addu $gp, $gp, $t9" +void MipsMCInstLower::LowerCPLOAD(SmallVector& MCInsts) { + MCOperand GPReg = MCOperand::CreateReg(Mips::GP); + MCOperand T9Reg = MCOperand::CreateReg(Mips::T9); StringRef SymName("_gp_disp"); - const MCSymbol *Symbol = Ctx.GetOrCreateSymbol(SymName); + const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName); const MCSymbolRefExpr *MCSym; - // lui $gp, %hi(_gp_disp) - Lui.setOpcode(Mips::LUi); - Lui.addOperand(MCOperand::CreateReg(Mips::GP)); - MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_HI, Ctx); - Lui.addOperand(MCOperand::CreateExpr(MCSym)); - MCInsts.push_back(Lui); - - // addiu $gp, $gp, %lo(_gp_disp) - Addiu.setOpcode(Mips::ADDiu); - Addiu.addOperand(MCOperand::CreateReg(Mips::GP)); - Addiu.addOperand(MCOperand::CreateReg(Mips::GP)); - MCSym = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_Mips_ABS_LO, Ctx); - Addiu.addOperand(MCOperand::CreateExpr(MCSym)); - MCInsts.push_back(Addiu); - - // addu $gp. $gp, $reg - Addu.setOpcode(Mips::ADDu); - Addu.addOperand(MCOperand::CreateReg(Mips::GP)); - Addu.addOperand(MCOperand::CreateReg(Mips::GP)); - const MachineOperand &MO = MI->getOperand(0); - assert(MO.isReg() && "CPLOAD's operand must be a register."); - Addu.addOperand(MCOperand::CreateReg(MO.getReg())); - MCInsts.push_back(Addu); + MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx); + MCOperand SymHi = MCOperand::CreateExpr(MCSym); + MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx); + MCOperand SymLo = MCOperand::CreateExpr(MCSym); + + MCInsts.resize(3); + + CreateMCInst(MCInsts[0], Mips::LUi, GPReg, SymHi); + CreateMCInst(MCInsts[1], Mips::ADDiu, GPReg, GPReg, SymLo); + CreateMCInst(MCInsts[2], Mips::ADDu, GPReg, GPReg, T9Reg); } // Lower ".cprestore offset" to "sw $gp, offset($sp)". -void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI, MCInst &OutMI) { - OutMI.clear(); - OutMI.setOpcode(Mips::SW); - OutMI.addOperand(MCOperand::CreateReg(Mips::GP)); - OutMI.addOperand(MCOperand::CreateReg(Mips::SP)); - const MachineOperand &MO = MI->getOperand(0); - assert(MO.isImm() && "CPRESTORE's operand must be an immediate."); - OutMI.addOperand(MCOperand::CreateImm(MO.getImm())); +void MipsMCInstLower::LowerCPRESTORE(int64_t Offset, + SmallVector& MCInsts) { + assert(isInt<32>(Offset) && (Offset >= 0) && + "Imm operand of .cprestore must be a non-negative 32-bit value."); + + MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg; + MCOperand GPReg = MCOperand::CreateReg(Mips::GP); + + if (!isInt<16>(Offset)) { + unsigned Hi = ((Offset + 0x8000) >> 16) & 0xffff; + Offset &= 0xffff; + MCOperand ATReg = MCOperand::CreateReg(Mips::AT); + BaseReg = ATReg; + + // lui at,hi + // addu at,at,sp + MCInsts.resize(2); + CreateMCInst(MCInsts[0], Mips::LUi, ATReg, MCOperand::CreateImm(Hi)); + CreateMCInst(MCInsts[1], Mips::ADDu, ATReg, ATReg, SPReg); + } + + MCInst Sw; + CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset)); + MCInsts.push_back(Sw); } MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO, - unsigned offset) const { + unsigned offset) const { MachineOperandType MOTy = MO.getType(); - + switch (MOTy) { - default: - assert(0 && "unknown operand type"); - break; + default: llvm_unreachable("unknown operand type"); case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) break; @@ -167,6 +186,8 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO, case MachineOperand::MO_ConstantPoolIndex: case MachineOperand::MO_BlockAddress: return LowerSymbolOperand(MO, MOTy, offset); + case MachineOperand::MO_RegisterMask: + break; } return MCOperand(); @@ -174,7 +195,7 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO, void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); - + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); MCOperand MCOp = LowerOperand(MO); @@ -185,114 +206,133 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { } void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI, - SmallVector& MCInsts) { + SmallVector& MCInsts) { unsigned Opc = MI->getOpcode(); - MCInst instr1, instr2, instr3, move; + MCInst Instr1, Instr2, Instr3, Move; - bool two_instructions = false; + bool TwoInstructions = false; assert(MI->getNumOperands() == 3); assert(MI->getOperand(0).isReg()); assert(MI->getOperand(1).isReg()); - MCOperand target = LowerOperand(MI->getOperand(0)); - MCOperand base = LowerOperand(MI->getOperand(1)); - MCOperand atReg = MCOperand::CreateReg(Mips::AT); - MCOperand zeroReg = MCOperand::CreateReg(Mips::ZERO); + MCOperand Target = LowerOperand(MI->getOperand(0)); + MCOperand Base = LowerOperand(MI->getOperand(1)); + MCOperand ATReg = MCOperand::CreateReg(Mips::AT); + MCOperand ZeroReg = MCOperand::CreateReg(Mips::ZERO); - MachineOperand unloweredName = MI->getOperand(2); - MCOperand name = LowerOperand(unloweredName); + MachineOperand UnLoweredName = MI->getOperand(2); + MCOperand Name = LowerOperand(UnLoweredName); - move.setOpcode(Mips::ADDu); - move.addOperand(target); - move.addOperand(atReg); - move.addOperand(zeroReg); + Move.setOpcode(Mips::ADDu); + Move.addOperand(Target); + Move.addOperand(ATReg); + Move.addOperand(ZeroReg); switch (Opc) { case Mips::ULW: { // FIXME: only works for little endian right now - MCOperand adj_name = LowerOperand(unloweredName, 3); - if (base.getReg() == (target.getReg())) { - instr1.setOpcode(Mips::LWL); - instr1.addOperand(atReg); - instr1.addOperand(base); - instr1.addOperand(adj_name); - instr2.setOpcode(Mips::LWR); - instr2.addOperand(atReg); - instr2.addOperand(base); - instr2.addOperand(name); - instr3 = move; + MCOperand AdjName = LowerOperand(UnLoweredName, 3); + if (Base.getReg() == (Target.getReg())) { + Instr1.setOpcode(Mips::LWL); + Instr1.addOperand(ATReg); + Instr1.addOperand(Base); + Instr1.addOperand(AdjName); + Instr2.setOpcode(Mips::LWR); + Instr2.addOperand(ATReg); + Instr2.addOperand(Base); + Instr2.addOperand(Name); + Instr3 = Move; } else { - two_instructions = true; - instr1.setOpcode(Mips::LWL); - instr1.addOperand(target); - instr1.addOperand(base); - instr1.addOperand(adj_name); - instr2.setOpcode(Mips::LWR); - instr2.addOperand(target); - instr2.addOperand(base); - instr2.addOperand(name); + TwoInstructions = true; + Instr1.setOpcode(Mips::LWL); + Instr1.addOperand(Target); + Instr1.addOperand(Base); + Instr1.addOperand(AdjName); + Instr2.setOpcode(Mips::LWR); + Instr2.addOperand(Target); + Instr2.addOperand(Base); + Instr2.addOperand(Name); } break; } case Mips::ULHu: { // FIXME: only works for little endian right now - MCOperand adj_name = LowerOperand(unloweredName, 1); - instr1.setOpcode(Mips::LBu); - instr1.addOperand(atReg); - instr1.addOperand(base); - instr1.addOperand(adj_name); - instr2.setOpcode(Mips::LBu); - instr2.addOperand(target); - instr2.addOperand(base); - instr2.addOperand(name); - instr3.setOpcode(Mips::INS); - instr3.addOperand(target); - instr3.addOperand(atReg); - instr3.addOperand(MCOperand::CreateImm(0x8)); - instr3.addOperand(MCOperand::CreateImm(0x18)); + MCOperand AdjName = LowerOperand(UnLoweredName, 1); + Instr1.setOpcode(Mips::LBu); + Instr1.addOperand(ATReg); + Instr1.addOperand(Base); + Instr1.addOperand(AdjName); + Instr2.setOpcode(Mips::LBu); + Instr2.addOperand(Target); + Instr2.addOperand(Base); + Instr2.addOperand(Name); + Instr3.setOpcode(Mips::INS); + Instr3.addOperand(Target); + Instr3.addOperand(ATReg); + Instr3.addOperand(MCOperand::CreateImm(0x8)); + Instr3.addOperand(MCOperand::CreateImm(0x18)); break; } case Mips::USW: { // FIXME: only works for little endian right now - assert (base.getReg() != target.getReg()); - two_instructions = true; - MCOperand adj_name = LowerOperand(unloweredName, 3); - instr1.setOpcode(Mips::SWL); - instr1.addOperand(target); - instr1.addOperand(base); - instr1.addOperand(adj_name); - instr2.setOpcode(Mips::SWR); - instr2.addOperand(target); - instr2.addOperand(base); - instr2.addOperand(name); + assert (Base.getReg() != Target.getReg()); + TwoInstructions = true; + MCOperand AdjName = LowerOperand(UnLoweredName, 3); + Instr1.setOpcode(Mips::SWL); + Instr1.addOperand(Target); + Instr1.addOperand(Base); + Instr1.addOperand(AdjName); + Instr2.setOpcode(Mips::SWR); + Instr2.addOperand(Target); + Instr2.addOperand(Base); + Instr2.addOperand(Name); break; } case Mips::USH: { - MCOperand adj_name = LowerOperand(unloweredName, 1); - instr1.setOpcode(Mips::SB); - instr1.addOperand(target); - instr1.addOperand(base); - instr1.addOperand(name); - instr2.setOpcode(Mips::SRL); - instr2.addOperand(atReg); - instr2.addOperand(target); - instr2.addOperand(MCOperand::CreateImm(8)); - instr3.setOpcode(Mips::SB); - instr3.addOperand(atReg); - instr3.addOperand(base); - instr3.addOperand(adj_name); + MCOperand AdjName = LowerOperand(UnLoweredName, 1); + Instr1.setOpcode(Mips::SB); + Instr1.addOperand(Target); + Instr1.addOperand(Base); + Instr1.addOperand(Name); + Instr2.setOpcode(Mips::SRL); + Instr2.addOperand(ATReg); + Instr2.addOperand(Target); + Instr2.addOperand(MCOperand::CreateImm(8)); + Instr3.setOpcode(Mips::SB); + Instr3.addOperand(ATReg); + Instr3.addOperand(Base); + Instr3.addOperand(AdjName); break; } default: // FIXME: need to add others - assert(0 && "unaligned instruction not processed"); + llvm_unreachable("unaligned instruction not processed"); } - MCInsts.push_back(instr1); - MCInsts.push_back(instr2); - if (!two_instructions) MCInsts.push_back(instr3); + MCInsts.push_back(Instr1); + MCInsts.push_back(Instr2); + if (!TwoInstructions) MCInsts.push_back(Instr3); } +// Create the following two instructions: +// "lui $2, %hi(_gp_disp)" +// "addiu $2, $2, %lo(_gp_disp)" +void MipsMCInstLower::LowerSETGP01(SmallVector& MCInsts) { + MCOperand RegOpnd = MCOperand::CreateReg(Mips::V0); + StringRef SymName("_gp_disp"); + const MCSymbol *Sym = Ctx->GetOrCreateSymbol(SymName); + const MCSymbolRefExpr *MCSym; + + MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx); + MCOperand SymHi = MCOperand::CreateExpr(MCSym); + MCSym = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx); + MCOperand SymLo = MCOperand::CreateExpr(MCSym); + + MCInsts.resize(2); + + CreateMCInst(MCInsts[0], Mips::LUi, RegOpnd, SymHi); + CreateMCInst(MCInsts[1], Mips::ADDiu, RegOpnd, RegOpnd, SymLo); +}