X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsInstrInfo.td;h=1584d296709e2f20eecbd12269c3a525f8016a36;hb=8e7aa4be58277562240e5083a18bd52d6e76abf5;hp=60e26683acedecfca8774124494a09571026beef;hpb=f862a4aefe2b50bc7643d27ae6689356cb977f63;p=oota-llvm.git diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 60e26683ace..1584d296709 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -168,10 +168,10 @@ def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, AssemblerPredicate<"FeatureMips64r2">; def IsN64 : Predicate<"Subtarget.isABI_N64()">, AssemblerPredicate<"FeatureN64">; -def NotN64 : Predicate<"!Subtarget.isABI_N64()">, - AssemblerPredicate<"!FeatureN64">; def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, AssemblerPredicate<"FeatureMips16">; +def HasCnMips : Predicate<"Subtarget.hasCnMips()">, + AssemblerPredicate<"FeatureCnMips">; def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, AssemblerPredicate<"FeatureMips32">; def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, @@ -187,6 +187,7 @@ def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">, AssemblerPredicate<"!FeatureMicroMips">; def IsLE : Predicate<"Subtarget.isLittle()">; def IsBE : Predicate<"!Subtarget.isLittle()">; +def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">; class MipsPat : Pat { let Predicates = [HasStdEnc]; @@ -248,6 +249,8 @@ def calltarget : Operand { let EncoderMethod = "getJumpTargetOpValue"; } +def simm10 : Operand; + def simm16 : Operand { let DecoderMethod= "DecodeSimm16"; } @@ -315,6 +318,7 @@ def mem : mem_generic; // MSA specific address operand def mem_msa : mem_generic { + let MIOperandInfo = (ops ptr_rc, simm10); let EncoderMethod = "getMSAMemEncoding"; } @@ -407,6 +411,8 @@ def addrRegReg : def addrDefault : ComplexPattern; +def addrimm10 : ComplexPattern; + //===----------------------------------------------------------------------===// // Instructions specific format //===----------------------------------------------------------------------===// @@ -420,6 +426,7 @@ class ArithLogicR { let isCommutable = isComm; let isReMaterializable = 1; + let TwoOperandAliasConstraint = "$rd = $rs"; } // Arithmetic and logical instructions with 2 register operands. @@ -612,7 +619,7 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in { class JumpLinkReg: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), - [], IIBranch, FrmR, opstr>; + [], IIBranch, FrmR>; class BGEZAL_FT : InstSE<(outs), (ins RO:$rs, opnd:$offset), @@ -768,7 +775,6 @@ class CountLeading1: [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>, Requires<[HasBitCount, HasStdEnc]>; - // Sign Extend in Register. class SignExtInReg : @@ -976,16 +982,16 @@ def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel, def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>; def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, LW_FM<0x23>; -def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; -def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; -def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; +def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>; +def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; +def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; /// load/store left/right let Predicates = [NotInMicroMips] in { def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>; def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>; -def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>; -def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>; +def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>; +def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>; } def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM; @@ -1013,10 +1019,10 @@ def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>; def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>; -def WAIT : MMRel, WAIT_FT<"wait">, WAIT_FM; +let Predicates = [NotInMicroMips] in { +def WAIT : WAIT_FT<"wait">, WAIT_FM; /// Load-linked, Store-conditional -let Predicates = [NotInMicroMips] in { def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>; def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>; } @@ -1038,7 +1044,10 @@ def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, def B : UncondBranch; def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; -def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; +let Predicates = [NotInMicroMips] in { +def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; +} +def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>; def JALRPseudo : JumpLinkRegPseudo; def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>; def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>; @@ -1143,7 +1152,7 @@ def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>; //===----------------------------------------------------------------------===// def : InstAlias<"move $dst, $src", (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>, - Requires<[NotMips64]>; + Requires<[NotMips64, NotInMicroMips]>; def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>; def : InstAlias<"addu $rs, $rt, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; @@ -1152,7 +1161,9 @@ def : InstAlias<"add $rs, $rt, $imm", def : InstAlias<"and $rs, $rt, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>; +let Predicates = [NotInMicroMips] in { def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; +} def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>; def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>; def : InstAlias<"not $rt, $rs",