X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FIA64%2FIA64ISelLowering.cpp;h=87c81bf427a2ba802872f2ad1952fcab4ecd657a;hb=475871a144eb604ddaf37503397ba0941442e5fb;hp=b9508a9cb35344f900f428a46de7d332218386b7;hpb=36397f50343639ce9a25996f2d790c656791ab92;p=oota-llvm.git diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index b9508a9cb35..87c81bf427a 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Duraid Madina and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" using namespace llvm; @@ -26,103 +26,109 @@ using namespace llvm; IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) : TargetLowering(TM) { - // register class for general registers - addRegisterClass(MVT::i64, IA64::GRRegisterClass); + // register class for general registers + addRegisterClass(MVT::i64, IA64::GRRegisterClass); - // register class for FP registers - addRegisterClass(MVT::f64, IA64::FPRegisterClass); + // register class for FP registers + addRegisterClass(MVT::f64, IA64::FPRegisterClass); - // register class for predicate registers - addRegisterClass(MVT::i1, IA64::PRRegisterClass); + // register class for predicate registers + addRegisterClass(MVT::i1, IA64::PRRegisterClass); - setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote); + setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand); + setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand); - setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand); - setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand); - setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote); + setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand); - setOperationAction(ISD::BRIND , MVT::Other, Expand); - setOperationAction(ISD::BR_JT , MVT::Other, Expand); - setOperationAction(ISD::BR_CC , MVT::Other, Expand); - setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); + setOperationAction(ISD::BRIND , MVT::Other, Expand); + setOperationAction(ISD::BR_JT , MVT::Other, Expand); + setOperationAction(ISD::BR_CC , MVT::Other, Expand); + setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); - // ia64 uses SELECT not SELECT_CC - setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); - - // We need to handle ISD::RET for void functions ourselves, - // so we get a chance to restore ar.pfs before adding a - // br.ret insn - setOperationAction(ISD::RET, MVT::Other, Custom); + // ia64 uses SELECT not SELECT_CC + setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); + + // We need to handle ISD::RET for void functions ourselves, + // so we get a chance to restore ar.pfs before adding a + // br.ret insn + setOperationAction(ISD::RET, MVT::Other, Custom); - setSetCCResultType(MVT::i1); - setShiftAmountType(MVT::i64); + setShiftAmountType(MVT::i64); - setOperationAction(ISD::FREM , MVT::f32 , Expand); - setOperationAction(ISD::FREM , MVT::f64 , Expand); + setOperationAction(ISD::FREM , MVT::f32 , Expand); + setOperationAction(ISD::FREM , MVT::f64 , Expand); - setOperationAction(ISD::UREM , MVT::f32 , Expand); - setOperationAction(ISD::UREM , MVT::f64 , Expand); + setOperationAction(ISD::UREM , MVT::f32 , Expand); + setOperationAction(ISD::UREM , MVT::f64 , Expand); - setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); - setOperationAction(ISD::MEMSET , MVT::Other, Expand); - setOperationAction(ISD::MEMCPY , MVT::Other, Expand); - - setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); - setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); - - // We don't support sin/cos/sqrt - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FSQRT, MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FSQRT, MVT::f32, Expand); - - // FIXME: IA64 supports fcopysign natively! - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); - - // We don't have line number support yet. - setOperationAction(ISD::LOCATION, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); - - //IA64 has these, but they are not implemented - setOperationAction(ISD::CTTZ , MVT::i64 , Expand); - setOperationAction(ISD::CTLZ , MVT::i64 , Expand); - setOperationAction(ISD::ROTL , MVT::i64 , Expand); - setOperationAction(ISD::ROTR , MVT::i64 , Expand); - setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev - - setOperationAction(ISD::ADJUST_TRAMP, MVT::i64, Expand); - - // VASTART needs to be custom lowered to use the VarArgsFrameIndex - setOperationAction(ISD::VAARG , MVT::Other, Custom); - setOperationAction(ISD::VASTART , MVT::Other, Custom); - - // Use the default implementation. - setOperationAction(ISD::VACOPY , MVT::Other, Expand); - setOperationAction(ISD::VAEND , MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); - // Thread Local Storage - setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); + setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); + setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); - setStackPointerRegisterToSaveRestore(IA64::r12); + // We don't support sin/cos/sqrt/pow + setOperationAction(ISD::FSIN , MVT::f64, Expand); + setOperationAction(ISD::FCOS , MVT::f64, Expand); + setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FSIN , MVT::f32, Expand); + setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FPOW , MVT::f32, Expand); - setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes.. - setJumpBufAlignment(16); // ...and must be 16-byte aligned - - computeRegisterProperties(); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); + + // FIXME: IA64 supports fcopysign natively! + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + + // We don't have line number support yet. + setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + + // IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer + // expansion for ctlz/cttz in terms of ctpop is much larger, but lower + // latency. + // FIXME: Custom lower CTLZ when compiling for size? + setOperationAction(ISD::CTLZ , MVT::i64 , Expand); + setOperationAction(ISD::CTTZ , MVT::i64 , Expand); + setOperationAction(ISD::ROTL , MVT::i64 , Expand); + setOperationAction(ISD::ROTR , MVT::i64 , Expand); + + // FIXME: IA64 has this, but is not implemented. should be mux @rev + setOperationAction(ISD::BSWAP, MVT::i64 , Expand); + + // VASTART needs to be custom lowered to use the VarArgsFrameIndex + setOperationAction(ISD::VAARG , MVT::Other, Custom); + setOperationAction(ISD::VASTART , MVT::Other, Custom); + + // Use the default implementation. + setOperationAction(ISD::VACOPY , MVT::Other, Expand); + setOperationAction(ISD::VAEND , MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + + // Thread Local Storage + setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); + + setStackPointerRegisterToSaveRestore(IA64::r12); + + setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes.. + setJumpBufAlignment(16); // ...and must be 16-byte aligned + + computeRegisterProperties(); - setOperationAction(ISD::ConstantFP, MVT::f64, Expand); - addLegalFPImmediate(+0.0); - addLegalFPImmediate(+1.0); + addLegalFPImmediate(APFloat(+0.0)); + addLegalFPImmediate(APFloat(-0.0)); + addLegalFPImmediate(APFloat(+1.0)); + addLegalFPImmediate(APFloat(-1.0)); } const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const { @@ -134,10 +140,12 @@ const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const { } } +MVT IA64TargetLowering::getSetCCResultType(const SDValue &) const { + return MVT::i1; +} -std::vector -IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { - std::vector ArgValues; +void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, + SmallVectorImpl &ArgValues) { // // add beautiful description of IA64 stack frame format // here (from intel 24535803.pdf most likely) @@ -146,9 +154,9 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { MachineFrameInfo *MFI = MF.getFrameInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); MachineBasicBlock& BB = MF.front(); @@ -169,10 +177,10 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - SDOperand newroot, argt; + SDValue newroot, argt; if(count < 8) { // need to fix this logic? maybe. - switch (getValueType(I->getType())) { + switch (getValueType(I->getType()).getSimpleVT()) { default: assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n"); case MVT::f32: @@ -180,17 +188,19 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // see intel ABI docs) case MVT::f64: //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]); - MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn + MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]); + // mark this reg as liveIn // floating point args go into f8..f15 as-needed, the increment argVreg[count] = // is below..: - MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64)); + MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64)); // FP args go into f8..f15 as needed: (hence the ++) argPreg[count] = args_FP[used_FPArgs++]; argOpc[count] = IA64::FMOV; argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::f64); if (I->getType() == Type::FloatTy) - argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt); + argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt, + DAG.getIntPtrConstant(0)); break; case MVT::i1: // NOTE: as far as C abi stuff goes, // bools are just boring old ints @@ -199,9 +209,10 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i32: case MVT::i64: //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]); - MF.addLiveIn(args_int[count]); // mark this register as liveIn + MF.getRegInfo().addLiveIn(args_int[count]); + // mark this register as liveIn argVreg[count] = - MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); argPreg[count] = args_int[count]; argOpc[count] = IA64::MOV; argt = newroot = @@ -218,7 +229,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Create the SelectionDAG nodes corresponding to a load //from this parameter - SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64); + SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); argt = newroot = DAG.getLoad(getValueType(I->getType()), DAG.getEntryNode(), FIN, NULL, 0); } @@ -230,7 +241,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Create a vreg to hold the output of (what will become) // the "alloc" instruction - VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now /* @@ -274,7 +285,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Finally, inform the code generator which regs we return values in. // (see the ISD::RET: case in the instruction selector) - switch (getValueType(F.getReturnType())) { + switch (getValueType(F.getReturnType()).getSimpleVT()) { default: assert(0 && "i have no idea where to return this type!"); case MVT::isVoid: break; case MVT::i1: @@ -282,22 +293,20 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i16: case MVT::i32: case MVT::i64: - MF.addLiveOut(IA64::r8); + MF.getRegInfo().addLiveOut(IA64::r8); break; case MVT::f32: case MVT::f64: - MF.addLiveOut(IA64::F8); + MF.getRegInfo().addLiveOut(IA64::F8); break; } - - return ArgValues; } -std::pair -IA64TargetLowering::LowerCallTo(SDOperand Chain, - const Type *RetTy, bool RetTyIsSigned, +std::pair +IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, + bool RetSExt, bool RetZExt, bool isVarArg, unsigned CallingConv, - bool isTailCall, SDOperand Callee, + bool isTailCall, SDValue Callee, ArgListTy &Args, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); @@ -326,19 +335,19 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy())); - SDOperand StackPtr; - std::vector Stores; - std::vector Converts; - std::vector RegValuesToPass; + SDValue StackPtr; + std::vector Stores; + std::vector Converts; + std::vector RegValuesToPass; unsigned ArgOffset = 16; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - SDOperand Val = Args[i].Node; - MVT::ValueType ObjectVT = Val.getValueType(); - SDOperand ValToStore(0, 0), ValToConvert(0, 0); + SDValue Val = Args[i].Node; + MVT ObjectVT = Val.getValueType(); + SDValue ValToStore(0, 0), ValToConvert(0, 0); unsigned ObjSize=8; - switch (ObjectVT) { + switch (ObjectVT.getSimpleVT()) { default: assert(0 && "unexpected argument type!"); case MVT::i1: case MVT::i8: @@ -382,7 +391,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, if(!StackPtr.Val) { StackPtr = DAG.getRegister(IA64::r12, MVT::i64); } - SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); + SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff); Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); ArgOffset += ObjSize; @@ -407,16 +416,16 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, IA64::F12, IA64::F13, IA64::F14, IA64::F15 }; - SDOperand InFlag; + SDValue InFlag; // save the current GP, SP and RP : FIXME: do we need to do all 3 always? - SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); + SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag); Chain = GPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); + SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag); Chain = SPBeforeCall.getValue(1); InFlag = Chain.getValue(2); - SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); + SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag); Chain = RPBeforeCall.getValue(1); InFlag = Chain.getValue(2); @@ -430,7 +439,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, // flagged for now, but shouldn't have to be (TODO) unsigned seenConverts = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { - if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) { + if(RegValuesToPass[i].getValueType().isFloatingPoint()) { Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag); InFlag = Chain.getValue(1); @@ -441,7 +450,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, unsigned usedFPArgs = 0; for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, - MVT::isInteger(RegValuesToPass[i].getValueType()) ? + RegValuesToPass[i].getValueType().isInteger() ? IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag); InFlag = Chain.getValue(1); } @@ -454,8 +463,8 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, } */ - std::vector NodeTys; - std::vector CallOperands; + std::vector NodeTys; + std::vector CallOperands; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. CallOperands.push_back(Chain); @@ -480,22 +489,22 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag); InFlag = Chain.getValue(1); - std::vector RetVals; + std::vector RetVals; RetVals.push_back(MVT::Other); RetVals.push_back(MVT::Flag); - MVT::ValueType RetTyVT = getValueType(RetTy); - SDOperand RetVal; + MVT RetTyVT = getValueType(RetTy); + SDValue RetVal; if (RetTyVT != MVT::isVoid) { - switch (RetTyVT) { + switch (RetTyVT.getSimpleVT()) { default: assert(0 && "Unknown value type to return!"); case MVT::i1: { // bools are just like other integers (returned in r8) // we *could* fall through to the truncate below, but this saves a // few redundant predicate ops - SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag); + SDValue boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag); InFlag = boolInR8.getValue(2); Chain = boolInR8.getValue(1); - SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); + SDValue zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag); InFlag = zeroReg.getValue(2); Chain = zeroReg.getValue(1); @@ -523,7 +532,8 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, case MVT::f32: RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); Chain = RetVal.getValue(1); - RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal); + RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal, + DAG.getIntPtrConstant(0)); break; case MVT::f64: RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag); @@ -533,20 +543,21 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, } } - Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, - DAG.getConstant(NumBytes, getPointerTy())); - + Chain = DAG.getCALLSEQ_END(Chain, + DAG.getConstant(NumBytes, getPointerTy()), + DAG.getConstant(0, getPointerTy()), + SDValue()); return std::make_pair(RetVal, Chain); } -SDOperand IA64TargetLowering:: -LowerOperation(SDOperand Op, SelectionDAG &DAG) { +SDValue IA64TargetLowering:: +LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { default: assert(0 && "Should not custom lower this!"); case ISD::GlobalTLSAddress: assert(0 && "TLS not implemented for IA64."); case ISD::RET: { - SDOperand AR_PFSVal, Copy; + SDValue AR_PFSVal, Copy; switch(Op.getNumOperands()) { default: @@ -559,46 +570,45 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal); case 3: { // Copy the result into the output register & restore ar.pfs - MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); - unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8; + MVT ArgVT = Op.getOperand(1).getValueType(); + unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8; AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64); Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1), - SDOperand()); + SDValue()); AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal, Copy.getValue(1)); return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal, AR_PFSVal.getValue(1)); } } - return SDOperand(); + return SDValue(); } case ISD::VAARG: { - MVT::ValueType VT = getPointerTy(); - SrcValueSDNode *SV = cast(Op.getOperand(2)); - SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), - SV->getValue(), SV->getOffset()); + MVT VT = getPointerTy(); + const Value *SV = cast(Op.getOperand(2))->getValue(); + SDValue VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1), + SV, 0); // Increment the pointer, VAList, to the next vaarg - SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList, - DAG.getConstant(MVT::getSizeInBits(VT)/8, + SDValue VAIncr = DAG.getNode(ISD::ADD, VT, VAList, + DAG.getConstant(VT.getSizeInBits()/8, VT)); // Store the incremented VAList to the legalized pointer VAIncr = DAG.getStore(VAList.getValue(1), VAIncr, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + Op.getOperand(1), SV, 0); // Load the actual argument out of the pointer VAList return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0); } case ISD::VASTART: { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); - SrcValueSDNode *SV = cast(Op.getOperand(2)); - return DAG.getStore(Op.getOperand(0), FR, - Op.getOperand(1), SV->getValue(), SV->getOffset()); + SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64); + const Value *SV = cast(Op.getOperand(2))->getValue(); + return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); } // Frame & Return address. Currently unimplemented case ISD::RETURNADDR: break; case ISD::FRAMEADDR: break; } - return SDOperand(); + return SDValue(); }