X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FHexagon%2FHexagonTargetMachine.cpp;h=64f75a3e2f5c57ab0e99dfdc7546ad463c75a784;hb=417c5c172ce0d56105112481b1bcf0bc2fc011c2;hp=6c418854a484c3a38a75b833b45984edc9e204a3;hpb=ab7955b9ce3197215406bc9fc97b22074127d035;p=oota-llvm.git diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 6c418854a48..64f75a3e2f5 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -1,4 +1,4 @@ -//===- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon --------===// +//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===// // // The LLVM Compiler Infrastructure // @@ -7,26 +7,36 @@ // //===----------------------------------------------------------------------===// // +// Implements the info about Hexagon target spec. // //===----------------------------------------------------------------------===// #include "HexagonTargetMachine.h" #include "Hexagon.h" #include "HexagonISelLowering.h" -#include "llvm/Module.h" +#include "HexagonMachineScheduler.h" +#include "HexagonTargetObjectFile.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/PassManager.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" -#include "llvm/Transforms/Scalar.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/IR/Module.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/TargetRegistry.h" +#include "llvm/Transforms/IPO/PassManagerBuilder.h" +#include "llvm/Transforms/Scalar.h" using namespace llvm; -static cl:: -opt DisableHardwareLoops( - "disable-hexagon-hwloops", cl::Hidden, - cl::desc("Disable Hardware Loops for Hexagon target")); +static cl:: opt DisableHardwareLoops("disable-hexagon-hwloops", + cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); + +static cl::opt DisableHexagonMISched("disable-hexagon-misched", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Hexagon MI Scheduling")); + +static cl::opt DisableHexagonCFGOpt("disable-hexagon-cfgopt", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Hexagon CFG Optimization")); + /// HexagonTargetMachineModule - Note that this is used on hosts that /// cannot link in a library unless there are references into the @@ -41,6 +51,13 @@ extern "C" void LLVMInitializeHexagonTarget() { RegisterTargetMachine X(TheHexagonTarget); } +static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { + return new VLIWMachineScheduler(C, make_unique()); +} + +static MachineSchedRegistry +SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", + createVLIWMachineSched); /// HexagonTargetMachine ctor - Create an ILP32 architecture model. /// @@ -49,48 +66,47 @@ extern "C" void LLVMInitializeHexagonTarget() { /// HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - TargetOptions Options, - Reloc::Model RM, - CodeModel::Model CM, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") , - Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), - TSInfo(*this), - FrameLowering(Subtarget), - InstrItins(&Subtarget.getInstrItineraryData()) { - setMCUseCFI(false); + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique()), + DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"), Subtarget(TT, CPU, FS, *this) { + initAsmInfo(); } -// addPassesForOptimizations - Allow the backend (target) to add Target -// Independent Optimization passes to the Pass Manager. -bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) { - - PM.add(createConstantPropagationPass()); - PM.add(createLoopSimplifyPass()); - PM.add(createDeadCodeEliminationPass()); - PM.add(createConstantPropagationPass()); - PM.add(createLoopUnrollPass()); - PM.add(createLoopStrengthReducePass(getTargetLowering())); - return true; -} +HexagonTargetMachine::~HexagonTargetMachine() {} namespace { /// Hexagon Code Generator Pass Configuration Options. class HexagonPassConfig : public TargetPassConfig { public: HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) { + // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define + // HexagonSubtarget::enableMachineScheduler() { return true; }. + // That will bypass the SelectionDAG VLIW scheduler, which is probably just + // hurting compile time and will be removed eventually anyway. + if (DisableHexagonMISched) + disablePass(&MachineSchedulerID); + else + enablePass(&MachineSchedulerID); + } HexagonTargetMachine &getHexagonTargetMachine() const { return getTM(); } - virtual bool addInstSelector(); - virtual bool addPreRegAlloc(); - virtual bool addPostRegAlloc(); - virtual bool addPreSched2(); - virtual bool addPreEmitPass(); + ScheduleDAGInstrs * + createMachineScheduler(MachineSchedContext *C) const override { + return createVLIWMachineSched(C); + } + + bool addInstSelector() override; + void addPreRegAlloc() override; + void addPostRegAlloc() override; + void addPreSched2() override; + void addPreEmitPass() override; }; } // namespace @@ -99,43 +115,57 @@ TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { } bool HexagonPassConfig::addInstSelector() { - PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine())); - PM.add(createHexagonISelDag(getHexagonTargetMachine())); - PM.add(createHexagonPeephole()); - return false; -} + HexagonTargetMachine &TM = getHexagonTargetMachine(); + bool NoOpt = (getOptLevel() == CodeGenOpt::None); + if (!NoOpt) + addPass(createHexagonRemoveExtendArgs(TM)); -bool HexagonPassConfig::addPreRegAlloc() { - if (!DisableHardwareLoops) { - PM.add(createHexagonHardwareLoops()); + addPass(createHexagonISelDag(TM, getOptLevel())); + + if (!NoOpt) { + addPass(createHexagonPeephole()); + printAndVerify("After hexagon peephole pass"); } return false; } -bool HexagonPassConfig::addPostRegAlloc() { - PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine())); - return true; +void HexagonPassConfig::addPreRegAlloc() { + if (getOptLevel() != CodeGenOpt::None) + if (!DisableHardwareLoops) + addPass(createHexagonHardwareLoops(), false); } +void HexagonPassConfig::addPostRegAlloc() { + if (getOptLevel() != CodeGenOpt::None) + if (!DisableHexagonCFGOpt) + addPass(createHexagonCFGOptimizer(), false); +} -bool HexagonPassConfig::addPreSched2() { - addPass(IfConverterID); - return true; +void HexagonPassConfig::addPreSched2() { + addPass(createHexagonCopyToCombine(), false); + if (getOptLevel() != CodeGenOpt::None) + addPass(&IfConverterID, false); + addPass(createHexagonSplitConst32AndConst64()); } -bool HexagonPassConfig::addPreEmitPass() { +void HexagonPassConfig::addPreEmitPass() { + bool NoOpt = (getOptLevel() == CodeGenOpt::None); - if (!DisableHardwareLoops) { - PM.add(createHexagonFixupHwLoops()); - } + if (!NoOpt) + addPass(createHexagonNewValueJump(), false); // Expand Spill code for predicate registers. - PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine())); + addPass(createHexagonExpandPredSpillCode(), false); // Split up TFRcondsets into conditional transfers. - PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine())); + addPass(createHexagonSplitTFRCondSets(), false); - return false; + // Create Packets. + if (!NoOpt) { + if (!DisableHardwareLoops) + addPass(createHexagonFixupHwLoops(), false); + addPass(createHexagonPacketizer(), false); + } }