X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FHexagon%2FHexagonRegisterInfo.td;h=81629dc6d47ff2b6c264b7eb1782e87f51eea567;hb=4704a2c28432abe0efaeee88f1b61e36a796163e;hp=fe41fc3bc60cd5afb16ee450e2885b62f0675b8a;hpb=7517bbc91ae1c60d3c7df8b11642c7a5bb3d5a71;p=oota-llvm.git diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index fe41fc3bc60..81629dc6d47 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -13,90 +13,84 @@ let Namespace = "Hexagon" in { - class HexagonReg : Register { + class HexagonReg num, string n, list alt = [], + list alias = []> : Register { field bits<5> Num; + let Aliases = alias; + let HWEncoding{4-0} = num; } - class HexagonDoubleReg subregs> : + class HexagonDoubleReg num, string n, list subregs, + list alt = []> : RegisterWithSubRegs { field bits<5> Num; + + let AltNames = alt; + let HWEncoding{4-0} = num; } // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers. - class Ri num, string n> : HexagonReg { + class Ri num, string n, list alt = []> : HexagonReg { let Num = num; } // Rf - 32-bit floating-point registers. - class Rf num, string n> : HexagonReg { + class Rf num, string n> : HexagonReg { let Num = num; } // Rd - 64-bit registers. class Rd num, string n, list subregs> : - HexagonDoubleReg { + HexagonDoubleReg { let Num = num; let SubRegs = subregs; } // Rp - predicate registers - class Rp num, string n> : HexagonReg { + class Rp num, string n> : HexagonReg { let Num = num; } + + // Rq - vector predicate registers + class Rq num, string n> : Register { + let HWEncoding{2-0} = num; + } + // Rc - control registers - class Rc num, string n> : HexagonReg { + class Rc num, string n, + list alt = [], list alias = []> : + HexagonReg { let Num = num; } - // Rj - aliased integer registers - class Rj: HexagonReg { - let Num = R.Num; - let Aliases = [R]; + // Rcc - 64-bit control registers. + class Rcc num, string n, list subregs, + list alt = []> : + HexagonDoubleReg { + let Num = num; + let SubRegs = subregs; + } + + // Mx - address modifier registers + class Mx num, string n> : HexagonReg<{0b0000, num}, n> { + let Num = !cast>(num); } - def subreg_loreg : SubRegIndex; - def subreg_hireg : SubRegIndex; + def subreg_loreg : SubRegIndex<32>; + def subreg_hireg : SubRegIndex<32, 32>; + def subreg_overflow : SubRegIndex<1, 0>; // Integer registers. - def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; - def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; - def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; - def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; - def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; - def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; - def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>; - def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>; - def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>; - def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>; - def R10 : Ri<10, "r10">, DwarfRegNum<[10]>; - def R11 : Ri<11, "r11">, DwarfRegNum<[11]>; - def R12 : Ri<12, "r12">, DwarfRegNum<[12]>; - def R13 : Ri<13, "r13">, DwarfRegNum<[13]>; - def R14 : Ri<14, "r14">, DwarfRegNum<[14]>; - def R15 : Ri<15, "r15">, DwarfRegNum<[15]>; - def R16 : Ri<16, "r16">, DwarfRegNum<[16]>; - def R17 : Ri<17, "r17">, DwarfRegNum<[17]>; - def R18 : Ri<18, "r18">, DwarfRegNum<[18]>; - def R19 : Ri<19, "r19">, DwarfRegNum<[19]>; - def R20 : Ri<20, "r20">, DwarfRegNum<[20]>; - def R21 : Ri<21, "r21">, DwarfRegNum<[21]>; - def R22 : Ri<22, "r22">, DwarfRegNum<[22]>; - def R23 : Ri<23, "r23">, DwarfRegNum<[23]>; - def R24 : Ri<24, "r24">, DwarfRegNum<[24]>; - def R25 : Ri<25, "r25">, DwarfRegNum<[25]>; - def R26 : Ri<26, "r26">, DwarfRegNum<[26]>; - def R27 : Ri<27, "r27">, DwarfRegNum<[27]>; - def R28 : Ri<28, "r28">, DwarfRegNum<[28]>; - def R29 : Ri<29, "r29">, DwarfRegNum<[29]>; - def R30 : Ri<30, "r30">, DwarfRegNum<[30]>; - def R31 : Ri<31, "r31">, DwarfRegNum<[31]>; - - def SP : Rj<"sp", R29>, DwarfRegNum<[29]>; - def FP : Rj<"fp", R30>, DwarfRegNum<[30]>; - def LR : Rj<"lr", R31>, DwarfRegNum<[31]>; + foreach i = 0-28 in { + def R#i : Ri, DwarfRegNum<[i]>; + } + + def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; + def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; + def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; // Aliases of the R* registers used to hold 64-bit int values (doubles). let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { @@ -124,44 +118,153 @@ let Namespace = "Hexagon" in { def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; - // Control registers. - def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>; - def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>; + // Modifier registers. + // C6 and C7 can also be M0 and M1, but register names must be unique, even + // if belonging to different register classes. + def M0 : Mx<0, "m0">, DwarfRegNum<[72]>; + def M1 : Mx<1, "m1">, DwarfRegNum<[73]>; - def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>; - def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>; + // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc- + // tions modify this bit, and multiple such instructions are allowed in the + // same packet. We need to ignore output dependencies on this bit, but not + // on the entire USR. + def USR_OVF : Rc; - def M0 : Rc<6, "m0">, DwarfRegNum<[71]>; - def M1 : Rc<7, "m1">, DwarfRegNum<[72]>; + // Control registers. + def SA0 : Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; + def LC0 : Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; + def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; + def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; + def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, + DwarfRegNum<[71]>; + def C5 : Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; // future use + def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>; + def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[74]>; - def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct? - def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct? + def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { + let SubRegIndices = [subreg_overflow]; + let SubRegs = [USR_OVF]; + } + def PC : Rc<9, "pc">, DwarfRegNum<[76]>; + def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; + def GP : Rc<11, "gp">, DwarfRegNum<[78]>; + def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; + def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; + def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; + def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; } + // Control registers pairs. + let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { + def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; + def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; + def C7_6 : Rcc<6, "c7:6", [C6, C7], ["m1:0"]>, DwarfRegNum<[72]>; + def C9_8 : Rcc<8, "c9:8", [USR, PC]>, DwarfRegNum<[74]>; + def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; + def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; + def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>; + } + + foreach i = 0-31 in { + def V#i : Ri, DwarfRegNum<[!add(i, 99)]>; + } + + // Aliases of the V* registers used to hold double vec values. + let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { + def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>; + def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>; + def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>; + def W3 : Rd< 6, "v7:6", [V6, V7]>, DwarfRegNum<[105]>; + def W4 : Rd< 8, "v9:8", [V8, V9]>, DwarfRegNum<[107]>; + def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>; + def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>; + def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>; + def W8 : Rd<16, "v17:16", [V16, V17]>, DwarfRegNum<[115]>; + def W9 : Rd<18, "v19:18", [V18, V19]>, DwarfRegNum<[117]>; + def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>; + def W11 : Rd<22, "v23:22", [V22, V23]>, DwarfRegNum<[121]>; + def W12 : Rd<24, "v25:24", [V24, V25]>, DwarfRegNum<[123]>; + def W13 : Rd<26, "v27:26", [V26, V27]>, DwarfRegNum<[125]>; + def W14 : Rd<28, "v29:28", [V28, V29]>, DwarfRegNum<[127]>; + def W15 : Rd<30, "v31:30", [V30, V31]>, DwarfRegNum<[129]>; + } + + // Vector Predicate registers. + def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>; + def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; + def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; + def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; + // Register classes. // // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32, +def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), R10, R11, R29, R30, R31)> { } -def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64, +// Registers are listed in reverse order for allocation preference reasons. +def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, + (add R7, R6, R5, R4, R3, R2, R1, R0)> ; + +def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; +def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512, + (add (sequence "V%u", 0, 31))>; + +def VecDblRegs : RegisterClass<"Hexagon", + [v128i8, v64i16, v32i32, v16i64], 1024, + (add (sequence "W%u", 0, 15))>; + +def VectorRegs128B : RegisterClass<"Hexagon", + [v128i8, v64i16, v32i32, v16i64], 1024, + (add (sequence "V%u", 0, 31))>; -def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))> +def VecDblRegs128B : RegisterClass<"Hexagon", + [v256i8,v128i16,v64i32,v32i64], 2048, + (add (sequence "W%u", 0, 15))>; + +def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512, + (add (sequence "Q%u", 0, 3))>; + +def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024, + (add (sequence "Q%u", 0, 3))>; + +def PredRegs : RegisterClass<"Hexagon", + [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, + (add (sequence "P%u", 0, 3))> { let Size = 32; } -def CRRegs : RegisterClass<"Hexagon", [i32], 32, - (add (sequence "LC%u", 0, 1), - (sequence "SA%u", 0, 1), - (sequence "M%u", 0, 1), PC, GP)> { - let Size = 32; +let Size = 32 in +def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; + +let Size = 32, isAllocatable = 0 in +def CtrRegs : RegisterClass<"Hexagon", [i32], 32, + (add LC0, SA0, LC1, SA1, + P3_0, + M0, M1, C6, C7, CS0, CS1, UPCL, UPCH, + USR, USR_OVF, UGP, GP, PC)>; + +let Size = 64, isAllocatable = 0 in +def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, + (add C1_0, C3_2, C7_6, C9_8, C11_10, CS, UPC)>; + +def VolatileV3 { + list Regs = [D0, D1, D2, D3, D4, D5, D6, D7, + R28, R31, + P0, P1, P2, P3, + M0, M1, + LC0, LC1, SA0, SA1, USR, USR_OVF]; } + +def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), +[{ + return isPositiveHalfWord(N); +}]>;