X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FHexagon%2FHexagonInstrInfoV4.td;h=d39f7d7e6c7ad75faa001031e7269cc06ea20321;hb=545127f54dc632b2d0da38e027c58888d091ede1;hp=475c23d98bf7d85105ef0fa41b73c4427b66cf76;hpb=f3ad5745681ece7af3027fd2f82fadb0247242e8;p=oota-llvm.git diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 475c23d98bf..d39f7d7e6c7 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1004,21 +1004,22 @@ defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel; let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in class NVJrr_template majOp, bit NvOpNum, - bit isNegCond, bit isTaken> + bit isNegCond, bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic# "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")# "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { bits<5> src1; bits<5> src2; bits<3> Ns; // New-Value Operand - bits<5> RegOp; // Non New-Value Operand + bits<5> RegOp; // Non-New-Value Operand bits<11> offset; + let isTaken = isTak; let isBrTaken = !if(isTaken, "true", "false"); let isPredicatedFalse = isNegCond; @@ -1030,7 +1031,7 @@ class NVJrr_template majOp, bit NvOpNum, let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = Ns; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{12-8} = RegOp; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; @@ -1078,13 +1079,14 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in class NVJri_template majOp, bit isNegCond, - bit isTaken> + bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { + let isTaken = isTak; let isPredicatedFalse = isNegCond; let isBrTaken = !if(isTaken, "true", "false"); @@ -1097,7 +1099,7 @@ class NVJri_template majOp, bit isNegCond, let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = src1; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{12-8} = src2; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; @@ -1135,14 +1137,15 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in class NVJ_ConstImm_template majOp, string ImmVal, - bit isNegCond, bit isTaken> + bit isNegCond, bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic #"($src1.new, #"#ImmVal#")) jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { + let isTaken = isTak; let isPredicatedFalse = isNegCond; let isBrTaken = !if(isTaken, "true", "false"); @@ -1153,7 +1156,7 @@ class NVJ_ConstImm_template majOp, string ImmVal, let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = src1; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; } @@ -2019,9 +2022,10 @@ multiclass MemOpi_bitPats ; + def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)), + immPred:$bitend), + (addrPred (i32 IntRegs:$addr), extPred:$offset)), + (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>; } multiclass MemOpi_bitExtType { @@ -2065,9 +2069,10 @@ multiclass MemOpr_Pats { let AddedComplexity = 141 in // mem[bhw](Rs+#0) [+-&|]= Rt - def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)), - addrPred:$addr), - (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>; + def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)), + (i32 IntRegs:$addend)), + (addrPred (i32 IntRegs:$addr), extPred:$offset)), + (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>; // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt let AddedComplexity = 150 in @@ -2125,6 +2130,42 @@ let Predicates = [HasV4T, UseMEMOP] in { // incorrect code for negative numbers. // Pd=cmpb.eq(Rs,#u8) +let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0, + validSubTargets = HasV4SubT in +class CMP_NOT_REG_IMM op, Operand ImmOp, + list Pattern> + : ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2), + "$dst = !cmp."#OpName#"($src1, #$src2)", + Pattern, + "", ALU32_2op_tc_2early_SLOT0123> { + bits<2> dst; + bits<5> src1; + bits<10> src2; + + let IClass = 0b0111; + let Inst{27-24} = 0b0101; + let Inst{23-22} = op; + let Inst{20-16} = src1; + let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9}); + let Inst{13-5} = src2{8-0}; + let Inst{4-2} = 0b100; + let Inst{1-0} = dst; +} + +let opExtentBits = 10, isExtentSigned = 1 in { +def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst), + (setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>; + +def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst), + (not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>; + +} +let opExtentBits = 9 in +def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst), + (not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>; + + + // p=!cmp.eq(r1,r2) let isCompare = 1, validSubTargets = HasV4SubT in def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst), @@ -2134,15 +2175,6 @@ def CMPnotEQ_rr : ALU32_rr<(outs PredRegs:$dst), (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2)))]>, Requires<[HasV4T]>; -// p=!cmp.eq(r1,#s10) -let isCompare = 1, validSubTargets = HasV4SubT in -def CMPnotEQ_ri : ALU32_ri<(outs PredRegs:$dst), - (ins IntRegs:$src1, s10Ext:$src2), - "$dst = !cmp.eq($src1, #$src2)", - [(set (i1 PredRegs:$dst), - (setne (i32 IntRegs:$src1), s10ImmPred:$src2))]>, - Requires<[HasV4T]>; - // p=!cmp.gt(r1,r2) let isCompare = 1, validSubTargets = HasV4SubT in def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst), @@ -2152,14 +2184,6 @@ def CMPnotGT_rr : ALU32_rr<(outs PredRegs:$dst), (not (setgt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>, Requires<[HasV4T]>; -// p=!cmp.gt(r1,#s10) -let isCompare = 1, validSubTargets = HasV4SubT in -def CMPnotGT_ri : ALU32_ri<(outs PredRegs:$dst), - (ins IntRegs:$src1, s10Ext:$src2), - "$dst = !cmp.gt($src1, #$src2)", - [(set (i1 PredRegs:$dst), - (not (setgt (i32 IntRegs:$src1), s10ImmPred:$src2)))]>, - Requires<[HasV4T]>; // p=!cmp.gtu(r1,r2) let isCompare = 1, validSubTargets = HasV4SubT in @@ -2170,15 +2194,6 @@ def CMPnotGTU_rr : ALU32_rr<(outs PredRegs:$dst), (not (setugt (i32 IntRegs:$src1), (i32 IntRegs:$src2))))]>, Requires<[HasV4T]>; -// p=!cmp.gtu(r1,#u9) -let isCompare = 1, validSubTargets = HasV4SubT in -def CMPnotGTU_ri : ALU32_ri<(outs PredRegs:$dst), - (ins IntRegs:$src1, u9Ext:$src2), - "$dst = !cmp.gtu($src1, #$src2)", - [(set (i1 PredRegs:$dst), - (not (setugt (i32 IntRegs:$src1), u9ImmPred:$src2)))]>, - Requires<[HasV4T]>; - let isCompare = 1, validSubTargets = HasV4SubT in def CMPbEQri_V4 : MInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2), @@ -3198,7 +3213,7 @@ def : Pat<(i64 (cttz (i64 DoubleRegs:$src1))), // i8 -> i64 loads -// We need a complexity of 120 here to overide preceeding handling of +// We need a complexity of 120 here to override preceding handling of // zextloadi8. let Predicates = [HasV4T], AddedComplexity = 120 in { def: Pat <(i64 (extloadi8 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), @@ -3220,7 +3235,7 @@ def: Pat <(i64 (sextloadi8 FoldGlobalAddr:$addr)), (i64 (SXTW (LDrib_abs_V4 FoldGlobalAddr:$addr)))>; } // i16 -> i64 loads -// We need a complexity of 120 here to overide preceeding handling of +// We need a complexity of 120 here to override preceding handling of // zextloadi16. let AddedComplexity = 120 in { def: Pat <(i64 (extloadi16 (NumUsesBelowThresCONST32 tglobaladdr:$addr))), @@ -3248,7 +3263,7 @@ def: Pat <(i64 (sextloadi16 FoldGlobalAddr:$addr)), Requires<[HasV4T]>; } // i32->i64 loads -// We need a complexity of 120 here to overide preceeding handling of +// We need a complexity of 120 here to override preceding handling of // zextloadi32. let AddedComplexity = 120 in { def: Pat <(i64 (extloadi32 (NumUsesBelowThresCONST32 tglobaladdr:$addr))),