X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FHexagon%2FHexagonInstrInfo.h;h=d0b8a4631c1d6ce27d37cc09db4049a19072dc5e;hb=cd52a7a381a73c53ec4ef517ad87f19808cb1a28;hp=a9cd98cb39fbd1784eb4c20f16cafb2d358df63e;hpb=b33857040f63a9fdfb0c2a2ca2af67ec12cf9d02;p=oota-llvm.git diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index a9cd98cb39f..d0b8a4631c1 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -1,3 +1,4 @@ + //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// // // The LLVM Compiler Infrastructure @@ -11,139 +12,158 @@ // //===----------------------------------------------------------------------===// -#ifndef HexagonINSTRUCTIONINFO_H -#define HexagonINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H #include "HexagonRegisterInfo.h" #include "MCTargetDesc/HexagonBaseInfo.h" -#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/CodeGen/MachineBranchProbabilityInfo.h" #include "llvm/Target/TargetFrameLowering.h" - +#include "llvm/Target/TargetInstrInfo.h" #define GET_INSTRINFO_HEADER #include "HexagonGenInstrInfo.inc" namespace llvm { +struct EVT; +class HexagonSubtarget; class HexagonInstrInfo : public HexagonGenInstrInfo { + virtual void anchor(); const HexagonRegisterInfo RI; - const HexagonSubtarget& Subtarget; + const HexagonSubtarget &Subtarget; + public: + typedef unsigned Opcode_t; + explicit HexagonInstrInfo(HexagonSubtarget &ST); /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } + const HexagonRegisterInfo &getRegisterInfo() const { return RI; } /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, - int &FrameIndex) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(const MachineInstr *MI, - int &FrameIndex) const; - - - virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, - bool AllowModify) const; - - virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; - - virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond, - DebugLoc DL) const; - - virtual void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const; - - virtual void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const; - - virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const; - - virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const; - - virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const; - - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl &Ops, - int FrameIndex) const; - - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl &Ops, - MachineInstr* LoadMI) const { - return 0; + unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; + + + bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const override; + + unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + + unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, ArrayRef Cond, + DebugLoc DL) const override; + + bool analyzeCompare(const MachineInstr *MI, + unsigned &SrcReg, unsigned &SrcReg2, + int &Mask, int &Value) const override; + + void copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const override; + + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + + void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + + void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const; + + /// expandPostRAPseudo - This function is called for all pseudo instructions + /// that remain after register allocation. Many pseudo instructions are + /// created to help register allocation. This is the place to convert them + /// into real instructions. The target can edit MI in place, or it can insert + /// new instructions and erase MI. The function should return true if + /// anything was changed. + bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; + + MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, + ArrayRef Ops, + MachineBasicBlock::iterator InsertPt, + int FrameIndex) const override; + + MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, + ArrayRef Ops, + MachineBasicBlock::iterator InsertPt, + MachineInstr *LoadMI) const override { + return nullptr; } unsigned createVR(MachineFunction* MF, MVT VT) const; - virtual bool isPredicable(MachineInstr *MI) const; - virtual bool - PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl &Cond) const; - - virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, - unsigned ExtraPredCycles, - const BranchProbability &Probability) const; - - virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, - unsigned NumTCycles, unsigned ExtraTCycles, - MachineBasicBlock &FMBB, - unsigned NumFCycles, unsigned ExtraFCycles, - const BranchProbability &Probability) const; - - virtual bool isPredicated(const MachineInstr *MI) const; - virtual bool DefinesPredicate(MachineInstr *MI, - std::vector &Pred) const; - virtual bool - SubsumesPredicate(const SmallVectorImpl &Pred1, - const SmallVectorImpl &Pred2) const; - - virtual bool - ReverseBranchCondition(SmallVectorImpl &Cond) const; - - virtual bool - isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, - const BranchProbability &Probability) const; - - virtual DFAPacketizer* - CreateTargetScheduleState(const TargetMachine *TM, - const ScheduleDAG *DAG) const; - - virtual bool isSchedulingBoundary(const MachineInstr *MI, - const MachineBasicBlock *MBB, - const MachineFunction &MF) const; - bool isValidOffset(const int Opcode, const int Offset) const; + bool isBranch(const MachineInstr *MI) const; + bool isPredicable(MachineInstr *MI) const override; + bool PredicateInstruction(MachineInstr *MI, + ArrayRef Cond) const override; + + bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, + unsigned ExtraPredCycles, + const BranchProbability &Probability) const override; + + bool isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned NumTCycles, unsigned ExtraTCycles, + MachineBasicBlock &FMBB, + unsigned NumFCycles, unsigned ExtraFCycles, + const BranchProbability &Probability) const override; + + bool isPredicated(const MachineInstr *MI) const override; + bool isPredicated(unsigned Opcode) const; + bool isPredicatedTrue(const MachineInstr *MI) const; + bool isPredicatedTrue(unsigned Opcode) const; + bool isPredicatedNew(const MachineInstr *MI) const; + bool isPredicatedNew(unsigned Opcode) const; + bool DefinesPredicate(MachineInstr *MI, + std::vector &Pred) const override; + bool SubsumesPredicate(ArrayRef Pred1, + ArrayRef Pred2) const override; + + bool + ReverseBranchCondition(SmallVectorImpl &Cond) const override; + + bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, + const BranchProbability &Probability) const override; + + DFAPacketizer * + CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override; + + bool isSchedulingBoundary(const MachineInstr *MI, + const MachineBasicBlock *MBB, + const MachineFunction &MF) const override; + bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; bool isMemOp(const MachineInstr *MI) const; bool isSpillPredRegOp(const MachineInstr *MI) const; @@ -165,21 +185,47 @@ public: bool isConditionalALU32 (const MachineInstr* MI) const; bool isConditionalLoad (const MachineInstr* MI) const; bool isConditionalStore(const MachineInstr* MI) const; + bool isNewValueInst(const MachineInstr* MI) const; + bool isNewValue(const MachineInstr* MI) const; + bool isNewValue(Opcode_t Opcode) const; + bool isDotNewInst(const MachineInstr* MI) const; + int GetDotOldOp(const int opc) const; + int GetDotNewOp(const MachineInstr* MI) const; + int GetDotNewPredOp(MachineInstr *MI, + const MachineBranchProbabilityInfo + *MBPI) const; + bool mayBeNewStore(const MachineInstr* MI) const; bool isDeallocRet(const MachineInstr *MI) const; unsigned getInvertedPredicatedOpcode(const int Opc) const; bool isExtendable(const MachineInstr* MI) const; bool isExtended(const MachineInstr* MI) const; bool isPostIncrement(const MachineInstr* MI) const; bool isNewValueStore(const MachineInstr* MI) const; + bool isNewValueStore(unsigned Opcode) const; bool isNewValueJump(const MachineInstr* MI) const; + bool isNewValueJump(Opcode_t Opcode) const; bool isNewValueJumpCandidate(const MachineInstr *MI) const; - unsigned getImmExtForm(const MachineInstr* MI) const; - unsigned getNormalBranchForm(const MachineInstr* MI) const; - bool isExpr(unsigned OpType) const; - bool isConstExtended(MachineInstr *MI) const; -private: - int getMatchingCondBranchOpcode(int Opc, bool sense) const; + + void immediateExtend(MachineInstr *MI) const; + bool isConstExtended(const MachineInstr *MI) const; + unsigned getSize(const MachineInstr *MI) const; + int getDotNewPredJumpOp(MachineInstr *MI, + const MachineBranchProbabilityInfo *MBPI) const; + unsigned getAddrMode(const MachineInstr* MI) const; + bool isOperandExtended(const MachineInstr *MI, + unsigned short OperandNum) const; + unsigned short getCExtOpNum(const MachineInstr *MI) const; + int getMinValue(const MachineInstr *MI) const; + int getMaxValue(const MachineInstr *MI) const; + bool NonExtEquivalentExists (const MachineInstr *MI) const; + short getNonExtOpcode(const MachineInstr *MI) const; + bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; + bool predOpcodeHasNot(ArrayRef Cond) const; + bool isEndLoopN(Opcode_t Opcode) const; + bool getPredReg(ArrayRef Cond, unsigned &PredReg, + unsigned &PredRegPos, unsigned &PredRegFlags) const; + int getCondOpcode(int Opc, bool sense) const; };