X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FHexagon%2FHexagonISelDAGToDAG.cpp;h=9bf2be9e10048e692d842f48503f205bd7599dea;hb=d25cfdb6495ce1aba944cda1c897dfc89fe64952;hp=c59bc0b21c0363debd92eed162c8241ba1397824;hpb=609c7fa14eca7e98f979c62efe69071d9b8e4681;p=oota-llvm.git diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index c59bc0b21c0..9bf2be9e100 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -320,38 +320,38 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID) default: return 0; case Intrinsic::hexagon_C2_tfrpr: - return Hexagon::TFR_RsPd; + return Hexagon::C2_tfrpr; case Intrinsic::hexagon_C2_and: - return Hexagon::AND_pp; + return Hexagon::C2_and; case Intrinsic::hexagon_C2_xor: - return Hexagon::XOR_pp; + return Hexagon::C2_xor; case Intrinsic::hexagon_C2_or: - return Hexagon::OR_pp; + return Hexagon::C2_or; case Intrinsic::hexagon_C2_not: - return Hexagon::NOT_p; + return Hexagon::C2_not; case Intrinsic::hexagon_C2_any8: - return Hexagon::ANY_pp; + return Hexagon::C2_any8; case Intrinsic::hexagon_C2_all8: - return Hexagon::ALL_pp; + return Hexagon::C2_all8; case Intrinsic::hexagon_C2_vitpack: - return Hexagon::VITPACK_pp; + return Hexagon::C2_vitpack; case Intrinsic::hexagon_C2_mask: - return Hexagon::MASK_p; + return Hexagon::C2_mask; case Intrinsic::hexagon_C2_mux: return Hexagon::C2_mux; // Mapping hexagon_C2_muxir to MUX_pri. This is pretty weird - but // that's how it's mapped in q6protos.h. case Intrinsic::hexagon_C2_muxir: - return Hexagon::MUX_ri; + return Hexagon::C2_muxri; // Mapping hexagon_C2_muxri to MUX_pir. This is pretty weird - but // that's how it's mapped in q6protos.h. case Intrinsic::hexagon_C2_muxri: - return Hexagon::MUX_ir; + return Hexagon::C2_muxir; case Intrinsic::hexagon_C2_muxii: - return Hexagon::MUX_ii; + return Hexagon::C2_muxii; case Intrinsic::hexagon_C2_vmux: return Hexagon::VMUX_prr64; case Intrinsic::hexagon_S2_valignrb: @@ -404,10 +404,10 @@ SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) { dl, PointerTy, TargAddr); // Figure out base + offset opcode - if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed; - else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed; - else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed; - else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed; + if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io; + else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io; + else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io; + else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io; else llvm_unreachable("unknown memory type"); // Build indexed load. @@ -453,7 +453,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MVT::Other, Base, TargetConst, Chain); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64, SDValue(Result_1, 0)); MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = LD->getMemOperand(); @@ -474,7 +474,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other, Base, TargetConst0, Chain); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64, SDValue(Result_1, 0)); SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32, Base, TargetConstVal, @@ -521,9 +521,9 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, MVT::Other, Base, TargetConstVal, Chain); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, TargetConst0); - SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl, + SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl, MVT::i64, MVT::Other, SDValue(Result_2,0), SDValue(Result_1,0)); @@ -548,9 +548,9 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other, Base, TargetConst0, Chain); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, TargetConst0); - SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl, + SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl, MVT::i64, MVT::Other, SDValue(Result_2,0), SDValue(Result_1,0)); @@ -595,24 +595,24 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) { TM.getSubtargetImpl()->getInstrInfo()); if (LoadedVT == MVT::i64) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = Hexagon::POST_LDrid; + Opcode = Hexagon::L2_loadrd_pi; else - Opcode = Hexagon::LDrid; + Opcode = Hexagon::L2_loadrd_io; } else if (LoadedVT == MVT::i32) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = Hexagon::POST_LDriw; + Opcode = Hexagon::L2_loadri_pi; else - Opcode = Hexagon::LDriw; + Opcode = Hexagon::L2_loadri_io; } else if (LoadedVT == MVT::i16) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih; + Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi; else - Opcode = zextval ? Hexagon::LDriuh : Hexagon::LDrih; + Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io; } else if (LoadedVT == MVT::i8) { if (TII->isValidAutoIncImm(LoadedVT, Val)) - Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib; + Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi; else - Opcode = zextval ? Hexagon::LDriub : Hexagon::LDrib; + Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io; } else llvm_unreachable("unknown memory type"); @@ -712,7 +712,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) { if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri; else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri; else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri; - else if (StoredVT == MVT::i8) Opcode = Hexagon::POST_STbri; + else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi; else llvm_unreachable("unknown memory type"); // Build post increment store. @@ -865,7 +865,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) { SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); - OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, + OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, MVT::Other, LD->getBasePtr(), TargetConst0, Chain), 0); @@ -891,7 +891,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) { SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); - OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, + OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, MVT::Other, LD->getBasePtr(), TargetConst0, Chain), 0); @@ -900,7 +900,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) { } // Generate a mpy instruction. - SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY64, dl, MVT::i64, + SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64, OP0, OP1); ReplaceUses(N, Result); return Result; @@ -936,7 +936,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) { N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) { SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl, MVT::i32, N000); - SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl, + SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl, MVT::i32, SDValue(SextNode, 0), N1); @@ -960,7 +960,7 @@ SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) { N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) { SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl, MVT::i32, N000); - SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl, + SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl, MVT::i32, SDValue(SextNode, 0), N1); @@ -1045,7 +1045,7 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) { SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); - OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, + OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, MVT::Other, LD->getBasePtr(), TargetConst0, Chain), 0); @@ -1070,7 +1070,7 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) { SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); - OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, + OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, MVT::Other, LD->getBasePtr(), TargetConst0, Chain), 0); @@ -1079,7 +1079,7 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) { } // Generate a mpy instruction. - SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY, dl, MVT::i32, + SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32, OP0, OP1); ReplaceUses(N, Result); return Result; @@ -1112,7 +1112,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) { if (ConstantSDNode *CN = dyn_cast(Val.getNode())) if (isInt<9>(CN->getSExtValue())) { SDNode* Result = - CurDAG->getMachineNode(Hexagon::MPYI_ri, dl, + CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32, Mul_0, Val); ReplaceUses(N, Result); return Result; @@ -1140,7 +1140,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) { dyn_cast(Val.getNode())) if (isInt<9>(CN->getSExtValue())) { SDNode* Result = - CurDAG->getMachineNode(Hexagon::MPYI_ri, dl, MVT::i32, + CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32, Shl2_0, Val); ReplaceUses(N, Result); return Result; @@ -1177,13 +1177,13 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) { if (N->getValueType(0) == MVT::i64) { // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs). SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); - SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl, + SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl, MVT::i32, SDValue(IsIntrinsic, 0)); - SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, + SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, TargetConst0); - SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl, + SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl, MVT::i64, MVT::Other, SDValue(Result_2, 0), SDValue(Result_1, 0)); @@ -1192,7 +1192,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) { } if (N->getValueType(0) == MVT::i32) { // Convert the zero_extend to Rs = Pd - SDNode* RsPd = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl, + SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl, MVT::i32, SDValue(IsIntrinsic, 0)); ReplaceUses(N, RsPd); @@ -1236,7 +1236,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { Ops.push_back(SDValue(Arg, 0)); } else if (RC == &Hexagon::PredRegsRegClass) { // Do the transfer. - SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1, + SDNode *PdRs = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1, SDValue(Arg, 0)); Ops.push_back(SDValue(PdRs,0)); } else if (!RC && (dyn_cast(Arg) != nullptr)) { @@ -1289,19 +1289,19 @@ SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) { if (Val == -1) { // Create the IntReg = 1 node. SDNode* IntRegTFR = - CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32, + CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)); // Pd = IntReg - SDNode* Pd = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1, + SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1, SDValue(IntRegTFR, 0)); // not(Pd) - SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_p, dl, MVT::i1, + SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1, SDValue(Pd, 0)); // xor(not(Pd)) - Result = CurDAG->getMachineNode(Hexagon::XOR_pp, dl, MVT::i1, + Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1, SDValue(Pd, 0), SDValue(NotPd, 0)); // We have just built: @@ -1334,7 +1334,7 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) { // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that // Rd and Rd' are assigned to the same register - SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_ADD_rr, dl, MVT::i32, + SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32, N->getOperand(1), Src1->getOperand(0), Src1->getOperand(1));