X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaRegisterInfo.cpp;h=f1e651c6a805894ee2eea08146f981a482a3d17f;hb=c25e7581b9b8088910da31702d4ca21c4734c6d7;hp=6cf9df71346089fb4827f71c1eb6de5652ac475b;hpb=f191c80cd79ee35e47b5a4feed98d687782dfe85;p=oota-llvm.git diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 6cf9df71346..f1e651c6a80 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -2,12 +2,12 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// @@ -28,6 +28,8 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include @@ -54,172 +56,10 @@ static long getLower16(long l) AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), - TII(tii) + TII(tii), curgpdist(0) { } -void -AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const { - //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " - // << FrameIdx << "\n"; - //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); - if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, TII.get(Alpha::STS)) - .addReg(SrcReg, false, false, true) - .addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, TII.get(Alpha::STT)) - .addReg(SrcReg, false, false, true) - .addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, TII.get(Alpha::STQ)) - .addReg(SrcReg, false, false, true) - .addFrameIndex(FrameIdx).addReg(Alpha::F31); - else - abort(); -} - -void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { - unsigned Opc = 0; - if (RC == Alpha::F4RCRegisterClass) - Opc = Alpha::STS; - else if (RC == Alpha::F8RCRegisterClass) - Opc = Alpha::STT; - else if (RC == Alpha::GPRCRegisterClass) - Opc = Alpha::STQ; - else - abort(); - MachineInstrBuilder MIB = - BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); - for (unsigned i = 0, e = Addr.size(); i != e; ++i) { - MachineOperand &MO = Addr[i]; - if (MO.isRegister()) - MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); - else - MIB.addImm(MO.getImm()); - } - NewMIs.push_back(MIB); -} - -void -AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC) const { - //cerr << "Trying to load " << getPrettyName(DestReg) << " to " - // << FrameIdx << "\n"; - if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg) - .addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg) - .addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg) - .addFrameIndex(FrameIdx).addReg(Alpha::F31); - else - abort(); -} - -void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const { - unsigned Opc = 0; - if (RC == Alpha::F4RCRegisterClass) - Opc = Alpha::LDS; - else if (RC == Alpha::F8RCRegisterClass) - Opc = Alpha::LDT; - else if (RC == Alpha::GPRCRegisterClass) - Opc = Alpha::LDQ; - else - abort(); - MachineInstrBuilder MIB = - BuildMI(TII.get(Opc), DestReg); - for (unsigned i = 0, e = Addr.size(); i != e; ++i) { - MachineOperand &MO = Addr[i]; - if (MO.isRegister()) - MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); - else - MIB.addImm(MO.getImm()); - } - NewMIs.push_back(MIB); -} - -MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, - unsigned OpNum, - int FrameIndex) const { - // Make sure this is a reg-reg copy. - unsigned Opc = MI->getOpcode(); - - MachineInstr *NewMI = NULL; - switch(Opc) { - default: - break; - case Alpha::BISr: - case Alpha::CPYSS: - case Alpha::CPYST: - if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { - if (OpNum == 0) { // move -> store - unsigned InReg = MI->getOperand(1).getReg(); - Opc = (Opc == Alpha::BISr) ? Alpha::STQ : - ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } else { // load -> move - unsigned OutReg = MI->getOperand(0).getReg(); - Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : - ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } - } - break; - } - if (NewMI) - NewMI->copyKillDeadInfo(MI); - return 0; -} - - -void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { - //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; - if (DestRC != SrcRC) { - cerr << "Not yet supported!"; - abort(); - } - - if (DestRC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (DestRC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } -} - -void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, - const MachineInstr *Orig) const { - MachineInstr *MI = Orig->clone(); - MI->getOperand(0).setReg(DestReg); - MBB.insert(I, MI); -} - const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { static const unsigned CalleeSavedRegs[] = { @@ -265,7 +105,7 @@ BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // if frame pointer elimination is disabled. // bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } @@ -277,7 +117,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP, // ' MachineInstr *Old = I; - uint64_t Amount = Old->getOperand(0).getImmedValue(); + uint64_t Amount = Old->getOperand(0).getImm(); if (Amount != 0) { // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next @@ -287,11 +127,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -321,12 +161,12 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineFunction &MF = *MBB.getParent(); bool FP = hasFP(MF); - while (!MI.getOperand(i).isFrameIndex()) { + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } - int FrameIndex = MI.getOperand(i).getFrameIndex(); + int FrameIndex = MI.getOperand(i).getIndex(); // Add the base register of R30 (SP) or R15 (FP). MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); @@ -350,7 +190,8 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28) + MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(), + TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { @@ -363,20 +204,20 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = (MBBI != MBB.end() ? + MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); bool FP = hasFP(MF); - static int curgpdist = 0; - //handle GOP offset - BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) .addGlobalAddress(const_cast(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo @@ -397,25 +238,27 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { // adjust stack pointer: r30 -= numbytes NumBytes = -NumBytes; if (NumBytes >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) >= IMM_LOW) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes)) - .addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes)) - .addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { - cerr << "Too big a stack frame at " << NumBytes << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Too big a stack frame at " + NumBytes; + llvm_report_error(Msg.str()); } //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, TII.get(Alpha::STQ)) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) .addReg(Alpha::R30).addReg(Alpha::R30); } @@ -425,9 +268,10 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert(MBBI->getOpcode() == Alpha::RETDAG || - MBBI->getOpcode() == Alpha::RETDAGp + assert((MBBI->getOpcode() == Alpha::RETDAG || + MBBI->getOpcode() == Alpha::RETDAGp) && "Can only insert epilog into returning blocks"); + DebugLoc dl = MBBI->getDebugLoc(); bool FP = hasFP(MF); @@ -435,34 +279,35 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, long NumBytes = MFI->getStackSize(); //now if we need to, restore the old FP - if (FP) - { + if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) .addReg(Alpha::R15); //restore the FP - BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) + .addImm(0).addReg(Alpha::R15); } - if (NumBytes != 0) - { - if (NumBytes <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) - .addReg(Alpha::R30); - } else if (getUpper16(NumBytes) <= IMM_HIGH) { - BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30) - .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30) - .addImm(getLower16(NumBytes)).addReg(Alpha::R30); - } else { - cerr << "Too big a stack frame at " << NumBytes << "\n"; - abort(); - } - } + if (NumBytes != 0) { + if (NumBytes <= IMM_HIGH) { + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + .addReg(Alpha::R30); + } else if (getUpper16(NumBytes) <= IMM_HIGH) { + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); + } else { + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Too big a stack frame at " + NumBytes; + llvm_report_error(Msg.str()); + } + } } unsigned AlphaRegisterInfo::getRARegister() const { - assert(0 && "What is the return address register"); + LLVM_UNREACHABLE("What is the return address register"); return 0; } @@ -471,17 +316,17 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned AlphaRegisterInfo::getEHExceptionRegister() const { - assert(0 && "What is the exception register"); + LLVM_UNREACHABLE("What is the exception register"); return 0; } unsigned AlphaRegisterInfo::getEHHandlerRegister() const { - assert(0 && "What is the exception handler register"); + LLVM_UNREACHABLE("What is the exception handler register"); return 0; } -int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum) const { - assert(0 && "What is the dwarf register number"); +int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { + LLVM_UNREACHABLE("What is the dwarf register number"); return -1; }