X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaRegisterInfo.cpp;h=be9cbf516f92c9b7234bf8097fb2b0e078d1f204;hb=d10fd9791c20fd8368fa0ce94b626b769c6c8ba0;hp=bafd3b3229e0701ec3fcff099af7bd352bebc438;hpb=f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8;p=oota-llvm.git diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index bafd3b3229e..be9cbf516f9 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -28,6 +28,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include using namespace llvm; @@ -60,22 +61,51 @@ AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) void AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const { + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " // << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (RC == Alpha::F4RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STS)) - .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + .addReg(SrcReg, false, false, isKill) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STT)) - .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + .addReg(SrcReg, false, false, isKill) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STQ)) - .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + .addReg(SrcReg, false, false, isKill) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); + else + abort(); +} + +void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + bool isKill, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const { + unsigned Opc = 0; + if (RC == Alpha::F4RCRegisterClass) + Opc = Alpha::STS; + else if (RC == Alpha::F8RCRegisterClass) + Opc = Alpha::STT; + else if (RC == Alpha::GPRCRegisterClass) + Opc = Alpha::STQ; else abort(); + MachineInstrBuilder MIB = + BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); + else + MIB.addImm(MO.getImm()); + } + NewMIs.push_back(MIB); } void @@ -98,9 +128,36 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, abort(); } +void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVectorImpl &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl &NewMIs) const { + unsigned Opc = 0; + if (RC == Alpha::F4RCRegisterClass) + Opc = Alpha::LDS; + else if (RC == Alpha::F8RCRegisterClass) + Opc = Alpha::LDT; + else if (RC == Alpha::GPRCRegisterClass) + Opc = Alpha::LDQ; + else + abort(); + MachineInstrBuilder MIB = + BuildMI(TII.get(Opc), DestReg); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); + else + MIB.addImm(MO.getImm()); + } + NewMIs.push_back(MIB); +} + MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, - unsigned OpNum, + SmallVectorImpl &Ops, int FrameIndex) const { + if (Ops.size() != 1) return NULL; + // Make sure this is a reg-reg copy. unsigned Opc = MI->getOpcode(); @@ -112,18 +169,18 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, case Alpha::CPYSS: case Alpha::CPYST: if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { - if (OpNum == 0) { // move -> store - unsigned InReg = MI->getOperand(1).getReg(); - Opc = (Opc == Alpha::BISr) ? Alpha::STQ : - ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); + if (Ops[0] == 0) { // move -> store + unsigned InReg = MI->getOperand(1).getReg(); + Opc = (Opc == Alpha::BISr) ? Alpha::STQ : + ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); + NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex) + .addReg(Alpha::F31); } else { // load -> move - unsigned OutReg = MI->getOperand(0).getReg(); - Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : - ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); + unsigned OutReg = MI->getOperand(0).getReg(); + Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : + ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); + NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex) + .addReg(Alpha::F31); } } break; @@ -133,26 +190,18 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, return 0; } - -void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; - if (RC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } +void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, + const MachineInstr *Orig) const { + MachineInstr *MI = Orig->clone(); + MI->getOperand(0).setReg(DestReg); + MBB.insert(I, MI); } -const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const { - static const unsigned CalleeSaveRegs[] = { +const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) + const { + static const unsigned CalleeSavedRegs[] = { Alpha::R9, Alpha::R10, Alpha::R11, Alpha::R12, Alpha::R13, Alpha::R14, @@ -161,12 +210,12 @@ const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const { Alpha::F6, Alpha::F7, Alpha::F8, Alpha::F9, 0 }; - return CalleeSaveRegs; + return CalleeSavedRegs; } const TargetRegisterClass* const* -AlphaRegisterInfo::getCalleeSaveRegClasses() const { - static const TargetRegisterClass * const CalleeSaveRegClasses[] = { +AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { + static const TargetRegisterClass * const CalleeSavedRegClasses[] = { &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, @@ -175,7 +224,15 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const { &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0 }; - return CalleeSaveRegClasses; + return CalleeSavedRegClasses; +} + +BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + Reserved.set(Alpha::R15); + Reserved.set(Alpha::R30); + Reserved.set(Alpha::R31); + return Reserved; } //===----------------------------------------------------------------------===// @@ -186,7 +243,7 @@ AlphaRegisterInfo::getCalleeSaveRegClasses() const { // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(const MachineFunction &MF) { +bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } @@ -199,7 +256,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP, // ' MachineInstr *Old = I; - uint64_t Amount = Old->getOperand(0).getImmedValue(); + uint64_t Amount = Old->getOperand(0).getImm(); if (Amount != 0) { // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next @@ -233,8 +290,10 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, //variable locals //<- SP -void -AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { +void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected"); + unsigned i = 0; MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); @@ -246,7 +305,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } - int FrameIndex = MI.getOperand(i).getFrameIndex(); + int FrameIndex = MI.getOperand(i).getIndex(); // Add the base register of R30 (SP) or R15 (FP). MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); @@ -302,16 +361,6 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { // Get the number of bytes to allocate from the FrameInfo long NumBytes = MFI->getStackSize(); - if (MFI->hasCalls() && !FP) { - // We reserve argument space for call sites in the function immediately on - // entry to the current function. This eliminates the need for add/sub - // brackets around call sites. - //If there is a frame pointer, then we don't do this - NumBytes += MFI->getMaxCallFrameSize(); - DOUT << "Added " << MFI->getMaxCallFrameSize() - << " to the stack due to calls\n"; - } - if (FP) NumBytes += 8; //reserve space for the old FP @@ -400,6 +449,21 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { return hasFP(MF) ? Alpha::R15 : Alpha::R30; } +unsigned AlphaRegisterInfo::getEHExceptionRegister() const { + assert(0 && "What is the exception register"); + return 0; +} + +unsigned AlphaRegisterInfo::getEHHandlerRegister() const { + assert(0 && "What is the exception handler register"); + return 0; +} + +int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { + assert(0 && "What is the dwarf register number"); + return -1; +} + #include "AlphaGenRegisterInfo.inc" std::string AlphaRegisterInfo::getPrettyName(unsigned reg)