X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaISelDAGToDAG.cpp;h=89dee2a4fa5f39a59b5a2a4fb117d8fca120998e;hb=475871a144eb604ddaf37503397ba0941442e5fb;hp=5fadc81ce84720421ef0d0741695d7f1f2e5427a;hpb=53d89706257889e92f60e08f3b1e92dcbadca80c;p=oota-llvm.git diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 5fadc81ce84..89dee2a4fa5 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Andrew Lenharth and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -18,16 +18,20 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/Statistic.h" #include "llvm/Constants.h" +#include "llvm/DerivedTypes.h" #include "llvm/GlobalValue.h" +#include "llvm/Intrinsics.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include +#include +#include using namespace llvm; namespace { @@ -38,39 +42,159 @@ namespace { class AlphaDAGToDAGISel : public SelectionDAGISel { AlphaTargetLowering AlphaLowering; - static const int IMM_LOW = -32768; - static const int IMM_HIGH = 32767; - static const int IMM_MULT = 65536; + static const int64_t IMM_LOW = -32768; + static const int64_t IMM_HIGH = 32767; + static const int64_t IMM_MULT = 65536; + static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT; + static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT; + + static int64_t get_ldah16(int64_t x) { + int64_t y = x / IMM_MULT; + if (x % IMM_MULT > IMM_HIGH) + ++y; + return y; + } + + static int64_t get_lda16(int64_t x) { + return x - get_ldah16(x) * IMM_MULT; + } + + /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot + /// instruction (if not, return 0). Note that this code accepts partial + /// zap masks. For example (and LHS, 1) is a valid zap, as long we know + /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are + /// in checking mode. If LHS is null, we assume that the mask has already + /// been validated before. + uint64_t get_zapImm(SDValue LHS, uint64_t Constant) { + uint64_t BitsToCheck = 0; + unsigned Result = 0; + for (unsigned i = 0; i != 8; ++i) { + if (((Constant >> 8*i) & 0xFF) == 0) { + // nothing to do. + } else { + Result |= 1 << i; + if (((Constant >> 8*i) & 0xFF) == 0xFF) { + // If the entire byte is set, zapnot the byte. + } else if (LHS.Val == 0) { + // Otherwise, if the mask was previously validated, we know its okay + // to zapnot this entire byte even though all the bits aren't set. + } else { + // Otherwise we don't know that the it's okay to zapnot this entire + // byte. Only do this iff we can prove that the missing bits are + // already null, so the bytezap doesn't need to really null them. + BitsToCheck |= ~Constant & (0xFF << 8*i); + } + } + } + + // If there are missing bits in a byte (for example, X & 0xEF00), check to + // see if the missing bits (0x1000) are already known zero if not, the zap + // isn't okay to do, as it won't clear all the required bits. + if (BitsToCheck && + !CurDAG->MaskedValueIsZero(LHS, + APInt(LHS.getValueSizeInBits(), + BitsToCheck))) + return 0; + + return Result; + } + static uint64_t get_zapImm(uint64_t x) { + unsigned build = 0; + for(int i = 0; i != 8; ++i) { + if ((x & 0x00FF) == 0x00FF) + build |= 1 << i; + else if ((x & 0x00FF) != 0) + return 0; + x >>= 8; + } + return build; + } + + + static uint64_t getNearPower2(uint64_t x) { + if (!x) return 0; + unsigned at = CountLeadingZeros_64(x); + uint64_t complow = 1 << (63 - at); + uint64_t comphigh = 1 << (64 - at); + //cerr << x << ":" << complow << ":" << comphigh << "\n"; + if (abs(complow - x) <= abs(comphigh - x)) + return complow; + else + return comphigh; + } + + static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) { + uint64_t y = getNearPower2(x); + if (swap) + return (y - x) == r; + else + return (x - y) == r; + } + + static bool isFPZ(SDValue N) { + ConstantFPSDNode *CN = dyn_cast(N); + return (CN && (CN->getValueAPF().isZero())); + } + static bool isFPZn(SDValue N) { + ConstantFPSDNode *CN = dyn_cast(N); + return (CN && CN->getValueAPF().isNegZero()); + } + static bool isFPZp(SDValue N) { + ConstantFPSDNode *CN = dyn_cast(N); + return (CN && CN->getValueAPF().isPosZero()); + } + public: - AlphaDAGToDAGISel(TargetMachine &TM) - : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {} + explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM) + : SelectionDAGISel(AlphaLowering), + AlphaLowering(*TM.getTargetLowering()) + {} /// getI64Imm - Return a target constant with the specified value, of type /// i64. - inline SDOperand getI64Imm(int64_t Imm) { + inline SDValue getI64Imm(int64_t Imm) { return CurDAG->getTargetConstant(Imm, MVT::i64); } // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. - SDOperand Select(SDOperand Op); + SDNode *Select(SDValue Op); - /// InstructionSelectBasicBlock - This callback is invoked by + /// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. - virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); + virtual void InstructionSelect(SelectionDAG &DAG); virtual const char *getPassName() const { return "Alpha DAG->DAG Pattern Instruction Selection"; } + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for + /// inline asm expressions. + virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, + char ConstraintCode, + std::vector &OutOps, + SelectionDAG &DAG) { + SDValue Op0; + switch (ConstraintCode) { + default: return true; + case 'm': // memory + Op0 = Op; + AddToISelQueue(Op0); + break; + } + + OutOps.push_back(Op0); + return false; + } + // Include the pieces autogenerated from the target description. #include "AlphaGenDAGISel.inc" private: - SDOperand getGlobalBaseReg(); - SDOperand getRASaveReg(); - SDOperand SelectCALL(SDOperand Op); + SDValue getGlobalBaseReg(); + SDValue getGlobalRetAddr(); + void SelectCALL(SDValue Op); }; } @@ -78,297 +202,279 @@ private: /// getGlobalBaseReg - Output the instructions required to put the /// GOT address into a register. /// -SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { +SDValue AlphaDAGToDAGISel::getGlobalBaseReg() { + unsigned GP = 0; + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) + if (ii->first == Alpha::R29) { + GP = ii->second; + break; + } + assert(GP && "GOT PTR not in liveins"); return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - AlphaLowering.getVRegGP(), - MVT::i64); + GP, MVT::i64); } /// getRASaveReg - Grab the return address /// -SDOperand AlphaDAGToDAGISel::getRASaveReg() { +SDValue AlphaDAGToDAGISel::getGlobalRetAddr() { + unsigned RA = 0; + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) + if (ii->first == Alpha::R26) { + RA = ii->second; + break; + } + assert(RA && "RA PTR not in liveins"); return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - AlphaLowering.getVRegRA(), - MVT::i64); + RA, MVT::i64); } -/// InstructionSelectBasicBlock - This callback is invoked by +/// InstructionSelect - This callback is invoked by /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. -void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { +void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) { DEBUG(BB->dump()); // Select target instructions for the DAG. - DAG.setRoot(Select(DAG.getRoot())); - CodeGenMap.clear(); + DAG.setRoot(SelectRoot(DAG.getRoot())); DAG.RemoveDeadNodes(); - - // Emit machine code to BB. - ScheduleAndEmitDAG(DAG); } // Select - Convert the specified operand from a target-independent to a // target-specific node if it hasn't already been changed. -SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) { +SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.Val; - if (N->getOpcode() >= ISD::BUILTIN_OP_END && - N->getOpcode() < AlphaISD::FIRST_NUMBER) - return Op; // Already selected. + if (N->isMachineOpcode()) { + return NULL; // Already selected. + } - // If this has already been converted, use it. - std::map::iterator CGMI = CodeGenMap.find(Op); - if (CGMI != CodeGenMap.end()) return CGMI->second; - switch (N->getOpcode()) { default: break; - case ISD::TAILCALL: - case ISD::CALL: return SelectCALL(Op); - - case ISD::DYNAMIC_STACKALLOC: { - if (!isa(N->getOperand(2)) || - cast(N->getOperand(2))->getValue() != 0) { - std::cerr << "Cannot allocate stack object with greater alignment than" - << " the stack alignment yet!"; - abort(); - } - - SDOperand Chain = Select(N->getOperand(0)); - SDOperand Amt = Select(N->getOperand(1)); - SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64); - SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64); - Chain = Val.getValue(1); - - // Subtract the amount (guaranteed to be a multiple of the stack alignment) - // from the stack pointer, giving us the result pointer. - SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt); - - // Copy this result back into R30. - Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result); - - // Copy this result back out of R30 to make sure we're not using the stack - // space without decrementing the stack pointer. - Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64); - - // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg. - CodeGenMap[Op.getValue(0)] = Result; - CodeGenMap[Op.getValue(1)] = Result.getValue(1); - return SDOperand(Result.Val, Op.ResNo); - } - case ISD::BRCOND: { - if (N->getOperand(1).getOpcode() == ISD::SETCC && - MVT::isFloatingPoint(N->getOperand(1).getOperand(0).getValueType())) { - SDOperand Chain = Select(N->getOperand(0)); - SDOperand CC1 = Select(N->getOperand(1).getOperand(0)); - SDOperand CC2 = Select(N->getOperand(1).getOperand(1)); - ISD::CondCode cCode= cast(N->getOperand(1).getOperand(2))->get(); + case AlphaISD::CALL: + SelectCALL(Op); + return NULL; - bool rev = false; - bool isNE = false; - unsigned Opc = Alpha::WTF; - switch(cCode) { - default: N->dump(); assert(0 && "Unknown FP comparison!"); - case ISD::SETEQ: Opc = Alpha::CMPTEQ; break; - case ISD::SETLT: Opc = Alpha::CMPTLT; break; - case ISD::SETLE: Opc = Alpha::CMPTLE; break; - case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break; - case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break; - case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break; - }; - SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, - rev?CC2:CC1, - rev?CC1:CC2); - - MachineBasicBlock *Dest = - cast(N->getOperand(2))->getBasicBlock(); - if(isNE) - return CurDAG->SelectNodeTo(N, Alpha::FBEQ, MVT::Other, cmp, - CurDAG->getBasicBlock(Dest), Chain); - else - return CurDAG->SelectNodeTo(N, Alpha::FBNE, MVT::Other, cmp, - CurDAG->getBasicBlock(Dest), Chain); - } - SDOperand Chain = Select(N->getOperand(0)); - SDOperand CC = Select(N->getOperand(1)); - MachineBasicBlock *Dest = - cast(N->getOperand(2))->getBasicBlock(); - return CurDAG->SelectNodeTo(N, Alpha::BNE, MVT::Other, CC, - CurDAG->getBasicBlock(Dest), Chain); - } - - case ISD::BR: - return CurDAG->SelectNodeTo(N, Alpha::BR_DAG, MVT::Other, N->getOperand(1), - Select(N->getOperand(0))); case ISD::FrameIndex: { int FI = cast(N)->getIndex(); return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i32), getI64Imm(0)); } - case AlphaISD::GlobalBaseReg: - return getGlobalBaseReg(); + case ISD::GLOBAL_OFFSET_TABLE: { + SDValue Result = getGlobalBaseReg(); + ReplaceUses(Op, Result); + return NULL; + } + case AlphaISD::GlobalRetAddr: { + SDValue Result = getGlobalRetAddr(); + ReplaceUses(Op, Result); + return NULL; + } case AlphaISD::DivCall: { - SDOperand Chain = CurDAG->getEntryNode(); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, Select(Op.getOperand(1)), - SDOperand(0,0)); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Select(Op.getOperand(2)), - Chain.getValue(1)); - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)), - Chain.getValue(1)); - Chain = CurDAG->getTargetNode(Alpha::JSRsDAG, MVT::Other, MVT::Flag, - Chain, Chain.getValue(1)); + SDValue Chain = CurDAG->getEntryNode(); + SDValue N0 = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + AddToISelQueue(N0); + AddToISelQueue(N1); + AddToISelQueue(N2); + Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1, + SDValue(0,0)); + Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2, + Chain.getValue(1)); + Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0, + Chain.getValue(1)); + SDNode *CNode = + CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag, + Chain, Chain.getValue(1)); Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64, - Chain.getValue(1)); - return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain); + SDValue(CNode, 1)); + return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); } - case ISD::RET: { - SDOperand Chain = Select(N->getOperand(0)); // Token chain. - SDOperand InFlag; - - if (N->getNumOperands() == 2) { - SDOperand Val = Select(N->getOperand(1)); - if (N->getOperand(1).getValueType() == MVT::i64) { - Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag); - InFlag = Chain.getValue(1); - } else if (N->getOperand(1).getValueType() == MVT::f64 || - N->getOperand(1).getValueType() == MVT::f32) { - Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag); - InFlag = Chain.getValue(1); - } - } - Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag); - InFlag = Chain.getValue(1); - - // Finally, select this to a ret instruction. - return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag); + case ISD::READCYCLECOUNTER: { + SDValue Chain = N->getOperand(0); + AddToISelQueue(Chain); //Select chain + return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other, + Chain); } + case ISD::Constant: { - int64_t val = (int64_t)cast(N)->getValue(); - if (val > (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT || - val < (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) { - MachineConstantPool *CP = BB->getParent()->getConstantPool(); - ConstantUInt *C = - ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val); - SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64); - Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg()); - return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, CPI, Tmp); + uint64_t uval = cast(N)->getValue(); + + if (uval == 0) { + SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), + Alpha::R31, MVT::i64); + ReplaceUses(Op, Result); + return NULL; } - break; + + int64_t val = (int64_t)uval; + int32_t val32 = (int32_t)val; + if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT && + val >= IMM_LOW + IMM_LOW * IMM_MULT) + break; //(LDAH (LDA)) + if ((uval >> 32) == 0 && //empty upper bits + val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT) + // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true + break; //(zext (LDAH (LDA))) + //Else use the constant pool + ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval); + SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64); + SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, + getGlobalBaseReg()); + return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, + CPI, SDValue(Tmp, 0), CurDAG->getEntryNode()); } - case ISD::ConstantFP: - if (ConstantFPSDNode *CN = dyn_cast(N)) { - bool isDouble = N->getValueType(0) == MVT::f64; - MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32; - if (CN->isExactlyValue(+0.0)) { - return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, - T, CurDAG->getRegister(Alpha::F31, T), - CurDAG->getRegister(Alpha::F31, T)); - } else if ( CN->isExactlyValue(-0.0)) { - return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, - T, CurDAG->getRegister(Alpha::F31, T), - CurDAG->getRegister(Alpha::F31, T)); - } else { - abort(); - } - break; + case ISD::TargetConstantFP: { + ConstantFPSDNode *CN = cast(N); + bool isDouble = N->getValueType(0) == MVT::f64; + MVT T = isDouble ? MVT::f64 : MVT::f32; + if (CN->getValueAPF().isPosZero()) { + return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, + T, CurDAG->getRegister(Alpha::F31, T), + CurDAG->getRegister(Alpha::F31, T)); + } else if (CN->getValueAPF().isNegZero()) { + return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS, + T, CurDAG->getRegister(Alpha::F31, T), + CurDAG->getRegister(Alpha::F31, T)); + } else { + abort(); } + break; + } case ISD::SETCC: - if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) { - unsigned Opc = Alpha::WTF; + if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) { ISD::CondCode CC = cast(N->getOperand(2))->get(); + + unsigned Opc = Alpha::WTF; bool rev = false; - bool isNE = false; + bool inv = false; switch(CC) { - default: N->dump(); assert(0 && "Unknown FP comparison!"); - case ISD::SETEQ: Opc = Alpha::CMPTEQ; break; - case ISD::SETLT: Opc = Alpha::CMPTLT; break; - case ISD::SETLE: Opc = Alpha::CMPTLE; break; - case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break; - case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break; - case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break; + default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!"); + case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: + Opc = Alpha::CMPTEQ; break; + case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: + Opc = Alpha::CMPTLT; break; + case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: + Opc = Alpha::CMPTLE; break; + case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: + Opc = Alpha::CMPTLT; rev = true; break; + case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: + Opc = Alpha::CMPTLE; rev = true; break; + case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: + Opc = Alpha::CMPTEQ; inv = true; break; + case ISD::SETO: + Opc = Alpha::CMPTUN; inv = true; break; + case ISD::SETUO: + Opc = Alpha::CMPTUN; break; }; - SDOperand tmp1 = Select(N->getOperand(0)), - tmp2 = Select(N->getOperand(1)); - SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64, - rev?tmp2:tmp1, - rev?tmp1:tmp2); - if (isNE) - cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp, + SDValue tmp1 = N->getOperand(rev?1:0); + SDValue tmp2 = N->getOperand(rev?0:1); + AddToISelQueue(tmp1); + AddToISelQueue(tmp2); + SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2); + if (inv) + cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0), CurDAG->getRegister(Alpha::F31, MVT::f64)); - - SDOperand LD; - if (AlphaLowering.hasITOF()) { - LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp); - } else { - int FrameIdx = - CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); - SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); - SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other, - cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)); - LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, - CurDAG->getRegister(Alpha::R31, MVT::i64), - ST); + switch(CC) { + case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: + case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: + { + SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, + tmp1, tmp2); + cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64, + SDValue(cmp2, 0), SDValue(cmp, 0)); + break; + } + default: break; } - SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, - CurDAG->getRegister(Alpha::R31, MVT::i64), - LD); - return FP; + + SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0)); + return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, + CurDAG->getRegister(Alpha::R31, MVT::i64), + SDValue(LD,0)); } break; case ISD::SELECT: - if (MVT::isFloatingPoint(N->getValueType(0)) && - (N->getOperand(0).getOpcode() != ISD::SETCC || - !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) { + if (N->getValueType(0).isFloatingPoint() && + (N->getOperand(0).getOpcode() != ISD::SETCC || + !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) { //This should be the condition not covered by the Patterns //FIXME: Don't have SelectCode die, but rather return something testable // so that things like this can be caught in fall though code //move int to fp bool isDouble = N->getValueType(0) == MVT::f64; - SDOperand LD, - cond = Select(N->getOperand(0)), - TV = Select(N->getOperand(1)), - FV = Select(N->getOperand(2)); + SDValue cond = N->getOperand(0); + SDValue TV = N->getOperand(1); + SDValue FV = N->getOperand(2); + AddToISelQueue(cond); + AddToISelQueue(TV); + AddToISelQueue(FV); - if (AlphaLowering.hasITOF()) { - LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond); - } else { - int FrameIdx = - CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); - SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); - SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other, - cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64)); - LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, - CurDAG->getRegister(Alpha::R31, MVT::i64), - ST); + SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond); + return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, + MVT::f64, FV, TV, SDValue(LD,0)); + } + break; + + case ISD::AND: { + ConstantSDNode* SC = NULL; + ConstantSDNode* MC = NULL; + if (N->getOperand(0).getOpcode() == ISD::SRL && + (MC = dyn_cast(N->getOperand(1))) && + (SC = dyn_cast(N->getOperand(0).getOperand(1)))) { + uint64_t sval = SC->getValue(); + uint64_t mval = MC->getValue(); + // If the result is a zap, let the autogened stuff handle it. + if (get_zapImm(N->getOperand(0), mval)) + break; + // given mask X, and shift S, we want to see if there is any zap in the + // mask if we play around with the botton S bits + uint64_t dontcare = (~0ULL) >> (64 - sval); + uint64_t mask = mval << sval; + + if (get_zapImm(mask | dontcare)) + mask = mask | dontcare; + + if (get_zapImm(mask)) { + AddToISelQueue(N->getOperand(0).getOperand(0)); + SDValue Z = + SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64, + N->getOperand(0).getOperand(0), + getI64Imm(get_zapImm(mask))), 0); + return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z, + getI64Imm(sval)); } - SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, - MVT::f64, FV, TV, LD); - return FP; } break; + } } return SelectCode(Op); } -SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { +void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { //TODO: add flag stuff to prevent nondeturministic breakage! SDNode *N = Op.Val; - SDOperand Chain = Select(N->getOperand(0)); - SDOperand Addr = Select(N->getOperand(1)); - SDOperand InFlag; // Null incoming flag value. + SDValue Chain = N->getOperand(0); + SDValue Addr = N->getOperand(1); + SDValue InFlag(0,0); // Null incoming flag value. + AddToISelQueue(Chain); - std::vector CallOperands; - std::vector TypeOperands; + std::vector CallOperands; + std::vector TypeOperands; //grab the arguments for(int i = 2, e = N->getNumOperands(); i < e; ++i) { TypeOperands.push_back(N->getOperand(i).getValueType()); - CallOperands.push_back(Select(N->getOperand(i))); + AddToISelQueue(N->getOperand(i)); + CallOperands.push_back(N->getOperand(i)); } int count = N->getNumOperands() - 2; @@ -379,7 +485,7 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { for (int i = 6; i < count; ++i) { unsigned Opc = Alpha::WTF; - if (MVT::isInteger(TypeOperands[i])) { + if (TypeOperands[i].isInteger()) { Opc = Alpha::STQ; } else if (TypeOperands[i] == MVT::f32) { Opc = Alpha::STS; @@ -387,13 +493,14 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { Opc = Alpha::STT; } else assert(0 && "Unknown operand"); - Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i], - getI64Imm((i - 6) * 8), - CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), - Chain); + + SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), + CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64), + Chain }; + Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0); } for (int i = 0; i < std::min(6, count); ++i) { - if (MVT::isInteger(TypeOperands[i])) { + if (TypeOperands[i].isInteger()) { Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) { @@ -403,18 +510,26 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { assert(0 && "Unknown operand"); } - - Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); - InFlag = Chain.getValue(1); // Finally, once everything is in registers to pass to the call, emit the // call itself. - Chain = CurDAG->getTargetNode(Alpha::JSRDAG, MVT::Other, MVT::Flag, - Chain, InFlag ); + if (Addr.getOpcode() == AlphaISD::GPRelLo) { + SDValue GOT = getGlobalBaseReg(); + Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag); + InFlag = Chain.getValue(1); + Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag, + Addr.getOperand(0), Chain, InFlag), 0); + } else { + AddToISelQueue(Addr); + Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag); + InFlag = Chain.getValue(1); + Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag, + Chain, InFlag), 0); + } InFlag = Chain.getValue(1); - std::vector CallResults; + std::vector CallResults; - switch (N->getValueType(0)) { + switch (N->getValueType(0).getSimpleVT()) { default: assert(0 && "Unexpected ret value!"); case MVT::Other: break; case MVT::i64: @@ -433,14 +548,13 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { CallResults.push_back(Chain); for (unsigned i = 0, e = CallResults.size(); i != e; ++i) - CodeGenMap[Op.getValue(i)] = CallResults[i]; - return CallResults[Op.ResNo]; + ReplaceUses(Op.getValue(i), CallResults[i]); } /// createAlphaISelDag - This pass converts a legalized DAG into a /// Alpha-specific DAG, ready for instruction scheduling. /// -FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) { +FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) { return new AlphaDAGToDAGISel(TM); }