X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMSubtarget.cpp;h=f84e7a28d36b55e90e399c40a05ea49d586083b5;hb=0b8c9a80f20772c3793201ab5b251d3520b9cea3;hp=a7010c5be1bf218dbb71ea9f20b91721353d323e;hpb=385e930d55f3ecd3c9538823dfa5896a12461845;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index a7010c5be1b..f84e7a28d36 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -1,4 +1,4 @@ -//===-- ARMSubtarget.cpp - ARM Subtarget Information ------------*- C++ -*-===// +//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===// // // The LLVM Compiler Infrastructure // @@ -12,15 +12,14 @@ //===----------------------------------------------------------------------===// #include "ARMSubtarget.h" +#include "ARMBaseInstrInfo.h" #include "ARMBaseRegisterInfo.h" -#include "llvm/GlobalValue.h" -#include "llvm/Target/TargetSubtargetInfo.h" +#include "llvm/IR/GlobalValue.h" #include "llvm/Support/CommandLine.h" -#include "llvm/ADT/SmallVector.h" +#include "llvm/Target/TargetInstrInfo.h" -#define GET_SUBTARGETINFO_CTOR -#define GET_SUBTARGETINFO_MC_DESC #define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR #include "ARMGenSubtargetInfo.inc" using namespace llvm; @@ -32,33 +31,51 @@ ReserveR9("arm-reserve-r9", cl::Hidden, static cl::opt DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden); +static cl::opt +UseFusedMulOps("arm-use-mulops", + cl::init(true), cl::Hidden); + static cl::opt StrictAlign("arm-strict-align", cl::Hidden, cl::desc("Disallow all unaligned memory accesses")); ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool isT) - : ARMGenSubtargetInfo() - , ARMArchVersion(V4) + const std::string &FS) + : ARMGenSubtargetInfo(TT, CPU, FS) , ARMProcFamily(Others) - , ARMFPUType(None) + , HasV4TOps(false) + , HasV5TOps(false) + , HasV5TEOps(false) + , HasV6Ops(false) + , HasV6T2Ops(false) + , HasV7Ops(false) + , HasVFPv2(false) + , HasVFPv3(false) + , HasVFPv4(false) + , HasNEON(false) , UseNEONForSinglePrecisionFP(false) + , UseMulOps(UseFusedMulOps) , SlowFPVMLx(false) , HasVMLxForwarding(false) , SlowFPBrcc(false) - , IsThumb(isT) - , ThumbMode(Thumb1) + , InThumbMode(false) + , HasThumb2(false) + , IsMClass(false) , NoARM(false) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) , UseMovt(false) + , SupportsTailCall(false) , HasFP16(false) , HasD16(false) , HasHardwareDivide(false) + , HasHardwareDivideInARM(false) , HasT2ExtractPack(false) , HasDataBarrier(false) , Pref32BitThumb(false) , AvoidCPSRPartialUpdate(false) + , AvoidMOVsShifterOperand(false) + , HasRAS(false) , HasMPExtension(false) , FPOnlySP(false) , AllowsUnalignedMem(false) @@ -68,99 +85,46 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, , TargetTriple(TT) , TargetABI(ARM_ABI_APCS) { // Determine default and user specified characteristics - - // When no arch is specified either by CPU or by attributes, make the default - // ARMv4T. - const char *ARMArchFeature = ""; if (CPUString.empty()) CPUString = "generic"; - if (CPUString == "generic" && (FS.empty() || FS == "generic")) { - ARMArchVersion = V4T; - ARMArchFeature = "+v4t"; - } - - // Set the boolean corresponding to the current target triple, or the default - // if one cannot be determined, to true. - unsigned Len = TT.length(); - unsigned Idx = 0; - - if (Len >= 5 && TT.substr(0, 4) == "armv") - Idx = 4; - else if (Len >= 6 && TT.substr(0, 5) == "thumb") { - IsThumb = true; - if (Len >= 7 && TT[5] == 'v') - Idx = 6; - } - if (Idx) { - unsigned SubVer = TT[Idx]; - if (SubVer >= '7' && SubVer <= '9') { - ARMArchVersion = V7A; - ARMArchFeature = "+v7a"; - if (Len >= Idx+2 && TT[Idx+1] == 'm') { - ARMArchVersion = V7M; - ARMArchFeature = "+v7m"; - } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { - ARMArchVersion = V7EM; - ARMArchFeature = "+v7em"; - } - } else if (SubVer == '6') { - ARMArchVersion = V6; - ARMArchFeature = "+v6"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { - ARMArchVersion = V6T2; - ARMArchFeature = "+v6t2"; - } - } else if (SubVer == '5') { - ARMArchVersion = V5T; - ARMArchFeature = "+v5t"; - if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { - ARMArchVersion = V5TE; - ARMArchFeature = "+v5te"; - } - } else if (SubVer == '4') { - if (Len >= Idx+2 && TT[Idx+1] == 't') { - ARMArchVersion = V4T; - ARMArchFeature = "+v4t"; - } else { - ARMArchVersion = V4; - ARMArchFeature = ""; - } - } - } - - if (TT.find("eabi") != std::string::npos) - TargetABI = ARM_ABI_AAPCS; // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. - std::string FSWithArch = std::string(ARMArchFeature); - if (FSWithArch.empty()) - FSWithArch = FS; - else if (!FS.empty()) - FSWithArch = FSWithArch + "," + FS; - ParseSubtargetFeatures(FSWithArch, CPUString); + std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString); + if (!FS.empty()) { + if (!ArchFS.empty()) + ArchFS = ArchFS + "," + FS; + else + ArchFS = FS; + } + ParseSubtargetFeatures(CPUString, ArchFS); + + // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a + // ARM version or CPU and then remove this. + if (!HasV6T2Ops && hasThumb2()) + HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; + + // Keep a pointer to static instruction cost data for the specified CPU. + SchedModel = getSchedModelForCPU(CPUString); // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); - // After parsing Itineraries, set ItinData.IssueWidth. - computeIssueWidth(); - - // Thumb2 implies at least V6T2. - if (ARMArchVersion >= V6T2) - ThumbMode = Thumb2; - else if (ThumbMode >= Thumb2) - ARMArchVersion = V6T2; + if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass())) + // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g. + // Darwin-EABI conforms to AACPS but not the rest of EABI. + TargetABI = ARM_ABI_AAPCS; if (isAAPCS_ABI()) stackAlignment = 8; - if (!isTargetDarwin()) + if (!isTargetIOS()) UseMovt = hasV6T2Ops(); else { - IsR9Reserved = ReserveR9 | (ARMArchVersion < V6); + IsR9Reserved = ReserveR9 | !HasV6Ops; UseMovt = DarwinUseMOVT && hasV6T2Ops(); + SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0); } if (!isThumb() || hasThumb2()) @@ -226,31 +190,7 @@ ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV, } unsigned ARMSubtarget::getMispredictionPenalty() const { - // If we have a reasonable estimate of the pipeline depth, then we can - // estimate the penalty of a misprediction based on that. - if (isCortexA8()) - return 13; - else if (isCortexA9()) - return 8; - - // Otherwise, just return a sensible default. - return 10; -} - -void ARMSubtarget::computeIssueWidth() { - unsigned allStage1Units = 0; - for (const InstrItinerary *itin = InstrItins.Itineraries; - itin->FirstStage != ~0U; ++itin) { - const InstrStage *IS = InstrItins.Stages + itin->FirstStage; - allStage1Units |= IS->getUnits(); - } - InstrItins.IssueWidth = 0; - while (allStage1Units) { - ++InstrItins.IssueWidth; - // clear the lowest bit - allStage1Units ^= allStage1Units & ~(allStage1Units - 1); - } - assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); + return SchedModel->MispredictPenalty; } bool ARMSubtarget::enablePostRAScheduler(