X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMInstrInfo.td;h=a5719e4f131f38ca43ead7a09e193d81bdbd003c;hb=475871a144eb604ddaf37503397ba0941442e5fb;hp=f252f605cc474c706c16f72ed0bb4096e1051d27;hpb=c01c87c8baa5e7dd1e11a3bacbd3b4e94ebe6c5d;p=oota-llvm.git diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index f252f605cc4..a5719e4f131 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1,9 +1,8 @@ -//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===// +//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// // // The LLVM Compiler Infrastructure // -// This file was developed by the "Instituto Nokia de Tecnologia" and -// is distributed under the University of Illinois Open Source +// This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// @@ -12,315 +11,1445 @@ // //===----------------------------------------------------------------------===// -// Address operands -def op_addr_mode1 : Operand { - let PrintMethod = "printAddrMode1"; - let NumMIOperands = 3; - let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm); +//===----------------------------------------------------------------------===// +// ARM specific DAG Nodes. +// + +// Type profiles. +def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; +def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; + +def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; + +def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; + +def SDT_ARMCMov : SDTypeProfile<1, 3, + [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, + SDTCisVT<3, i32>]>; + +def SDT_ARMBrcond : SDTypeProfile<0, 2, + [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; + +def SDT_ARMBrJT : SDTypeProfile<0, 3, + [SDTCisPtrTy<0>, SDTCisVT<1, i32>, + SDTCisVT<2, i32>]>; + +def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; + +def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, + SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; + +def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; + +// Node definitions. +def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; +def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; + +def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, + [SDNPHasChain, SDNPOutFlag]>; +def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; + +def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; + +def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInFlag]>; + +def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, + [SDNPInFlag]>; +def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, + [SDNPInFlag]>; + +def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, + [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; + +def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, + [SDNPHasChain]>; + +def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, + [SDNPOutFlag]>; + +def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp, + [SDNPOutFlag]>; + +def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; + +def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; +def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; +def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; + +def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; + +//===----------------------------------------------------------------------===// +// ARM Instruction Predicate Definitions. +// +def HasV5T : Predicate<"Subtarget->hasV5TOps()">; +def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; +def HasV6 : Predicate<"Subtarget->hasV6Ops()">; +def IsThumb : Predicate<"Subtarget->isThumb()">; +def IsARM : Predicate<"!Subtarget->isThumb()">; + +//===----------------------------------------------------------------------===// +// ARM Flag Definitions. + +class RegConstraint { + string Constraints = C; } -def op_addr_mode5 : Operand { - let PrintMethod = "printAddrMode5"; - let NumMIOperands = 2; - let MIOperandInfo = (ops ptr_rc, i32imm); +//===----------------------------------------------------------------------===// +// ARM specific transformation functions and pattern fragments. +// + +// so_imm_XFORM - Return a so_imm value packed into the format described for +// so_imm def below. +def so_imm_XFORM : SDNodeXFormgetTargetConstant(ARM_AM::getSOImmVal(N->getValue()), + MVT::i32); +}]>; + +// so_imm_neg_XFORM - Return a so_imm value packed into the format described for +// so_imm_neg def below. +def so_imm_neg_XFORM : SDNodeXFormgetTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()), + MVT::i32); +}]>; + +// so_imm_not_XFORM - Return a so_imm value packed into the format described for +// so_imm_not def below. +def so_imm_not_XFORM : SDNodeXFormgetTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()), + MVT::i32); +}]>; + +// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. +def rot_imm : PatLeaf<(i32 imm), [{ + int32_t v = (int32_t)N->getValue(); + return v == 8 || v == 16 || v == 24; +}]>; + +/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. +def imm1_15 : PatLeaf<(i32 imm), [{ + return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16; +}]>; + +/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. +def imm16_31 : PatLeaf<(i32 imm), [{ + return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32; +}]>; + +def so_imm_neg : + PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }], + so_imm_neg_XFORM>; + +def so_imm_not : + PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }], + so_imm_not_XFORM>; + +// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. +def sext_16_node : PatLeaf<(i32 GPR:$a), [{ + return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; +}]>; + + + +//===----------------------------------------------------------------------===// +// Operand Definitions. +// + +// Branch target. +def brtarget : Operand; + +// A list of registers separated by comma. Used by load/store multiple. +def reglist : Operand { + let PrintMethod = "printRegisterList"; } -def memri : Operand { - let PrintMethod = "printMemRegImm"; - let NumMIOperands = 2; - let MIOperandInfo = (ops i32imm, ptr_rc); +// An operand for the CONSTPOOL_ENTRY pseudo-instruction. +def cpinst_operand : Operand { + let PrintMethod = "printCPInstOperand"; } -// Define ARM specific addressing mode. -//Addressing Mode 1: data processing operands -def addr_mode1 : ComplexPattern; +def jtblock_operand : Operand { + let PrintMethod = "printJTBlockOperand"; +} -//Addressing Mode 5: VFP load/store -def addr_mode5 : ComplexPattern; +// Local PC labels. +def pclabel : Operand { + let PrintMethod = "printPCLabel"; +} -//register plus/minus 12 bit offset -def iaddr : ComplexPattern; -//register plus scaled register -//def raddr : ComplexPattern; +// shifter_operand operands: so_reg and so_imm. +def so_reg : Operand, // reg reg imm + ComplexPattern { + let PrintMethod = "printSORegOperand"; + let MIOperandInfo = (ops GPR, GPR, i32imm); +} -//===----------------------------------------------------------------------===// -// Instruction Class Templates -//===----------------------------------------------------------------------===// -class InstARM pattern> : Instruction { - let Namespace = "ARM"; +// so_imm - Match a 32-bit shifter_operand immediate operand, which is an +// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are +// represented in the imm field in the same 12-bit form that they are encoded +// into so_imm instructions: the 8-bit immediate is the least significant bits +// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. +def so_imm : Operand, + PatLeaf<(imm), + [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }], + so_imm_XFORM> { + let PrintMethod = "printSOImmOperand"; +} - dag OperandList = ops; - let AsmString = asmstr; - let Pattern = pattern; +// Break so_imm's up into two pieces. This handles immediates with up to 16 +// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to +// get the first/second pieces. +def so_imm2part : Operand, + PatLeaf<(imm), + [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> { + let PrintMethod = "printSOImm2PartOperand"; +} + +def so_imm2part_1 : SDNodeXFormgetValue()); + return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); +}]>; + +def so_imm2part_2 : SDNodeXFormgetValue()); + return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); +}]>; + + +// Define ARM specific addressing modes. + +// addrmode2 := reg +/- reg shop imm +// addrmode2 := reg +/- imm12 +// +def addrmode2 : Operand, + ComplexPattern { + let PrintMethod = "printAddrMode2Operand"; + let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); +} + +def am2offset : Operand, + ComplexPattern { + let PrintMethod = "printAddrMode2OffsetOperand"; + let MIOperandInfo = (ops GPR, i32imm); +} + +// addrmode3 := reg +/- reg +// addrmode3 := reg +/- imm8 +// +def addrmode3 : Operand, + ComplexPattern { + let PrintMethod = "printAddrMode3Operand"; + let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } -class IntBinOp : - InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - !strconcat(OpcStr, " $dst, $a, $b"), - [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>; +def am3offset : Operand, + ComplexPattern { + let PrintMethod = "printAddrMode3OffsetOperand"; + let MIOperandInfo = (ops GPR, i32imm); +} + +// addrmode4 := reg, +// +def addrmode4 : Operand, + ComplexPattern { + let PrintMethod = "printAddrMode4Operand"; + let MIOperandInfo = (ops GPR, i32imm); +} + +// addrmode5 := reg +/- imm8*4 +// +def addrmode5 : Operand, + ComplexPattern { + let PrintMethod = "printAddrMode5Operand"; + let MIOperandInfo = (ops GPR, i32imm); +} -class FPBinOp : - InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b), - !strconcat(OpcStr, " $dst, $a, $b"), - [(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>; +// addrmodepc := pc + reg +// +def addrmodepc : Operand, + ComplexPattern { + let PrintMethod = "printAddrModePCOperand"; + let MIOperandInfo = (ops GPR, i32imm); +} -class DFPBinOp : - InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b), - !strconcat(OpcStr, " $dst, $a, $b"), - [(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>; +// ARM Predicate operand. Default to 14 = always (AL). Second part is CC +// register whose default is 0 (no register). +def pred : PredicateOperand { + let PrintMethod = "printPredicateOperand"; +} -class Addr1BinOp : - InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b), - !strconcat(OpcStr, " $dst, $a, $b"), - [(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>; +// Conditional code result for instructions whose 's' bit is set, e.g. subs. +// +def cc_out : OptionalDefOperand { + let PrintMethod = "printSBitModifierOperand"; +} //===----------------------------------------------------------------------===// -// Instructions +// ARM Instruction flags. These need to match ARMInstrInfo.h. +// + +// Addressing mode. +class AddrMode val> { + bits<4> Value = val; +} +def AddrModeNone : AddrMode<0>; +def AddrMode1 : AddrMode<1>; +def AddrMode2 : AddrMode<2>; +def AddrMode3 : AddrMode<3>; +def AddrMode4 : AddrMode<4>; +def AddrMode5 : AddrMode<5>; +def AddrModeT1 : AddrMode<6>; +def AddrModeT2 : AddrMode<7>; +def AddrModeT4 : AddrMode<8>; +def AddrModeTs : AddrMode<9>; + +// Instruction size. +class SizeFlagVal val> { + bits<3> Value = val; +} +def SizeInvalid : SizeFlagVal<0>; // Unset. +def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. +def Size8Bytes : SizeFlagVal<2>; +def Size4Bytes : SizeFlagVal<3>; +def Size2Bytes : SizeFlagVal<4>; + +// Load / store index mode. +class IndexMode val> { + bits<2> Value = val; +} +def IndexModeNone : IndexMode<0>; +def IndexModePre : IndexMode<1>; +def IndexModePost : IndexMode<2>; + //===----------------------------------------------------------------------===// +// ARM Instruction Format Definitions. +// -def brtarget : Operand; +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format val> { + bits<5> Value = val; +} -// Operand for printing out a condition code. -let PrintMethod = "printCCOperand" in - def CCOp : Operand; +def Pseudo : Format<1>; +def MulFrm : Format<2>; +def MulSMLAW : Format<3>; +def MulSMULW : Format<4>; +def MulSMLA : Format<5>; +def MulSMUL : Format<6>; +def Branch : Format<7>; +def BranchMisc : Format<8>; + +def DPRdIm : Format<9>; +def DPRdReg : Format<10>; +def DPRdSoReg : Format<11>; +def DPRdMisc : Format<12>; +def DPRnIm : Format<13>; +def DPRnReg : Format<14>; +def DPRnSoReg : Format<15>; +def DPRIm : Format<16>; +def DPRReg : Format<17>; +def DPRSoReg : Format<18>; +def DPRImS : Format<19>; +def DPRRegS : Format<20>; +def DPRSoRegS : Format<21>; + +def LdFrm : Format<22>; +def StFrm : Format<23>; + +def ArithMisc : Format<24>; +def ThumbFrm : Format<25>; +def VFPFrm : Format<26>; -def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>; -def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, - [SDNPHasChain, SDNPOutFlag]>; -def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, - [SDNPHasChain, SDNPOutFlag]>; -def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; -def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, - [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; -def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet, - [SDNPHasChain, SDNPOptInFlag]>; -def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>; -def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>; +//===----------------------------------------------------------------------===// -def SDTarmfmstat : SDTypeProfile<0, 0, []>; -def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>; +// ARM Instruction templates. +// -def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; -def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>; +// ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode. +class ARMPat : Pat { + list Predicates = [IsARM]; +} +class ARMV5TEPat : Pat { + list Predicates = [IsARM, HasV5TE]; +} +class ARMV6Pat : Pat { + list Predicates = [IsARM, HasV6]; +} -def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; -def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>; +class InstARM opcod, AddrMode am, SizeFlagVal sz, IndexMode im, + Format f, string cstr> + : Instruction { + let Namespace = "ARM"; -def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>; -def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>; -def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>; -def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>; -def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>; -def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>; -def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>; -def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>; + bits<4> Opcode = opcod; + AddrMode AM = am; + bits<4> AddrModeBits = AM.Value; + + SizeFlagVal SZ = sz; + bits<3> SizeFlag = SZ.Value; + + IndexMode IM = im; + bits<2> IndexModeBits = IM.Value; + + Format F = f; + bits<5> Form = F.Value; + + let Constraints = cstr; +} -def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>; -def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd, - [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +class PseudoInst pattern> + : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { + let OutOperandList = oops; + let InOperandList = iops; + let AsmString = asm; + let Pattern = pattern; +} -def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>; -def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>; +// Almost all ARM instructions are predicable. +class I opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string opc, string asm, string cstr, + list pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p)); + let AsmString = !strconcat(opc, !strconcat("${p}", asm)); + let Pattern = pattern; + list Predicates = [IsARM]; +} -def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt), - "!ADJCALLSTACKUP $amt", - [(callseq_end imm:$amt)]>, Imp<[R13],[R13]>; +// Same as I except it can optionally modify CPSR. Note it's modeled as +// an input operand since by default it's a zero register. It will +// become an implicit def once it's "flipped". +class sI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string opc, string asm, string cstr, + list pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); + let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); + let Pattern = pattern; + list Predicates = [IsARM]; +} -def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt), - "!ADJCALLSTACKDOWN $amt", - [(callseq_start imm:$amt)]>, Imp<[R13],[R13]>; +class AI opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AsI opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : sI; +class AI1 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AsI1 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : sI; +class AI2 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AI3 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AI4 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; +class AI1x2 opcod, dag oops, dag iops, Format f, string opc, + string asm, list pattern> + : I; + +// Pre-indexed ops +class AI2pr opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; +class AI3pr opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; + +// Post-indexed ops +class AI2po opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; +class AI3po opcod, dag oops, dag iops, Format f, string opc, + string asm, string cstr, list pattern> + : I; + + +class BinOpFrag : PatFrag<(ops node:$LHS, node:$RHS), res>; +class UnOpFrag : PatFrag<(ops node:$Src), res>; + + +/// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a +/// binop that produces a value. +multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode> { + def ri : AsI1; + def rr : AsI1; + def rs : AsI1; +} -let isReturn = 1 in { - def bx: InstARM<(ops), "bx r14", [(retflag)]>; +/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the +/// instruction modifies the CSPR register. +let Defs = [CPSR] in { +multiclass ASI1_bin_s_irs opcod, string opc, PatFrag opnode> { + def ri : AI1; + def rr : AI1; + def rs : AI1; +} } -let noResults = 1, Defs = [R0, R1, R2, R3, R14] in { - def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>; +/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test +/// patterns. Similar to AsI1_bin_irs except the instruction does not produce +/// a explicit result, only implicitly set CPSR. +let Defs = [CPSR] in { +multiclass AI1_cmp_irs opcod, string opc, PatFrag opnode> { + def ri : AI1; + def rr : AI1; + def rs : AI1; +} } -def ldr : InstARM<(ops IntRegs:$dst, memri:$addr), - "ldr $dst, $addr", - [(set IntRegs:$dst, (load iaddr:$addr))]>; +/// AI_unary_rrot - A unary operation with two forms: one whose operand is a +/// register and one whose operand is a register rotated by 8/16/24. +multiclass AI_unary_rrot opcod, string opc, PatFrag opnode> { + def r : AI, Requires<[IsARM, HasV6]>; + def r_rot : AI, + Requires<[IsARM, HasV6]>; +} -def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrb $dst, [$addr]", - [(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>; +/// AI_bin_rrot - A binary operation with two forms: one whose operand is a +/// register and one whose operand is a register rotated by 8/16/24. +multiclass AI_bin_rrot opcod, string opc, PatFrag opnode> { + def rr : AI, + Requires<[IsARM, HasV6]>; + def rr_rot : AI, + Requires<[IsARM, HasV6]>; +} -def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrsb $dst, [$addr]", - [(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>; +// Special cases. +class XI opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, + IndexMode im, Format f, string asm, string cstr, list pattern> + : InstARM { + let OutOperandList = oops; + let InOperandList = iops; + let AsmString = asm; + let Pattern = pattern; + list Predicates = [IsARM]; +} + +class AXI opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI1 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI2 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI3 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; +class AXI4 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; + +class AXIx2 opcod, dag oops, dag iops, Format f, string asm, + list pattern> + : XI; + +// BR_JT instructions +class JTI opcod, dag oops, dag iops, string asm, list pattern> + : XI; +class JTI1 opcod, dag oops, dag iops, string asm, list pattern> + : XI; +class JTI2 opcod, dag oops, dag iops, string asm, list pattern> + : XI; + +/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and +/// setting carry bit. But it can optionally set CPSR. +let Uses = [CPSR] in { +multiclass AsXI1_bin_c_irs opcod, string opc, PatFrag opnode> { + def ri : AXI1; + def rr : AXI1; + def rs : AXI1; +} +} -def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrh $dst, [$addr]", - [(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>; +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// -def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr), - "ldrsh $dst, [$addr]", - [(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>; +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +// -def str : InstARM<(ops IntRegs:$src, memri:$addr), - "str $src, $addr", - [(store IntRegs:$src, iaddr:$addr)]>; +/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in +/// the function. The first operand is the ID# for this instruction, the second +/// is the index into the MachineConstantPool that this is, the third is the +/// size in bytes of this constant pool entry. +let isNotDuplicable = 1 in +def CONSTPOOL_ENTRY : +PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, + i32imm:$size), + "${instid:label} ${cpidx:cpentry}", []>; + +let Defs = [SP], Uses = [SP] in { +def ADJCALLSTACKUP : +PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), + "@ ADJCALLSTACKUP $amt1", + [(ARMcallseq_end imm:$amt1, imm:$amt2)]>; + +def ADJCALLSTACKDOWN : +PseudoInst<(outs), (ins i32imm:$amt, pred:$p), + "@ ADJCALLSTACKDOWN $amt", + [(ARMcallseq_start imm:$amt)]>; +} -def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src), - "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>; +def DWARF_LOC : +PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), + ".loc $file, $line, $col", + [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; + +let isNotDuplicable = 1 in { +def PICADD : AXI1<0x0, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), + Pseudo, "$cp:\n\tadd$p $dst, pc, $a", + [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; + +let AddedComplexity = 10 in { +let isSimpleLoad = 1 in +def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", + [(set GPR:$dst, (load addrmodepc:$addr))]>; + +def PICLDZH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", + [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; + +def PICLDZB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", + [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; + +def PICLDH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", + [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>; + +def PICLDB : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", + [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>; + +def PICLDSH : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr", + [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; + +def PICLDSB : AXI3<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", + [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; +} +let AddedComplexity = 10 in { +def PICSTR : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tstr$p $src, $addr", + [(store GPR:$src, addrmodepc:$addr)]>; + +def PICSTRH : AXI3<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr", + [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; + +def PICSTRB : AXI2<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), + Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr", + [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; +} +} -def ADD : Addr1BinOp<"add", add>; -def ADCS : Addr1BinOp<"adcs", adde>; -def ADDS : Addr1BinOp<"adds", addc>; +//===----------------------------------------------------------------------===// +// Control Flow Instructions. +// -// "LEA" forms of add -def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr), - "add $dst, ${addr:arith}", - [(set IntRegs:$dst, iaddr:$addr)]>; +let isReturn = 1, isTerminator = 1 in + def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>; + +// FIXME: remove when we have a way to marking a MI with these properties. +// FIXME: $dst1 should be a def. But the extra ops must be in the end of the +// operand list. +let isReturn = 1, isTerminator = 1 in + def LDM_RET : AXI4<0x0, (outs), + (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), + LdFrm, "ldm${p}${addr:submode} $addr, $dst1", + []>; + +let isCall = 1, + Defs = [R0, R1, R2, R3, R12, LR, + D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { + def BL : AXI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, + "bl ${func:call}", + [(ARMcall tglobaladdr:$func)]>; + + def BL_pred : AI<0xB, (outs), (ins i32imm:$func, variable_ops), + Branch, "bl", " ${func:call}", + [(ARMcall_pred tglobaladdr:$func)]>; + + // ARMv5T and above + def BLX : AXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc, + "blx $func", + [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>; + let Uses = [LR] in { + // ARMv4T + def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops), + BranchMisc, "mov lr, pc\n\tbx $func", + [(ARMcall_nolink GPR:$func)]>; + } +} +let isBranch = 1, isTerminator = 1 in { + // B is "predicable" since it can be xformed into a Bcc. + let isBarrier = 1 in { + let isPredicable = 1 in + def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target", + [(br bb:$target)]>; + + let isNotDuplicable = 1, isIndirectBranch = 1 in { + def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), + "mov pc, $target \n$jt", + [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; + def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), + "ldr pc, $target \n$jt", + [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, + imm:$id)]>; + def BR_JTadd : JTI1<0x0, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, + i32imm:$id), + "add pc, $target, $idx \n$jt", + [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, + imm:$id)]>; + } + } + + // FIXME: should be able to write a pattern for ARMBrcond, but can't use + // a two-value operand where a dag node expects two operands. :( + def Bcc : AI<0xA, (outs), (ins brtarget:$target), Branch, + "b", " $target", + [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; +} -def SUB : Addr1BinOp<"sub", sub>; -def SBCS : Addr1BinOp<"sbcs", sube>; -def SUBS : Addr1BinOp<"subs", subc>; -def AND : Addr1BinOp<"and", and>; -def EOR : Addr1BinOp<"eor", xor>; -def ORR : Addr1BinOp<"orr", or>; +//===----------------------------------------------------------------------===// +// Load / store Instructions. +// -let isTwoAddress = 1 in { - def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, - op_addr_mode1:$true, CCOp:$cc), - "mov$cc $dst, $true", - [(set IntRegs:$dst, (armselect addr_mode1:$true, - IntRegs:$false, imm:$cc))]>; +// Load +let isSimpleLoad = 1 in +def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, + "ldr", " $dst, $addr", + [(set GPR:$dst, (load addrmode2:$addr))]>; + +// Special LDR for loads from non-pc-relative constpools. +let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in +def LDRcp : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, + "ldr", " $dst, $addr", []>; + +// Loads with zero extension +def LDRH : AI3<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, + "ldr", "h $dst, $addr", + [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; + +def LDRB : AI2<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, + "ldr", "b $dst, $addr", + [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; + +// Loads with sign extension +def LDRSH : AI3<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, + "ldr", "sh $dst, $addr", + [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; + +def LDRSB : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, + "ldr", "sb $dst, $addr", + [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; + +let mayLoad = 1 in { +// Load doubleword +def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm, + "ldr", "d $dst, $addr", + []>, Requires<[IsARM, HasV5T]>; + +// Indexed loads +def LDR_PRE : AI2pr<0x0, (outs GPR:$dst, GPR:$base_wb), + (ins addrmode2:$addr), LdFrm, + "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; + +def LDR_POST : AI2po<0x0, (outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base, am2offset:$offset), LdFrm, + "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; + +def LDRH_PRE : AI3pr<0xB, (outs GPR:$dst, GPR:$base_wb), + (ins addrmode3:$addr), LdFrm, + "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; + +def LDRH_POST : AI3po<0xB, (outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am3offset:$offset), LdFrm, + "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; + +def LDRB_PRE : AI2pr<0x1, (outs GPR:$dst, GPR:$base_wb), + (ins addrmode2:$addr), LdFrm, + "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; + +def LDRB_POST : AI2po<0x1, (outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am2offset:$offset), LdFrm, + "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; + +def LDRSH_PRE : AI3pr<0xE, (outs GPR:$dst, GPR:$base_wb), + (ins addrmode3:$addr), LdFrm, + "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; + +def LDRSH_POST: AI3po<0xE, (outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am3offset:$offset), LdFrm, + "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; + +def LDRSB_PRE : AI3pr<0xD, (outs GPR:$dst, GPR:$base_wb), + (ins addrmode3:$addr), LdFrm, + "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; + +def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), + (ins GPR:$base,am3offset:$offset), LdFrm, + "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; } -def MUL : IntBinOp<"mul", mul>; +// Store +def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, + "str", " $src, $addr", + [(store GPR:$src, addrmode2:$addr)]>; + +// Stores with truncate +def STRH : AI3<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, + "str", "h $src, $addr", + [(truncstorei16 GPR:$src, addrmode3:$addr)]>; + +def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, + "str", "b $src, $addr", + [(truncstorei8 GPR:$src, addrmode2:$addr)]>; + +// Store doubleword +let mayStore = 1 in +def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm, + "str", "d $src, $addr", + []>, Requires<[IsARM, HasV5T]>; + +// Indexed stores +def STR_PRE : AI2pr<0x0, (outs GPR:$base_wb), + (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, + "str", " $src, [$base, $offset]!", "$base = $base_wb", + [(set GPR:$base_wb, + (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; + +def STR_POST : AI2po<0x0, (outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + "str", " $src, [$base], $offset", "$base = $base_wb", + [(set GPR:$base_wb, + (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; + +def STRH_PRE : AI3pr<0xB, (outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm, + "str", "h $src, [$base, $offset]!", "$base = $base_wb", + [(set GPR:$base_wb, + (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; + +def STRH_POST: AI3po<0xB, (outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am3offset:$offset), StFrm, + "str", "h $src, [$base], $offset", "$base = $base_wb", + [(set GPR:$base_wb, (post_truncsti16 GPR:$src, + GPR:$base, am3offset:$offset))]>; + +def STRB_PRE : AI2pr<0x1, (outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + "str", "b $src, [$base, $offset]!", "$base = $base_wb", + [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, + GPR:$base, am2offset:$offset))]>; + +def STRB_POST: AI2po<0x1, (outs GPR:$base_wb), + (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, + "str", "b $src, [$base], $offset", "$base = $base_wb", + [(set GPR:$base_wb, (post_truncsti8 GPR:$src, + GPR:$base, am2offset:$offset))]>; -let Defs = [R0] in { - def SMULL : IntBinOp<"smull r12,", mulhs>; - def UMULL : IntBinOp<"umull r12,", mulhu>; +//===----------------------------------------------------------------------===// +// Load / store multiple Instructions. +// + +// FIXME: $dst1 should be a def. +let mayLoad = 1 in +def LDM : AXI4<0x0, (outs), + (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), + LdFrm, "ldm${p}${addr:submode} $addr, $dst1", + []>; + +let mayStore = 1 in +def STM : AXI4<0x0, (outs), + (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), + StFrm, "stm${p}${addr:submode} $addr, $src1", + []>; + +//===----------------------------------------------------------------------===// +// Move Instructions. +// + +def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg, + "mov", " $dst, $src", []>; +def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg, + "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>; + +let isReMaterializable = 1 in +def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm, + "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>; + +def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, + "mov", " $dst, $src, rrx", + [(set GPR:$dst, (ARMrrx GPR:$src))]>; + +// These aren't really mov instructions, but we have to define them this way +// due to flag operands. + +let Defs = [CPSR] in { +def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, + "mov", "s $dst, $src, lsr #1", + [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; +def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc, + "mov", "s $dst, $src, asr #1", + [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; } -def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc), - "b$cc $dst", - [(armbr bb:$dst, imm:$cc)]>; +//===----------------------------------------------------------------------===// +// Extend Instructions. +// + +// Sign extenders + +defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; +defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; + +defm SXTAB : AI_bin_rrot<0x0, "sxtab", + BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; +defm SXTAH : AI_bin_rrot<0x0, "sxtah", + BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; + +// TODO: SXT(A){B|H}16 + +// Zero extenders -def b : InstARM<(ops brtarget:$dst), - "b $dst", - [(br bb:$dst)]>; +let AddedComplexity = 16 in { +defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; +defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; +defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; -def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b), - "cmp $a, $b", - [(armcmp IntRegs:$a, addr_mode1:$b)]>; +def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), + (UXTB16r_rot GPR:$Src, 24)>; +def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), + (UXTB16r_rot GPR:$Src, 8)>; -// Floating Point Compare -def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b), - "fcmps $a, $b", - [(armcmp FPRegs:$a, FPRegs:$b)]>; +defm UXTAB : AI_bin_rrot<0x0, "uxtab", + BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; +defm UXTAH : AI_bin_rrot<0x0, "uxtah", + BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; +} -def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b), - "fcmpd $a, $b", - [(armcmp DFPRegs:$a, DFPRegs:$b)]>; +// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. +//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>; -// Floating Point Copy -def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>; +// TODO: UXT(A){B|H}16 -def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>; +//===----------------------------------------------------------------------===// +// Arithmetic Instructions. +// + +defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>; +defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; + +// ADD and SUB with 's' bit set. +defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>; +defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; + +// FIXME: Do not allow ADC / SBC to be predicated for now. +defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>; +defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; + +// These don't define reg/reg forms, because they are handled above. +def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, + "rsb", " $dst, $a, $b", + [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; + +def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, + "rsb", " $dst, $a, $b", + [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; + +// RSB with 's' bit set. +let Defs = [CPSR] in { +def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm, + "rsb", "s $dst, $a, $b", + [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; +def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg, + "rsb", "s $dst, $a, $b", + [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; +} -// Floating Point Conversion -// We use bitconvert for moving the data between the register classes. -// The format conversion is done with ARM specific nodes +// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. +let Uses = [CPSR] in { +def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), + DPRIm, "rsc${s} $dst, $a, $b", + [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; +def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), + DPRSoReg, "rsc${s} $dst, $a, $b", + [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; +} -def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src), - "fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>; +// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. +def : ARMPat<(add GPR:$src, so_imm_neg:$imm), + (SUBri GPR:$src, so_imm_neg:$imm)>; -def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src), - "fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>; +//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), +// (SUBSri GPR:$src, so_imm_neg:$imm)>; +//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), +// (SBCri GPR:$src, so_imm_neg:$imm)>; -def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src), - "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>; +// Note: These are implemented in C++ code, because they have to generate +// ADD/SUBrs instructions, which use a complex pattern that a xform function +// cannot produce. +// (mul X, 2^n+1) -> (add (X << n), X) +// (mul X, 2^n-1) -> (rsb X, (X << n)) -def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1), - "fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>; -def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src), - "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>; +//===----------------------------------------------------------------------===// +// Bitwise Instructions. +// -def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src), - "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>; +defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>; +defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>; +defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>; +defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; -def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src), - "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>; +def MVNr : AsI<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg, + "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>; +def MVNs : AsI<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg, + "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>; +let isReMaterializable = 1 in +def MVNi : AsI<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm, + "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>; -def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src), - "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>; +def : ARMPat<(and GPR:$src, so_imm_not:$imm), + (BICri GPR:$src, so_imm_not:$imm)>; -def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src), - "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>; +//===----------------------------------------------------------------------===// +// Multiply Instructions. +// -def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src), - "ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>; +def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm, + "mul", " $dst, $a, $b", + [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; + +def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), + MulFrm, "mla", " $dst, $a, $b, $c", + [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; + +// Extra precision multiplies with low / high results +def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), + MulFrm, "smull", " $ldst, $hdst, $a, $b", []>; + +def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), + MulFrm, "umull", " $ldst, $hdst, $a, $b", []>; + +// Multiply + accumulate +def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), + MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>; + +def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), + MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>; + +def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm, + "umaal", " $ldst, $hdst, $a, $b", []>, + Requires<[IsARM, HasV6]>; + +// Most significant word multiply +def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm, + "smmul", " $dst, $a, $b", + [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, + Requires<[IsARM, HasV6]>; + +def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm, + "smmla", " $dst, $a, $b, $c", + [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, + Requires<[IsARM, HasV6]>; + + +def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm, + "smmls", " $dst, $a, $b, $c", + [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, + Requires<[IsARM, HasV6]>; + +multiclass AI_smul { + def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, + !strconcat(opc, "bb"), " $dst, $a, $b", + [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), + (sext_inreg GPR:$b, i16)))]>, + Requires<[IsARM, HasV5TE]>; + + def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, + !strconcat(opc, "bt"), " $dst, $a, $b", + [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), + (sra GPR:$b, 16)))]>, + Requires<[IsARM, HasV5TE]>; + + def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, + !strconcat(opc, "tb"), " $dst, $a, $b", + [(set GPR:$dst, (opnode (sra GPR:$a, 16), + (sext_inreg GPR:$b, i16)))]>, + Requires<[IsARM, HasV5TE]>; + + def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL, + !strconcat(opc, "tt"), " $dst, $a, $b", + [(set GPR:$dst, (opnode (sra GPR:$a, 16), + (sra GPR:$b, 16)))]>, + Requires<[IsARM, HasV5TE]>; + + def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW, + !strconcat(opc, "wb"), " $dst, $a, $b", + [(set GPR:$dst, (sra (opnode GPR:$a, + (sext_inreg GPR:$b, i16)), 16))]>, + Requires<[IsARM, HasV5TE]>; + + def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW, + !strconcat(opc, "wt"), " $dst, $a, $b", + [(set GPR:$dst, (sra (opnode GPR:$a, + (sra GPR:$b, 16)), 16))]>, + Requires<[IsARM, HasV5TE]>; +} -def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src), - "fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>; -def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src), - "ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>; +multiclass AI_smla { + def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, + !strconcat(opc, "bb"), " $dst, $a, $b, $acc", + [(set GPR:$dst, (add GPR:$acc, + (opnode (sext_inreg GPR:$a, i16), + (sext_inreg GPR:$b, i16))))]>, + Requires<[IsARM, HasV5TE]>; + + def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, + !strconcat(opc, "bt"), " $dst, $a, $b, $acc", + [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), + (sra GPR:$b, 16))))]>, + Requires<[IsARM, HasV5TE]>; + + def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, + !strconcat(opc, "tb"), " $dst, $a, $b, $acc", + [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), + (sext_inreg GPR:$b, i16))))]>, + Requires<[IsARM, HasV5TE]>; + + def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA, + !strconcat(opc, "tt"), " $dst, $a, $b, $acc", + [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), + (sra GPR:$b, 16))))]>, + Requires<[IsARM, HasV5TE]>; + + def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW, + !strconcat(opc, "wb"), " $dst, $a, $b, $acc", + [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, + (sext_inreg GPR:$b, i16)), 16)))]>, + Requires<[IsARM, HasV5TE]>; + + def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW, + !strconcat(opc, "wt"), " $dst, $a, $b, $acc", + [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, + (sra GPR:$b, 16)), 16)))]>, + Requires<[IsARM, HasV5TE]>; +} -def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src), - "fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; +defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; +defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; -def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src), - "fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>; +// TODO: Halfword multiple accumulate long: SMLAL +// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD -def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>; +//===----------------------------------------------------------------------===// +// Misc. Arithmetic Instructions. +// -// Floating Point Arithmetic -def FADDS : FPBinOp<"fadds", fadd>; -def FADDD : DFPBinOp<"faddd", fadd>; -def FSUBS : FPBinOp<"fsubs", fsub>; -def FSUBD : DFPBinOp<"fsubd", fsub>; +def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, + "clz", " $dst, $src", + [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>; + +def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, + "rev", " $dst, $src", + [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>; + +def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, + "rev16", " $dst, $src", + [(set GPR:$dst, + (or (and (srl GPR:$src, 8), 0xFF), + (or (and (shl GPR:$src, 8), 0xFF00), + (or (and (srl GPR:$src, 8), 0xFF0000), + (and (shl GPR:$src, 8), 0xFF000000)))))]>, + Requires<[IsARM, HasV6]>; + +def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, + "revsh", " $dst, $src", + [(set GPR:$dst, + (sext_inreg + (or (srl (and GPR:$src, 0xFF00), 8), + (shl GPR:$src, 8)), i16))]>, + Requires<[IsARM, HasV6]>; + +def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), + Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt", + [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), + (and (shl GPR:$src2, (i32 imm:$shamt)), + 0xFFFF0000)))]>, + Requires<[IsARM, HasV6]>; + +// Alternate cases for PKHBT where identities eliminate some nodes. +def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), + (PKHBT GPR:$src1, GPR:$src2, 0)>; +def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), + (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; + + +def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), + Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt", + [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), + (and (sra GPR:$src2, imm16_31:$shamt), + 0xFFFF)))]>, Requires<[IsARM, HasV6]>; + +// Alternate cases for PKHTB where identities eliminate some nodes. Note that +// a shift amount of 0 is *not legal* here, it is PKHBT instead. +def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)), + (PKHTB GPR:$src1, GPR:$src2, 16)>; +def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), + (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), + (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; -def FNEGS : InstARM<(ops FPRegs:$dst, FPRegs:$src), - "fnegs $dst, $src", - [(set FPRegs:$dst, (fneg FPRegs:$src))]>; -def FNEGD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), - "fnegd $dst, $src", - [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; +//===----------------------------------------------------------------------===// +// Comparison Instructions... +// -def FABSS : InstARM<(ops FPRegs:$dst, FPRegs:$src), - "fabss $dst, $src", - [(set FPRegs:$dst, (fabs FPRegs:$src))]>; +defm CMP : AI1_cmp_irs<0xA, "cmp", + BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; +defm CMN : AI1_cmp_irs<0xB, "cmn", + BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; + +// Note that TST/TEQ don't set all the same flags that CMP does! +defm TST : AI1_cmp_irs<0x8, "tst", + BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; +defm TEQ : AI1_cmp_irs<0x9, "teq", + BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; + +defm CMPnz : AI1_cmp_irs<0xA, "cmp", + BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; +defm CMNnz : AI1_cmp_irs<0xA, "cmn", + BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; + +def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), + (CMNri GPR:$src, so_imm_neg:$imm)>; + +def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), + (CMNri GPR:$src, so_imm_neg:$imm)>; + + +// Conditional moves +// FIXME: should be able to write a pattern for ARMcmov, but can't use +// a two-value operand where a dag node expects two operands. :( +def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true), + DPRdReg, "mov", " $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">; + +def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true), + DPRdSoReg, "mov", " $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">; + +def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true), + DPRdIm, "mov", " $dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">; + + +// LEApcrel - Load a pc-relative address into a register without offending the +// assembler. +def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, + !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", + "${:private}PCRELL${:uid}+8))\n"), + !strconcat("${:private}PCRELL${:uid}:\n\t", + "add$p $dst, pc, #PCRELV${:uid}")), + []>; + +def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), + Pseudo, + !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", + "${:private}PCRELL${:uid}+8))\n"), + !strconcat("${:private}PCRELL${:uid}:\n\t", + "add$p $dst, pc, #PCRELV${:uid}")), + []>; -def FABSD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), - "fabsd $dst, $src", - [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; +//===----------------------------------------------------------------------===// +// TLS Instructions +// -def FMULS : FPBinOp<"fmuls", fmul>; -def FMULD : DFPBinOp<"fmuld", fmul>; -def FDIVS : FPBinOp<"fdivs", fdiv>; -def FDIVD : DFPBinOp<"fdivd", fdiv>; +// __aeabi_read_tp preserves the registers r1-r3. +let isCall = 1, + Defs = [R0, R12, LR, CPSR] in { + def TPsoft : AXI<0x0, (outs), (ins), BranchMisc, + "bl __aeabi_read_tp", + [(set R0, ARMthread_pointer)]>; +} -// Floating Point Load -def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr), - "flds $dst, $addr", - [(set FPRegs:$dst, (load addr_mode5:$addr))]>; +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns +// -def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr), - "fldd $dst, $addr", - [(set DFPRegs:$dst, (load addr_mode5:$addr))]>; +// ConstantPool, GlobalAddress, and JumpTable +def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>; +def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; +def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), + (LEApcrelJT tjumptable:$dst, imm:$id)>; + +// Large immediate handling. + +// Two piece so_imms. +let isReMaterializable = 1 in +def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc, + "mov", " $dst, $src", + [(set GPR:$dst, so_imm2part:$src)]>; + +def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), + (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), + (so_imm2part_2 imm:$RHS))>; +def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), + (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), + (so_imm2part_2 imm:$RHS))>; + +// TODO: add,sub,and, 3-instr forms? + + +// Direct calls +def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; + +// zextload i1 -> zextload i8 +def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; + +// extload -> zextload +def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; +def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; +def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; + +// smul* and smla* +def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)), + (SMULBB GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), + (SMULBB GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)), + (SMULBT GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)), + (SMULBT GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)), + (SMULTB GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b), + (SMULTB GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16), + (SMULWB GPR:$a, GPR:$b)>; +def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16), + (SMULWB GPR:$a, GPR:$b)>; + +def : ARMV5TEPat<(add GPR:$acc, + (mul (sra (shl GPR:$a, 16), 16), + (sra (shl GPR:$b, 16), 16))), + (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (mul sext_16_node:$a, sext_16_node:$b)), + (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))), + (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (mul sext_16_node:$a, (sra GPR:$b, 16))), + (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))), + (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (mul (sra GPR:$a, 16), sext_16_node:$b)), + (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)), + (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; +def : ARMV5TEPat<(add GPR:$acc, + (sra (mul GPR:$a, sext_16_node:$b), 16)), + (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; -// Floating Point Store -def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr), - "fsts $src, $addr", - [(store FPRegs:$src, addr_mode5:$addr)]>; +//===----------------------------------------------------------------------===// +// Thumb Support +// -def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr), - "fstd $src, $addr", - [(store DFPRegs:$src, addr_mode5:$addr)]>; +include "ARMInstrThumb.td" -def : Pat<(ARMcall tglobaladdr:$dst), - (bl tglobaladdr:$dst)>; +//===----------------------------------------------------------------------===// +// Floating Point Support +// -def : Pat<(ARMcall texternalsym:$dst), - (bl texternalsym:$dst)>; +include "ARMInstrVFP.td"