X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARM.h;h=cd7540e5241085c5904d58cbcd1fcca5ada8e151;hb=1422e1f158810323cfbe06d9242ba35c3f674921;hp=c582d684bfe25c041a9e5ee7e72fbb79bc56b1ca;hpb=a3f99f90338d89354384ca25f53ca4450a1a9d18;p=oota-llvm.git

diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h
index c582d684bfe..cd7540e5241 100644
--- a/lib/Target/ARM/ARM.h
+++ b/lib/Target/ARM/ARM.h
@@ -1,4 +1,4 @@
-//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
+//===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,115 +12,39 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef TARGET_ARM_H
-#define TARGET_ARM_H
+#ifndef LLVM_LIB_TARGET_ARM_ARM_H
+#define LLVM_LIB_TARGET_ARM_ARM_H
 
-#include "llvm/Target/TargetMachine.h"
-#include <cassert>
+#include "llvm/Support/CodeGen.h"
+#include <functional>
 
 namespace llvm {
 
-class ARMTargetMachine;
+class ARMAsmPrinter;
+class ARMBaseTargetMachine;
+class Function;
 class FunctionPass;
-class MachineCodeEmitter;
-class JITCodeEmitter;
-class raw_ostream;
-
-// Enums corresponding to ARM condition codes
-namespace ARMCC {
-  // The CondCodes constants map directly to the 4-bit encoding of the 
-  // condition field for predicated instructions. 
-  enum CondCodes {
-    EQ,
-    NE,
-    HS,
-    LO,
-    MI,
-    PL,
-    VS,
-    VC,
-    HI,
-    LS,
-    GE,
-    LT,
-    GT,
-    LE,
-    AL
-  };
-  
-  inline static CondCodes getOppositeCondition(CondCodes CC){
-    switch (CC) {
-    default: assert(0 && "Unknown condition code");
-    case EQ: return NE;
-    case NE: return EQ;
-    case HS: return LO;
-    case LO: return HS;
-    case MI: return PL;
-    case PL: return MI;
-    case VS: return VC;
-    case VC: return VS;
-    case HI: return LS;
-    case LS: return HI;
-    case GE: return LT;
-    case LT: return GE;
-    case GT: return LE;
-    case LE: return GT;
-    }
-  }
-}
-
-inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
-  switch (CC) {
-  default: assert(0 && "Unknown condition code");
-  case ARMCC::EQ:  return "eq";
-  case ARMCC::NE:  return "ne";
-  case ARMCC::HS:  return "hs";
-  case ARMCC::LO:  return "lo";
-  case ARMCC::MI:  return "mi";
-  case ARMCC::PL:  return "pl";
-  case ARMCC::VS:  return "vs";
-  case ARMCC::VC:  return "vc";
-  case ARMCC::HI:  return "hi";
-  case ARMCC::LS:  return "ls";
-  case ARMCC::GE:  return "ge";
-  case ARMCC::LT:  return "lt";
-  case ARMCC::GT:  return "gt";
-  case ARMCC::LE:  return "le";
-  case ARMCC::AL:  return "al";
-  }
-}
-
-FunctionPass *createARMISelDag(ARMTargetMachine &TM);
-FunctionPass *createARMCodePrinterPass(raw_ostream &O,
-                                       ARMTargetMachine &TM,
-                                       CodeGenOpt::Level OptLevel,
-                                       bool Verbose);
-FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
-                                       MachineCodeEmitter &MCE);
-
-FunctionPass *createARMCodeEmitterPass(
-    ARMTargetMachine &TM, MachineCodeEmitter &MCE);
-/*
-template< class machineCodeEmitter>
-FunctionPass *createARMCodeEmitterPass(
-    ARMTargetMachine &TM, machineCodeEmitter &MCE);
-*/
-FunctionPass *createARMJITCodeEmitterPass(
-    ARMTargetMachine &TM, JITCodeEmitter &JCE);
-
-FunctionPass *createARMLoadStoreOptimizationPass();
+class ImmutablePass;
+class MachineInstr;
+class MCInst;
+class TargetLowering;
+class TargetMachine;
+
+FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
+                               CodeGenOpt::Level OptLevel);
+FunctionPass *createA15SDOptimizerPass();
+FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
+FunctionPass *createARMExpandPseudoPass();
 FunctionPass *createARMConstantIslandPass();
+FunctionPass *createMLxExpansionPass();
+FunctionPass *createThumb2ITBlockPass();
+FunctionPass *createARMOptimizeBarriersPass();
+FunctionPass *createThumb2SizeReductionPass(
+    std::function<bool(const Function &)> Ftor = nullptr);
 
-} // end namespace llvm;
-
-// Defines symbolic names for ARM registers.  This defines a mapping from
-// register name to register number.
-//
-#include "ARMGenRegisterNames.inc"
-
-// Defines symbolic names for the ARM instructions.
-//
-#include "ARMGenInstrNames.inc"
+void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
+                                  ARMAsmPrinter &AP);
 
+} // end namespace llvm;
 
 #endif