X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FAArch64%2FAArch64RegisterInfo.td;h=9de7abdf5ff04132a1490b74f8eb491e1d7aa3ca;hb=08f6677a7fa8b89412c0e27e5445813174361504;hp=5e2b1963977aedd3c078c6dc3c515f572b73f1d4;hpb=6a5a667517160ca1b557002a29d08868ae029451;p=oota-llvm.git

diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td
index 5e2b1963977..9de7abdf5ff 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -30,7 +30,6 @@ def dsub_0 : SubRegIndex<64>;
 def dsub_1 : SubRegIndex<64, 64>;
 def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
 def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
-def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>;
 }
 
 // Registers are identified with 5-bit ID numbers.
@@ -147,7 +146,7 @@ foreach Index = 0-31 in {
 }
 
 
-def FPR8 : RegisterClass<"AArch64", [i8, v1i8], 8,
+def FPR8 : RegisterClass<"AArch64", [v1i8], 8,
                           (sequence "B%u", 0, 31)> {
 }
 
@@ -155,7 +154,7 @@ def FPR16 : RegisterClass<"AArch64", [f16, v1i16], 16,
                           (sequence "H%u", 0, 31)> {
 }
 
-def FPR32 : RegisterClass<"AArch64", [f32, v1i32, v1f32], 32,
+def FPR32 : RegisterClass<"AArch64", [f32, v1i32], 32,
                           (sequence "S%u", 0, 31)> {
 }
 
@@ -164,7 +163,7 @@ def FPR64 : RegisterClass<"AArch64",
                           64, (sequence "D%u", 0, 31)>;
 
 def FPR128 : RegisterClass<"AArch64",
-                           [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+                           [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
                            128, (sequence "Q%u", 0, 31)>;
 
 def FPR64Lo : RegisterClass<"AArch64",
@@ -172,7 +171,7 @@ def FPR64Lo : RegisterClass<"AArch64",
                             64, (sequence "D%u", 0, 15)>;
 
 def FPR128Lo : RegisterClass<"AArch64",
-                             [f128,v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
+                             [f128, v2f64, v2i64, v4f32, v4i32, v8i16, v16i8],
                              128, (sequence "Q%u", 0, 15)>;
 
 //===----------------------------------------------------------------------===//
@@ -206,7 +205,7 @@ def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
 //===----------------------------------------------------------------------===//
 //  Consecutive vector registers
 //===----------------------------------------------------------------------===//
-// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D30_D31
+// 2 Consecutive 64-bit registers: D0_D1, D1_D2, ..., D31_D0
 def Tuples2D : RegisterTuples<[dsub_0, dsub_1],
                               [(rotl FPR64, 0), (rotl FPR64, 1)]>;
                               
@@ -261,12 +260,12 @@ multiclass VectorList_operands<string PREFIX, string LAYOUT, int Count,
     let Name = PREFIX # LAYOUT # Count;
     let RenderMethod = "addVectorListOperands";
     let PredicateMethod = 
-        "isVectorList<A64Layout::_" # LAYOUT # ", " # Count # ">";
+        "isVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">";
     let ParserMethod = "ParseVectorList";
   }
 
   def _operand : RegisterOperand<RegList,
-        "printVectorList<A64Layout::_" # LAYOUT # ", " # Count # ">"> {
+        "printVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">"> {
     let ParserMatchClass =
       !cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand");
   }
@@ -288,4 +287,4 @@ multiclass VectorList_BHSD<string PREFIX, int Count, RegisterClass DRegList,
 defm VOne : VectorList_BHSD<"VOne", 1, FPR64, FPR128>;
 defm VPair : VectorList_BHSD<"VPair", 2, DPair, QPair>;
 defm VTriple : VectorList_BHSD<"VTriple", 3, DTriple, QTriple>;
-defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;
\ No newline at end of file
+defm VQuad : VectorList_BHSD<"VQuad", 4, DQuad, QQuad>;