X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FSupport%2FMemory.cpp;h=22f74944865ca9cc5abd8310ded933f5dfd18cfb;hb=c82cc587a468d44e5cfabfa8f8a639667127845d;hp=1294744649e3bf0860a0fd596a2de3e28bb1ca55;hpb=c4cc40c001e23dbeb6cb9953715177ccb314fbf1;p=oota-llvm.git

diff --git a/lib/Support/Memory.cpp b/lib/Support/Memory.cpp
index 1294744649e..22f74944865 100644
--- a/lib/Support/Memory.cpp
+++ b/lib/Support/Memory.cpp
@@ -16,6 +16,10 @@
 #include "llvm/Support/Valgrind.h"
 #include "llvm/Config/config.h"
 
+#if defined(__mips__)
+#include <sys/cachectl.h>
+#endif
+
 namespace llvm {
 using namespace sys;
 }
@@ -30,39 +34,6 @@ using namespace sys;
 
 extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
 
-/// ClearMipsCache - Invalidates instruction cache for Mips. This assembly code
-/// is copied from the MIPS32 Instruction Set Reference. Since the code ends
-/// with the return instruction "jr.hb ra" (Jump Register with Hazard Barrier),
-/// it must be implemented as a function (which is called from the
-/// InvalidateInstructionCache function). It cannot be directly inlined into
-/// InvalidateInstructionCache function, because in that case the epilog of
-/// InvalidateInstructionCache will not be executed.
-#if defined(__mips__)
-extern "C" void ClearMipsCache(const void* Addr, size_t Size);
-  asm volatile(
-    ".text\n"
-    ".align 2\n"
-    ".globl ClearMipsCache\n"
-    "ClearMipsCache:\n"
-    ".set       noreorder\n"
-    "beq $a1, $zero, 20f\n"          /* If size==0, branch around */
-    "nop\n"
-    "addu       $a1, $a0, $a1\n"     /* Calculate end address + 1 */
-    "rdhwr      $v0, $1\n"           /* Get step size for SYNCI */
-                                     /* $1 is $HW_SYNCI_Step */
-    "beq        $v0, $zero, 20f\n"   /* If no caches require synchronization, */
-                                     /* branch around */
-    "nop\n"
-    "10: synci  0($a0)\n"            /* Synchronize all caches around address */
-    "sltu       $v1, $a0, $a1\n"     /* Compare current with end address */
-    "bne        $v1, $zero, 10b\n"   /* Branch if more to do */
-    "addu       $a0, $a0, $v0\n"     /* Add step size in delay slot */
-    "sync\n"                         /* Clear memory hazards */
-    "20: jr.hb      $ra\n"           /* Return, clearing instruction hazards */
-    "nop\n"
-  );
-#endif
-
 /// InvalidateInstructionCache - Before the JIT can run a block of code
 /// that has been emitted it must invalidate the instruction cache on some
 /// platforms.
@@ -74,7 +45,7 @@ void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
 
 #  if (defined(__POWERPC__) || defined (__ppc__) || \
      defined(_POWER) || defined(_ARCH_PPC)) || defined(__arm__)
-  sys_icache_invalidate(Addr, Len);
+  sys_icache_invalidate(const_cast<void *>(Addr), Len);
 #  endif
 
 #else
@@ -96,11 +67,12 @@ void llvm::sys::Memory::InvalidateInstructionCache(const void *Addr,
   asm volatile("isync");
 #  elif defined(__arm__) && defined(__GNUC__)
   // FIXME: Can we safely always call this for __GNUC__ everywhere?
-  char *Start = (char*) Addr;
-  char *End = Start + Len;
-  __clear_cache(Start, End);
+  const char *Start = static_cast<const char *>(Addr);
+  const char *End = Start + Len;
+  __clear_cache(const_cast<char *>(Start), const_cast<char *>(End));
 #  elif defined(__mips__)
-  ClearMipsCache(Addr, Len);
+  const char *Start = static_cast<const char *>(Addr);
+  cacheflush(const_cast<char *>(Start), Len, BCACHE);
 #  endif
 
 #endif  // end apple