X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FMC%2FMCSubtargetInfo.cpp;h=ece775c4f08f7755236ea85b77d2561d9e229fbe;hb=ad0b09d10ebd7a3b540d52ef8c3ee1d181af3d1c;hp=6abdd3acbc5a355a58019302f4780281074f6054;hpb=d714fcf5c8c2046434a29651dff11ee4d00cc7d4;p=oota-llvm.git diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp index 6abdd3acbc5..ece775c4f08 100644 --- a/lib/MC/MCSubtargetInfo.cpp +++ b/lib/MC/MCSubtargetInfo.cpp @@ -34,17 +34,12 @@ MCSubtargetInfo::InitCPUSchedModel(StringRef CPU) { CPUSchedModel = MCSchedModel::GetDefaultSchedModel(); } -void -MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, - ArrayRef PF, - ArrayRef PD, - const SubtargetInfoKV *ProcSched, - const MCWriteProcResEntry *WPR, - const MCWriteLatencyEntry *WL, - const MCReadAdvanceEntry *RA, - const InstrStage *IS, - const unsigned *OC, - const unsigned *FP) { +void MCSubtargetInfo::InitMCSubtargetInfo( + const Triple &TT, StringRef C, StringRef FS, + ArrayRef PF, ArrayRef PD, + const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, + const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, + const InstrStage *IS, const unsigned *OC, const unsigned *FP) { TargetTriple = TT; CPU = C; ProcFeatures = PF; @@ -81,6 +76,11 @@ FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) { return FeatureBits; } +FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) { + SubtargetFeatures Features; + FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures); + return FeatureBits; +} MCSchedModel MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {