X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FSelectionDAG%2FSelectionDAGBuild.cpp;h=1b1d70baab82ac5df40391d46a31b397d72099e3;hb=d24479730a8790d82c4859dc477bc2416d7a6bda;hp=94170420d0f1880a284ed36c05598ab7ad6db7fa;hpb=219ab405e6bea993da14cf3ce7b50983c3bb7a6f;p=oota-llvm.git diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 94170420d0f..1b1d70baab8 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -37,16 +37,21 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/DwarfWriter.h" +#include "llvm/Analysis/DebugInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include using namespace llvm; @@ -62,7 +67,7 @@ LimitFPPrecision("limit-float-precision", cl::init(0)); /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence -/// insertvalue or extractvalue indices that identify a member, return +/// of insertvalue or extractvalue indices that identify a member, return /// the linearized index of the start of the member. /// static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, @@ -83,6 +88,7 @@ static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, return ComputeLinearIndex(TLI, *EI, Indices+1, IndicesEnd, CurIndex); CurIndex = ComputeLinearIndex(TLI, *EI, 0, 0, CurIndex); } + return CurIndex; } // Given an array type, recursively traverse the elements. else if (const ArrayType *ATy = dyn_cast(Ty)) { @@ -92,6 +98,7 @@ static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, return ComputeLinearIndex(TLI, EltTy, Indices+1, IndicesEnd, CurIndex); CurIndex = ComputeLinearIndex(TLI, EltTy, 0, 0, CurIndex); } + return CurIndex; } // We haven't found the type we're looking for, so keep searching. return CurIndex + 1; @@ -122,7 +129,7 @@ static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, // Given an array type, recursively traverse the elements. if (const ArrayType *ATy = dyn_cast(Ty)) { const Type *EltTy = ATy->getElementType(); - uint64_t EltSize = TLI.getTargetData()->getABITypeSize(EltTy); + uint64_t EltSize = TLI.getTargetData()->getTypePaddedSize(EltTy); for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i) ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets, StartingOffset + i * EltSize); @@ -143,7 +150,7 @@ namespace llvm { /// have aggregate-typed registers. The values at this point do not necessarily /// have legal types, so each value may require one or more registers of some /// legal type. - /// + /// struct VISIBILITY_HIDDEN RegsForValue { /// TLI - The TargetLowering object. /// @@ -153,7 +160,7 @@ namespace llvm { /// may need be promoted or synthesized from one or more registers. /// SmallVector ValueVTs; - + /// RegVTs - The value types of the registers. This is the same size as /// ValueVTs and it records, for each value, what the type of the assigned /// register or registers are. (Individual values are never synthesized @@ -164,21 +171,21 @@ namespace llvm { /// it is necessary to have a separate record of the types. /// SmallVector RegVTs; - + /// Regs - This list holds the registers assigned to the values. /// Each legal or promoted value requires one register, and each /// expanded value requires multiple registers. /// SmallVector Regs; - + RegsForValue() : TLI(0) {} - + RegsForValue(const TargetLowering &tli, - const SmallVector ®s, + const SmallVector ®s, MVT regvt, MVT valuevt) : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} RegsForValue(const TargetLowering &tli, - const SmallVector ®s, + const SmallVector ®s, const SmallVector ®vts, const SmallVector &valuevts) : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} @@ -196,7 +203,7 @@ namespace llvm { Reg += NumRegs; } } - + /// append - Add the specified values to this one. void append(const RegsForValue &RHS) { TLI = RHS.TLI; @@ -204,24 +211,24 @@ namespace llvm { RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); Regs.append(RHS.Regs.begin(), RHS.Regs.end()); } - - + + /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from - /// this value and returns the result as a ValueVTs value. This uses + /// this value and returns the result as a ValueVTs value. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. - SDValue getCopyFromRegs(SelectionDAG &DAG, + SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const; /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the - /// specified value into the registers specified by this object. This uses + /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. - void getCopyToRegs(SDValue Val, SelectionDAG &DAG, + void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const; - + /// AddInlineAsmOperands - Add this value to the specified inlineasm node - /// operand list. This adds the code marker and includes the number of + /// operand list. This adds the code marker and includes the number of /// values added into it. void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, std::vector &Ops) const; @@ -229,7 +236,7 @@ namespace llvm { } /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by -/// PHI nodes or outside of the basic block that defines it, or used by a +/// PHI nodes or outside of the basic block that defines it, or used by a /// switch or atomic instruction, which may expand to multiple basic blocks. static bool isUsedOutsideOfDefiningBlock(Instruction *I) { if (isa(I)) return true; @@ -265,6 +272,7 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli) } void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, + SelectionDAG &DAG, bool EnableFastISel) { Fn = &fn; MF = &mf; @@ -285,8 +293,8 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, if (AllocaInst *AI = dyn_cast(I)) if (ConstantInt *CUI = dyn_cast(AI->getArraySize())) { const Type *Ty = AI->getAllocatedType(); - uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); - unsigned Align = + uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty); + unsigned Align = std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), AI->getAlignment()); @@ -314,9 +322,54 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, // Create Machine PHI nodes for LLVM PHI nodes, lowering them as // appropriate. PHINode *PN; - for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast(I)); ++I){ - if (PN->use_empty()) continue; - + DebugLoc DL; + for (BasicBlock::iterator + I = BB->begin(), E = BB->end(); I != E; ++I) { + if (CallInst *CI = dyn_cast(I)) { + if (Function *F = CI->getCalledFunction()) { + switch (F->getIntrinsicID()) { + default: break; + case Intrinsic::dbg_stoppoint: { + DwarfWriter *DW = DAG.getDwarfWriter(); + DbgStopPointInst *SPI = cast(I); + + if (DW && DW->ValidDebugInfo(SPI->getContext())) { + DICompileUnit CU(cast(SPI->getContext())); + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), + CU.getFilename()); + unsigned idx = MF->getOrCreateDebugLocID(SrcFile, + SPI->getLine(), + SPI->getColumn()); + DL = DebugLoc::get(idx); + } + + break; + } + case Intrinsic::dbg_func_start: { + DwarfWriter *DW = DAG.getDwarfWriter(); + if (DW) { + DbgFuncStartInst *FSI = cast(I); + Value *SP = FSI->getSubprogram(); + + if (DW->ValidDebugInfo(SP)) { + DISubprogram Subprogram(cast(SP)); + DICompileUnit CU(Subprogram.getCompileUnit()); + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), + CU.getFilename()); + unsigned Line = Subprogram.getLineNumber(); + DL = DebugLoc::get(MF->getOrCreateDebugLocID(SrcFile, Line, 0)); + } + } + + break; + } + } + } + } + + PN = dyn_cast(I); + if (!PN || PN->use_empty()) continue; + unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); @@ -327,7 +380,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, unsigned NumRegisters = TLI.getNumRegisters(VT); const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); for (unsigned i = 0; i != NumRegisters; ++i) - BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i); + BuildMI(MBB, DL, TII->get(TargetInstrInfo::PHI), PHIReg + i); PHIReg += NumRegisters; } } @@ -368,14 +421,12 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { /// larger then ValueVT then AssertOp can be used to specify whether the extra /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT /// (ISD::AssertSext). -static SDValue getCopyFromParts(SelectionDAG &DAG, - const SDValue *Parts, - unsigned NumParts, - MVT PartVT, - MVT ValueVT, - ISD::NodeType AssertOp = ISD::DELETED_NODE) { +static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, + const SDValue *Parts, + unsigned NumParts, MVT PartVT, MVT ValueVT, + ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); - TargetLowering &TLI = DAG.getTargetLoweringInfo(); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); SDValue Val = Parts[0]; if (NumParts > 1) { @@ -397,34 +448,35 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, MVT::getFloatingPointVT(RoundBits/2); if (RoundParts > 2) { - Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); - Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, + Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT); + Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2, PartVT, HalfVT); } else { - Lo = DAG.getNode(ISD::BIT_CONVERT, HalfVT, Parts[0]); - Hi = DAG.getNode(ISD::BIT_CONVERT, HalfVT, Parts[1]); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); } if (TLI.isBigEndian()) std::swap(Lo, Hi); - Val = DAG.getNode(ISD::BUILD_PAIR, RoundVT, Lo, Hi); + Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); if (RoundParts < NumParts) { // Assemble the trailing non-power-of-2 part. unsigned OddParts = NumParts - RoundParts; MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); - Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); + Hi = getCopyFromParts(DAG, dl, + Parts+RoundParts, OddParts, PartVT, OddVT); // Combine the round and odd parts. Lo = Val; if (TLI.isBigEndian()) std::swap(Lo, Hi); MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); - Hi = DAG.getNode(ISD::ANY_EXTEND, TotalVT, Hi); - Hi = DAG.getNode(ISD::SHL, TotalVT, Hi, + Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); + Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, DAG.getConstant(Lo.getValueType().getSizeInBits(), - TLI.getShiftAmountTy())); - Lo = DAG.getNode(ISD::ZERO_EXTEND, TotalVT, Lo); - Val = DAG.getNode(ISD::OR, TotalVT, Lo, Hi); + TLI.getPointerTy())); + Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); + Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); } } else { // Handle a multi-element vector. @@ -445,7 +497,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, // If the register was not expanded, truncate or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, + Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, PartVT, IntermediateVT); } else if (NumParts > 0) { // If the intermediate type was expanded, build the intermediate operands @@ -454,14 +506,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, + Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, PartVT, IntermediateVT); } // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate // operands. Val = DAG.getNode(IntermediateVT.isVector() ? - ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, + ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, ValueVT, &Ops[0], NumIntermediates); } } @@ -474,14 +526,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, if (PartVT.isVector()) { assert(ValueVT.isVector() && "Unknown vector conversion!"); - return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); } if (ValueVT.isVector()) { assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial scalar-to-vector conversions should get here!"); - return DAG.getNode(ISD::BUILD_VECTOR, ValueVT, Val); + return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); } if (PartVT.isInteger() && @@ -491,24 +543,24 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, // indicate whether the truncated bits will always be // zero or sign-extension. if (AssertOp != ISD::DELETED_NODE) - Val = DAG.getNode(AssertOp, PartVT, Val, + Val = DAG.getNode(AssertOp, dl, PartVT, Val, DAG.getValueType(ValueVT)); - return DAG.getNode(ISD::TRUNCATE, ValueVT, Val); + return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { - return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val); + return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); } } if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { if (ValueVT.bitsLT(Val.getValueType())) // FP_ROUND's are always exact here. - return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, + return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, DAG.getIntPtrConstant(1)); - return DAG.getNode(ISD::FP_EXTEND, ValueVT, Val); + return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); } if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) - return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); assert(0 && "Unknown mismatch!"); return SDValue(); @@ -517,10 +569,10 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, /// getCopyToParts - Create a series of nodes that contain the specified value /// split into legal parts. If the parts contain more bits than Val, then, for /// integers, ExtendKind can be used to specify how to generate the extra bits. -static void getCopyToParts(SelectionDAG &DAG, SDValue Val, +static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { - TargetLowering &TLI = DAG.getTargetLoweringInfo(); + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); MVT PtrVT = TLI.getPointerTy(); MVT ValueVT = Val.getValueType(); unsigned PartBits = PartVT.getSizeInBits(); @@ -540,22 +592,22 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, // If the parts cover more bits than the value has, promote the value. if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { assert(NumParts == 1 && "Do not know what to promote to!"); - Val = DAG.getNode(ISD::FP_EXTEND, PartVT, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); } else if (PartVT.isInteger() && ValueVT.isInteger()) { ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ExtendKind, ValueVT, Val); + Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. assert(NumParts == 1 && PartVT != ValueVT); - Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { // If the parts cover less bits than value has, truncate the value. if (PartVT.isInteger() && ValueVT.isInteger()) { ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); + Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } @@ -580,21 +632,21 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, unsigned RoundParts = 1 << Log2_32(NumParts); unsigned RoundBits = RoundParts * PartBits; unsigned OddParts = NumParts - RoundParts; - SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val, - DAG.getConstant(RoundBits, - TLI.getShiftAmountTy())); - getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); + SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, + DAG.getConstant(RoundBits, + TLI.getPointerTy())); + getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT); if (TLI.isBigEndian()) // The odd parts were reversed by getCopyToParts - unreverse them. std::reverse(Parts + RoundParts, Parts + NumParts); NumParts = RoundParts; ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ISD::TRUNCATE, ValueVT, Val); + Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } // The number of parts is a power of 2. Repeatedly bisect the value using // EXTRACT_ELEMENT. - Parts[0] = DAG.getNode(ISD::BIT_CONVERT, + Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::getIntegerVT(ValueVT.getSizeInBits()), Val); for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { @@ -604,14 +656,18 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, SDValue &Part0 = Parts[i]; SDValue &Part1 = Parts[i+StepSize/2]; - Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, + Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, + ThisVT, Part0, DAG.getConstant(1, PtrVT)); - Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, ThisVT, Part0, + Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, + ThisVT, Part0, DAG.getConstant(0, PtrVT)); if (ThisBits == PartBits && ThisVT != PartVT) { - Part0 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part0); - Part1 = DAG.getNode(ISD::BIT_CONVERT, PartVT, Part1); + Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, + PartVT, Part0); + Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, + PartVT, Part1); } } } @@ -626,12 +682,13 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, if (NumParts == 1) { if (PartVT != ValueVT) { if (PartVT.isVector()) { - Val = DAG.getNode(ISD::BIT_CONVERT, PartVT, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); } else { assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); - Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, PartVT, Val, + Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, + PartVT, Val, DAG.getConstant(0, PtrVT)); } } @@ -643,8 +700,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, // Handle a multi-element vector. MVT IntermediateVT, RegisterVT; unsigned NumIntermediates; - unsigned NumRegs = - DAG.getTargetLoweringInfo() + unsigned NumRegs = TLI .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, RegisterVT); unsigned NumElements = ValueVT.getVectorNumElements(); @@ -657,13 +713,13 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, SmallVector Ops(NumIntermediates); for (unsigned i = 0; i != NumIntermediates; ++i) if (IntermediateVT.isVector()) - Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, + Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, IntermediateVT, Val, DAG.getConstant(i * (NumElements / NumIntermediates), PtrVT)); else - Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, - IntermediateVT, Val, + Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, + IntermediateVT, Val, DAG.getConstant(i, PtrVT)); // Split the intermediate operands into legal parts. @@ -671,7 +727,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, // If the register was not expanded, promote or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); + getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); } else if (NumParts > 0) { // If the intermediate type was expanded, split each the value into // legal parts. @@ -679,7 +735,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); + getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT); } } @@ -720,7 +776,7 @@ SDValue SelectionDAGLowering::getRoot() { } // Otherwise, we have to make a token factor node. - SDValue Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &PendingLoads[0], PendingLoads.size()); PendingLoads.clear(); DAG.setRoot(Root); @@ -750,7 +806,7 @@ SDValue SelectionDAGLowering::getControlRoot() { PendingExports.push_back(Root); } - Root = DAG.getNode(ISD::TokenFactor, MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &PendingExports[0], PendingExports.size()); PendingExports.clear(); @@ -773,7 +829,7 @@ void SelectionDAGLowering::visit(unsigned Opcode, User &I) { case Instruction::OPCODE:return visit##OPCODE((CLASS&)I); #include "llvm/Instruction.def" } -} +} void SelectionDAGLowering::visitAdd(User &I) { if (I.getType()->isFPOrFPVector()) @@ -792,25 +848,25 @@ void SelectionDAGLowering::visitMul(User &I) { SDValue SelectionDAGLowering::getValue(const Value *V) { SDValue &N = NodeMap[V]; if (N.getNode()) return N; - + if (Constant *C = const_cast(dyn_cast(V))) { MVT VT = TLI.getValueType(V->getType(), true); - + if (ConstantInt *CI = dyn_cast(C)) return N = DAG.getConstant(*CI, VT); if (GlobalValue *GV = dyn_cast(C)) return N = DAG.getGlobalAddress(GV, VT); - + if (isa(C)) return N = DAG.getConstant(0, TLI.getPointerTy()); - + if (ConstantFP *CFP = dyn_cast(C)) return N = DAG.getConstantFP(*CFP, VT); - + if (isa(C) && !isa(V->getType()) && !V->getType()->isAggregateType()) - return N = DAG.getNode(ISD::UNDEF, VT); + return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); if (ConstantExpr *CE = dyn_cast(C)) { visit(CE->getOpcode(), *CE); @@ -818,7 +874,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { assert(N1.getNode() && "visit didn't populate the ValueMap!"); return N1; } - + if (isa(C) || isa(C)) { SmallVector Constants; for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); @@ -843,7 +899,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { for (unsigned i = 0; i != NumElts; ++i) { MVT EltVT = ValueVTs[i]; if (isa(C)) - Constants[i] = DAG.getNode(ISD::UNDEF, EltVT); + Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); else if (EltVT.isFloatingPoint()) Constants[i] = DAG.getConstantFP(0, EltVT); else @@ -854,7 +910,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { const VectorType *VecTy = cast(V->getType()); unsigned NumElements = VecTy->getNumElements(); - + // Now that we know the number and type of the elements, get that number of // elements into the Ops array based on what kind of constant it is. SmallVector Ops; @@ -868,18 +924,19 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { SDValue Op; if (isa(C)) - Op = DAG.getNode(ISD::UNDEF, EltVT); + Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); else if (EltVT.isFloatingPoint()) Op = DAG.getConstantFP(0, EltVT); else Op = DAG.getConstant(0, EltVT); Ops.assign(NumElements, Op); } - + // Create a BUILD_VECTOR node. - return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); + return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), + VT, &Ops[0], Ops.size()); } - + // If this is a static alloca, generate it as the frameindex instead of // computation. if (const AllocaInst *AI = dyn_cast(V)) { @@ -888,25 +945,26 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { if (SI != FuncInfo.StaticAllocaMap.end()) return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); } - + unsigned InReg = FuncInfo.ValueMap[V]; assert(InReg && "Value not in map!"); - + RegsForValue RFV(TLI, InReg, V->getType()); SDValue Chain = DAG.getEntryNode(); - return RFV.getCopyFromRegs(DAG, Chain, NULL); + return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); } void SelectionDAGLowering::visitRet(ReturnInst &I) { if (I.getNumOperands() == 0) { - DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getControlRoot())); + DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), + MVT::Other, getControlRoot())); return; } - + SmallVector NewValues; NewValues.push_back(getControlRoot()); - for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { + for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { SmallVector ValueVTs; ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); @@ -929,14 +987,15 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { MVT PartVT = TLI.getRegisterType(VT); SmallVector Parts(NumParts); ISD::NodeType ExtendKind = ISD::ANY_EXTEND; - + const Function *F = I.getParent()->getParent(); if (F->paramHasAttr(0, Attribute::SExt)) ExtendKind = ISD::SIGN_EXTEND; else if (F->paramHasAttr(0, Attribute::ZExt)) ExtendKind = ISD::ZERO_EXTEND; - getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j), + getCopyToParts(DAG, getCurDebugLoc(), + SDValue(RetOp.getNode(), RetOp.getResNo() + j), &Parts[0], NumParts, PartVT, ExtendKind); // 'inreg' on function refers to return value @@ -949,7 +1008,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { } } } - DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, + DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other, &NewValues[0], NewValues.size())); } @@ -959,7 +1018,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) { // No need to export constants. if (!isa(V) && !isa(V)) return; - + // Already exported? if (FuncInfo.isExportedInst(V)) return; @@ -975,11 +1034,11 @@ bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, // Can export from current BB. if (VI->getParent() == FromBB) return true; - + // Is already exported, noop. return FuncInfo.isExportedInst(V); } - + // If this is an argument, we can export it if the BB is the entry block or // if it is already exported. if (isa(V)) { @@ -989,7 +1048,7 @@ bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V, // Otherwise, can only export this if it is already exported. return FuncInfo.isExportedInst(V); } - + // Otherwise, constants can always be exported. return true; } @@ -1030,7 +1089,7 @@ static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) { } if (FiniteOnlyFPMath()) return FOC; - else + else return FPC; } @@ -1098,7 +1157,7 @@ SelectionDAGLowering::EmitBranchForMergedCondition(Value *Cond, SwitchCases.push_back(CB); } -/// FindMergedConditions - If Cond is an expression like +/// FindMergedConditions - If Cond is an expression like void SelectionDAGLowering::FindMergedConditions(Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, @@ -1106,7 +1165,7 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, unsigned Opc) { // If this node is not part of the or/and tree, emit it as a branch. Instruction *BOp = dyn_cast(Cond); - if (!BOp || !(isa(BOp) || isa(BOp)) || + if (!BOp || !(isa(BOp) || isa(BOp)) || (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || BOp->getParent() != CurBB->getBasicBlock() || !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || @@ -1114,13 +1173,13 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB); return; } - + // Create TmpBB after CurBB. MachineFunction::iterator BBI = CurBB; MachineFunction &MF = DAG.getMachineFunction(); MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); CurBB->getParent()->insert(++BBI, TmpBB); - + if (Opc == Instruction::Or) { // Codegen X | Y as: // jmp_if_X TBB @@ -1129,10 +1188,10 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, // jmp_if_Y TBB // jmp FBB // - + // Emit the LHS condition. FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc); - + // Emit the RHS condition into TmpBB. FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); } else { @@ -1145,10 +1204,10 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, // jmp FBB // // This requires creation of TmpBB after CurBB. - + // Emit the LHS condition. FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc); - + // Emit the RHS condition into TmpBB. FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc); } @@ -1157,10 +1216,10 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond, /// If the set of cases should be emitted as a series of branches, return true. /// If we should emit this as a bunch of and/or'd together conditions, return /// false. -bool +bool SelectionDAGLowering::ShouldEmitAsBranches(const std::vector &Cases){ if (Cases.size() != 2) return true; - + // If this is two comparisons of the same values or'd or and'd together, they // will get folded into a single comparison, so don't emit two blocks. if ((Cases[0].CmpLHS == Cases[1].CmpLHS && @@ -1169,7 +1228,7 @@ SelectionDAGLowering::ShouldEmitAsBranches(const std::vector &Cases){ Cases[0].CmpLHS == Cases[1].CmpRHS)) { return false; } - + return true; } @@ -1186,10 +1245,11 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { if (I.isUnconditional()) { // Update machine-CFG edges. CurMBB->addSuccessor(Succ0MBB); - + // If this is not a fall-through branch, emit the branch. if (Succ0MBB != NextBlock) - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), + MVT::Other, getControlRoot(), DAG.getBasicBlock(Succ0MBB))); return; } @@ -1203,9 +1263,9 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // this as a sequence of branches instead of setcc's with and/or operations. // For example, instead of something like: // cmp A, B - // C = seteq + // C = seteq // cmp D, E - // F = setle + // F = setle // or C, F // jnz foo // Emit: @@ -1215,7 +1275,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // jle foo // if (BinaryOperator *BOp = dyn_cast(CondVal)) { - if (BOp->hasOneUse() && + if (BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And || BOp->getOpcode() == Instruction::Or)) { FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode()); @@ -1223,29 +1283,29 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // exported from this block, export them now. This block should always // be the first entry. assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!"); - + // Allow some cases to be rejected. if (ShouldEmitAsBranches(SwitchCases)) { for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { ExportFromCurrentBlock(SwitchCases[i].CmpLHS); ExportFromCurrentBlock(SwitchCases[i].CmpRHS); } - + // Emit the branch for this block. visitSwitchCase(SwitchCases[0]); SwitchCases.erase(SwitchCases.begin()); return; } - + // Okay, we decided not to do this, remove any inserted MBB's and clear // SwitchCases. for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) CurMBB->getParent()->erase(SwitchCases[i].ThisBB); - + SwitchCases.clear(); } } - + // Create a CaseBlock record representing this branch. CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(), NULL, Succ0MBB, Succ1MBB, CurMBB); @@ -1259,8 +1319,9 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { SDValue Cond; SDValue CondLHS = getValue(CB.CmpLHS); - - // Build the setcc now. + DebugLoc dl = getCurDebugLoc(); + + // Build the setcc now. if (CB.CmpMHS == NULL) { // Fold "(X == true)" to X and "(X == false)" to !X to // handle common cases produced by branch lowering. @@ -1268,61 +1329,64 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { Cond = CondLHS; else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); - Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True); + Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); } else - Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); + Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); } else { assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); - uint64_t Low = cast(CB.CmpLHS)->getSExtValue(); - uint64_t High = cast(CB.CmpRHS)->getSExtValue(); + const APInt& Low = cast(CB.CmpLHS)->getValue(); + const APInt& High = cast(CB.CmpRHS)->getValue(); SDValue CmpOp = getValue(CB.CmpMHS); MVT VT = CmpOp.getValueType(); if (cast(CB.CmpLHS)->isMinValue(true)) { - Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); + Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), + ISD::SETLE); } else { - SDValue SUB = DAG.getNode(ISD::SUB, VT, CmpOp, DAG.getConstant(Low, VT)); - Cond = DAG.getSetCC(MVT::i1, SUB, + SDValue SUB = DAG.getNode(ISD::SUB, dl, + VT, CmpOp, DAG.getConstant(Low, VT)); + Cond = DAG.getSetCC(dl, MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); } } - + // Update successor info CurMBB->addSuccessor(CB.TrueBB); CurMBB->addSuccessor(CB.FalseBB); - + // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. MachineBasicBlock *NextBlock = 0; MachineFunction::iterator BBI = CurMBB; if (++BBI != CurMBB->getParent()->end()) NextBlock = BBI; - + // If the lhs block is the next block, invert the condition so that we can // fall through to the lhs instead of the rhs block. if (CB.TrueBB == NextBlock) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, Cond.getValueType()); - Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); + Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); } - SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), Cond, - DAG.getBasicBlock(CB.TrueBB)); - + SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, + MVT::Other, getControlRoot(), Cond, + DAG.getBasicBlock(CB.TrueBB)); + // If the branch was constant folded, fix up the CFG. if (BrCond.getOpcode() == ISD::BR) { CurMBB->removeSuccessor(CB.FalseBB); DAG.setRoot(BrCond); } else { // Otherwise, go ahead and insert the false branch. - if (BrCond == getControlRoot()) + if (BrCond == getControlRoot()) CurMBB->removeSuccessor(CB.TrueBB); - + if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1332,45 +1396,50 @@ void SelectionDAGLowering::visitJumpTable(JumpTable &JT) { // Emit the code for the jump table assert(JT.Reg != -1U && "Should lower JT Header first!"); MVT PTy = TLI.getPointerTy(); - SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); + SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), + JT.Reg, PTy); SDValue Table = DAG.getJumpTable(JT.JTI, PTy); - DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1), + DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(), + MVT::Other, Index.getValue(1), Table, Index)); - return; } /// visitJumpTableHeader - This function emits necessary code to produce index /// in the JumpTable from switch case. void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH) { - // Subtract the lowest switch case value from the value being switched on - // and conditional branch to default mbb if the result is greater than the + // Subtract the lowest switch case value from the value being switched on and + // conditional branch to default mbb if the result is greater than the // difference between smallest and largest cases. SDValue SwitchOp = getValue(JTH.SValue); MVT VT = SwitchOp.getValueType(); - SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, - DAG.getConstant(JTH.First, VT)); - - // The SDNode we just created, which holds the value being switched on - // minus the the smallest case value, needs to be copied to a virtual - // register so it can be used as an index into the jump table in a - // subsequent basic block. This value may be smaller or larger than the - // target's pointer type, and therefore require extension or truncating. + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, + DAG.getConstant(JTH.First, VT)); + + // The SDNode we just created, which holds the value being switched on minus + // the the smallest case value, needs to be copied to a virtual register so it + // can be used as an index into the jump table in a subsequent basic block. + // This value may be smaller or larger than the target's pointer type, and + // therefore require extension or truncating. if (VT.bitsGT(TLI.getPointerTy())) - SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB); + SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), SUB); else - SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB); - + SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), + TLI.getPointerTy(), SUB); + unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), JumpTableReg, SwitchOp); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), + JumpTableReg, SwitchOp); JT.Reg = JumpTableReg; - // Emit the range check for the jump table, and branch to the default - // block for the switch statement if the value being switched on exceeds - // the largest case in the switch. - SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, - DAG.getConstant(JTH.Last-JTH.First,VT), - ISD::SETUGT); + // Emit the range check for the jump table, and branch to the default block + // for the switch statement if the value being switched on exceeds the largest + // case in the switch. + SDValue CMP = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), SUB, + DAG.getConstant(JTH.Last-JTH.First,VT), + ISD::SETUGT); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1379,16 +1448,15 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, if (++BBI != CurMBB->getParent()->end()) NextBlock = BBI; - SDValue BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP, - DAG.getBasicBlock(JT.Default)); + SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), + MVT::Other, CopyTo, CMP, + DAG.getBasicBlock(JT.Default)); if (JT.MBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, DAG.getBasicBlock(JT.MBB))); - - return; } /// visitBitTestHeader - This function emits necessary code to produce value @@ -1397,28 +1465,26 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { // Subtract the minimum value SDValue SwitchOp = getValue(B.SValue); MVT VT = SwitchOp.getValueType(); - SDValue SUB = DAG.getNode(ISD::SUB, VT, SwitchOp, - DAG.getConstant(B.First, VT)); + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, + DAG.getConstant(B.First, VT)); // Check range - SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB), SUB, - DAG.getConstant(B.Range, VT), - ISD::SETUGT); + SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), + SUB, DAG.getConstant(B.Range, VT), + ISD::SETUGT); SDValue ShiftOp; - if (VT.bitsGT(TLI.getShiftAmountTy())) - ShiftOp = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), SUB); + if (VT.bitsGT(TLI.getPointerTy())) + ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), SUB); else - ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), SUB); + ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), + TLI.getPointerTy(), SUB); - // Make desired shift - SDValue SwitchVal = DAG.getNode(ISD::SHL, TLI.getPointerTy(), - DAG.getConstant(1, TLI.getPointerTy()), - ShiftOp); - - unsigned SwitchReg = FuncInfo.MakeReg(TLI.getPointerTy()); - SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), SwitchReg, SwitchVal); - B.Reg = SwitchReg; + B.Reg = FuncInfo.MakeReg(TLI.getPointerTy()); + SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), + B.Reg, ShiftOp); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1432,37 +1498,44 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { CurMBB->addSuccessor(B.Default); CurMBB->addSuccessor(MBB); - SDValue BrRange = DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, RangeCmp, - DAG.getBasicBlock(B.Default)); - + SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), + MVT::Other, CopyTo, RangeCmp, + DAG.getBasicBlock(B.Default)); + if (MBB == NextBlock) DAG.setRoot(BrRange); else - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, CopyTo, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, DAG.getBasicBlock(MBB))); - - return; } /// visitBitTestCase - this function produces one "bit test" void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, unsigned Reg, BitTestCase &B) { + // Make desired shift + SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg, + TLI.getPointerTy()); + SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), + TLI.getPointerTy(), + DAG.getConstant(1, TLI.getPointerTy()), + ShiftOp); + // Emit bit tests and jumps - SDValue SwitchVal = DAG.getCopyFromReg(getControlRoot(), Reg, - TLI.getPointerTy()); - - SDValue AndOp = DAG.getNode(ISD::AND, TLI.getPointerTy(), SwitchVal, - DAG.getConstant(B.Mask, TLI.getPointerTy())); - SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp), AndOp, - DAG.getConstant(0, TLI.getPointerTy()), - ISD::SETNE); + SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), + TLI.getPointerTy(), SwitchVal, + DAG.getConstant(B.Mask, TLI.getPointerTy())); + SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(AndOp.getValueType()), + AndOp, DAG.getConstant(0, TLI.getPointerTy()), + ISD::SETNE); CurMBB->addSuccessor(B.TargetBB); CurMBB->addSuccessor(NextMBB); - - SDValue BrAnd = DAG.getNode(ISD::BRCOND, MVT::Other, getControlRoot(), - AndCmp, DAG.getBasicBlock(B.TargetBB)); + + SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), + MVT::Other, getControlRoot(), + AndCmp, DAG.getBasicBlock(B.TargetBB)); // Set NextBlock to be the MBB immediately after the current one, if any. // This is used to avoid emitting unnecessary branches to the next block. @@ -1474,10 +1547,8 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, if (NextMBB == NextBlock) DAG.setRoot(BrAnd); else - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrAnd, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, DAG.getBasicBlock(NextMBB))); - - return; } void SelectionDAGLowering::visitInvoke(InvokeInst &I) { @@ -1485,10 +1556,11 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) { MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; - if (isa(I.getCalledValue())) + const Value *Callee(I.getCalledValue()); + if (isa(Callee)) visitInlineAsm(&I); else - LowerCallTo(&I, getValue(I.getOperand(0)), false, LandingPad); + LowerCallTo(&I, getValue(Callee), false, LandingPad); // If the value of the invoke is used outside of its defining block, make it // available as a virtual register. @@ -1503,7 +1575,8 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) { CurMBB->addSuccessor(LandingPad); // Drop into normal successor. - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), + MVT::Other, getControlRoot(), DAG.getBasicBlock(Return))); } @@ -1517,15 +1590,15 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, Value* SV, MachineBasicBlock* Default) { Case& BackCase = *(CR.Range.second-1); - + // Size is the number of Cases represented by this range. - unsigned Size = CR.Range.second - CR.Range.first; + size_t Size = CR.Range.second - CR.Range.first; if (Size > 3) - return false; - + return false; + // Get the MachineFunction which holds the current MBB. This is used when // inserting any additional MBBs necessary to represent the switch. - MachineFunction *CurMF = CurMBB->getParent(); + MachineFunction *CurMF = CurMBB->getParent(); // Figure out which block is immediately after the current one. MachineBasicBlock *NextBlock = 0; @@ -1538,7 +1611,7 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, // is the same as the other, but has one bit unset that the other has set, // use bit manipulation to do two compares at once. For example: // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" - + // Rearrange the case blocks so that the last one falls through if possible. if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { // The last case block won't fall through into 'NextBlock' if we emit the @@ -1550,7 +1623,7 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, } } } - + // Create a CaseBlock record representing a conditional branch to // the Case's target mbb if the value being switched on SV is equal // to C. @@ -1576,7 +1649,7 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, LHS = I->Low; MHS = SV; RHS = I->High; } CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock); - + // If emitting the first comparison, just call visitSwitchCase to emit the // code into the current block. Otherwise, push the CaseBlock onto the // vector to be later processed by SDISel, and insert the node's MBB @@ -1585,7 +1658,7 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, visitSwitchCase(CB); else SwitchCases.push_back(CB); - + CurBlock = FallThrough; } @@ -1594,10 +1667,17 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, static inline bool areJTsAllowed(const TargetLowering &TLI) { return !DisableJumpTables && - (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || - TLI.isOperationLegal(ISD::BRIND, MVT::Other)); + (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || + TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); +} + +static APInt ComputeRange(const APInt &First, const APInt &Last) { + APInt LastExt(Last), FirstExt(First); + uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; + LastExt.sext(BitWidth); FirstExt.sext(BitWidth); + return (LastExt - FirstExt + 1ULL); } - + /// handleJTSwitchCase - Emit jumptable for current switch case range bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, CaseRecVector& WorkList, @@ -1606,24 +1686,26 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, Case& FrontCase = *CR.Range.first; Case& BackCase = *(CR.Range.second-1); - int64_t First = cast(FrontCase.Low)->getSExtValue(); - int64_t Last = cast(BackCase.High)->getSExtValue(); + const APInt& First = cast(FrontCase.Low)->getValue(); + const APInt& Last = cast(BackCase.High)->getValue(); - uint64_t TSize = 0; + size_t TSize = 0; for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) TSize += I->size(); if (!areJTsAllowed(TLI) || TSize <= 3) return false; - - double Density = (double)TSize / (double)((Last - First) + 1ULL); + + APInt Range = ComputeRange(First, Last); + double Density = (double)TSize / Range.roundToDouble(); if (Density < 0.4) return false; - DOUT << "Lowering jump table\n" - << "First entry: " << First << ". Last entry: " << Last << "\n" - << "Size: " << TSize << ". Density: " << Density << "\n\n"; + DEBUG(errs() << "Lowering jump table\n" + << "First entry: " << First << ". Last entry: " << Last << '\n' + << "Range: " << Range + << "Size: " << TSize << ". Density: " << Density << "\n\n"); // Get the MachineFunction which holds the current MBB. This is used when // inserting any additional MBBs necessary to represent the switch. @@ -1646,18 +1728,18 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, CurMF->insert(BBI, JumpTableBB); CR.CaseBB->addSuccessor(Default); CR.CaseBB->addSuccessor(JumpTableBB); - + // Build a vector of destination BBs, corresponding to each target // of the jump table. If the value of the jump table slot corresponds to // a case statement, push the case's BB onto the vector, otherwise, push // the default BB. std::vector DestBBs; - int64_t TEI = First; + APInt TEI = First; for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { - int64_t Low = cast(I->Low)->getSExtValue(); - int64_t High = cast(I->High)->getSExtValue(); - - if ((Low <= TEI) && (TEI <= High)) { + const APInt& Low = cast(I->Low)->getValue(); + const APInt& High = cast(I->High)->getValue(); + + if (Low.sle(TEI) && TEI.sle(High)) { DestBBs.push_back(I->BB); if (TEI==High) ++I; @@ -1665,28 +1747,28 @@ bool SelectionDAGLowering::handleJTSwitchCase(CaseRec& CR, DestBBs.push_back(Default); } } - + // Update successor info. Add one edge to each unique successor. - BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); - for (std::vector::iterator I = DestBBs.begin(), + BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); + for (std::vector::iterator I = DestBBs.begin(), E = DestBBs.end(); I != E; ++I) { if (!SuccsHandled[(*I)->getNumber()]) { SuccsHandled[(*I)->getNumber()] = true; JumpTableBB->addSuccessor(*I); } } - + // Create a jump table index for this jump table, or return an existing // one. unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs); - + // Set the jump table information so that we can codegen it as a second // MachineBasicBlock JumpTable JT(-1U, JTI, JumpTableBB, Default); JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == CurMBB)); if (CR.CaseBB == CurMBB) visitJumpTableHeader(JT, JTH); - + JTCases.push_back(JumpTableBlock(JTH, JT)); return true; @@ -1700,7 +1782,7 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, MachineBasicBlock* Default) { // Get the MachineFunction which holds the current MBB. This is used when // inserting any additional MBBs necessary to represent the switch. - MachineFunction *CurMF = CurMBB->getParent(); + MachineFunction *CurMF = CurMBB->getParent(); // Figure out which block is immediately after the current one. MachineBasicBlock *NextBlock = 0; @@ -1716,40 +1798,43 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, // Size is the number of Cases represented by this range. unsigned Size = CR.Range.second - CR.Range.first; - int64_t First = cast(FrontCase.Low)->getSExtValue(); - int64_t Last = cast(BackCase.High)->getSExtValue(); + const APInt& First = cast(FrontCase.Low)->getValue(); + const APInt& Last = cast(BackCase.High)->getValue(); double FMetric = 0; CaseItr Pivot = CR.Range.first + Size/2; // Select optimal pivot, maximizing sum density of LHS and RHS. This will // (heuristically) allow us to emit JumpTable's later. - uint64_t TSize = 0; + size_t TSize = 0; for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) TSize += I->size(); - uint64_t LSize = FrontCase.size(); - uint64_t RSize = TSize-LSize; - DOUT << "Selecting best pivot: \n" - << "First: " << First << ", Last: " << Last <<"\n" - << "LSize: " << LSize << ", RSize: " << RSize << "\n"; + size_t LSize = FrontCase.size(); + size_t RSize = TSize-LSize; + DEBUG(errs() << "Selecting best pivot: \n" + << "First: " << First << ", Last: " << Last <<'\n' + << "LSize: " << LSize << ", RSize: " << RSize << '\n'); for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; J!=E; ++I, ++J) { - int64_t LEnd = cast(I->High)->getSExtValue(); - int64_t RBegin = cast(J->Low)->getSExtValue(); - assert((RBegin-LEnd>=1) && "Invalid case distance"); - double LDensity = (double)LSize / (double)((LEnd - First) + 1ULL); - double RDensity = (double)RSize / (double)((Last - RBegin) + 1ULL); - double Metric = Log2_64(RBegin-LEnd)*(LDensity+RDensity); + const APInt& LEnd = cast(I->High)->getValue(); + const APInt& RBegin = cast(J->Low)->getValue(); + APInt Range = ComputeRange(LEnd, RBegin); + assert((Range - 2ULL).isNonNegative() && + "Invalid case distance"); + double LDensity = (double)LSize / (LEnd - First + 1ULL).roundToDouble(); + double RDensity = (double)RSize / (Last - RBegin + 1ULL).roundToDouble(); + double Metric = Range.logBase2()*(LDensity+RDensity); // Should always split in some non-trivial place - DOUT <<"=>Step\n" - << "LEnd: " << LEnd << ", RBegin: " << RBegin << "\n" - << "LDensity: " << LDensity << ", RDensity: " << RDensity << "\n" - << "Metric: " << Metric << "\n"; + DEBUG(errs() <<"=>Step\n" + << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' + << "LDensity: " << LDensity + << ", RDensity: " << RDensity << '\n' + << "Metric: " << Metric << '\n'); if (FMetric < Metric) { Pivot = J; FMetric = Metric; - DOUT << "Current metric set to: " << FMetric << "\n"; + DEBUG(errs() << "Current metric set to: " << FMetric << '\n'); } LSize += J->size(); @@ -1761,36 +1846,36 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, } else { Pivot = CR.Range.first + Size/2; } - + CaseRange LHSR(CR.Range.first, Pivot); CaseRange RHSR(Pivot, CR.Range.second); Constant *C = Pivot->Low; MachineBasicBlock *FalseBB = 0, *TrueBB = 0; - + // We know that we branch to the LHS if the Value being switched on is - // less than the Pivot value, C. We use this to optimize our binary + // less than the Pivot value, C. We use this to optimize our binary // tree a bit, by recognizing that if SV is greater than or equal to the - // LHS's Case Value, and that Case Value is exactly one less than the + // LHS's Case Value, and that Case Value is exactly one less than the // Pivot's Value, then we can branch directly to the LHS's Target, // rather than creating a leaf node for it. if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE && - cast(C)->getSExtValue() == - (cast(CR.GE)->getSExtValue() + 1LL)) { + cast(C)->getValue() == + (cast(CR.GE)->getValue() + 1LL)) { TrueBB = LHSR.first->BB; } else { TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); CurMF->insert(BBI, TrueBB); WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); } - + // Similar to the optimization above, if the Value being switched on is // known to be less than the Constant CR.LT, and the current Case Value // is CR.LT - 1, then we can branch directly to the target block for // the current Case Value, rather than emitting a RHS leaf node for it. if ((RHSR.second - RHSR.first) == 1 && CR.LT && - cast(RHSR.first->Low)->getSExtValue() == - (cast(CR.LT)->getSExtValue() - 1LL)) { + cast(RHSR.first->Low)->getValue() == + (cast(CR.LT)->getValue() - 1LL)) { FalseBB = RHSR.first->BB; } else { FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); @@ -1799,7 +1884,7 @@ bool SelectionDAGLowering::handleBTSplitSwitchCase(CaseRec& CR, } // Create a CaseBlock record representing a conditional branch to - // the LHS node if the value being switched on SV is less than C. + // the LHS node if the value being switched on SV is less than C. // Otherwise, branch to LHS. CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); @@ -1825,18 +1910,15 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, // Get the MachineFunction which holds the current MBB. This is used when // inserting any additional MBBs necessary to represent the switch. - MachineFunction *CurMF = CurMBB->getParent(); + MachineFunction *CurMF = CurMBB->getParent(); - unsigned numCmps = 0; + size_t numCmps = 0; for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { // Single case counts one, case range - two. - if (I->Low == I->High) - numCmps +=1; - else - numCmps +=2; + numCmps += (I->Low == I->High ? 1 : 2); } - + // Count unique destinations SmallSet Dests; for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { @@ -1845,37 +1927,37 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, // Don't bother the code below, if there are too much unique destinations return false; } - DOUT << "Total number of unique destinations: " << Dests.size() << "\n" - << "Total number of comparisons: " << numCmps << "\n"; - + DEBUG(errs() << "Total number of unique destinations: " << Dests.size() << '\n' + << "Total number of comparisons: " << numCmps << '\n'); + // Compute span of values. - Constant* minValue = FrontCase.Low; - Constant* maxValue = BackCase.High; - uint64_t range = cast(maxValue)->getSExtValue() - - cast(minValue)->getSExtValue(); - DOUT << "Compare range: " << range << "\n" - << "Low bound: " << cast(minValue)->getSExtValue() << "\n" - << "High bound: " << cast(maxValue)->getSExtValue() << "\n"; - - if (range>=IntPtrBits || + const APInt& minValue = cast(FrontCase.Low)->getValue(); + const APInt& maxValue = cast(BackCase.High)->getValue(); + APInt cmpRange = maxValue - minValue; + + DEBUG(errs() << "Compare range: " << cmpRange << '\n' + << "Low bound: " << minValue << '\n' + << "High bound: " << maxValue << '\n'); + + if (cmpRange.uge(APInt(cmpRange.getBitWidth(), IntPtrBits)) || (!(Dests.size() == 1 && numCmps >= 3) && !(Dests.size() == 2 && numCmps >= 5) && !(Dests.size() >= 3 && numCmps >= 6))) return false; - - DOUT << "Emitting bit tests\n"; - int64_t lowBound = 0; - + + DEBUG(errs() << "Emitting bit tests\n"); + APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); + // Optimize the case where all the case values fit in a // word without having to subtract minValue. In this case, // we can optimize away the subtraction. - if (cast(minValue)->getSExtValue() >= 0 && - cast(maxValue)->getSExtValue() < IntPtrBits) { - range = cast(maxValue)->getSExtValue(); + if (minValue.isNonNegative() && + maxValue.slt(APInt(maxValue.getBitWidth(), IntPtrBits))) { + cmpRange = maxValue; } else { - lowBound = cast(minValue)->getSExtValue(); + lowBound = minValue; } - + CaseBitsVector CasesBits; unsigned i, count = 0; @@ -1884,24 +1966,27 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, for (i = 0; i < count; ++i) if (Dest == CasesBits[i].BB) break; - + if (i == count) { assert((count < 3) && "Too much destinations to test!"); CasesBits.push_back(CaseBits(0, Dest, 0)); count++; } - - uint64_t lo = cast(I->Low)->getSExtValue() - lowBound; - uint64_t hi = cast(I->High)->getSExtValue() - lowBound; - + + const APInt& lowValue = cast(I->Low)->getValue(); + const APInt& highValue = cast(I->High)->getValue(); + + uint64_t lo = (lowValue - lowBound).getZExtValue(); + uint64_t hi = (highValue - lowBound).getZExtValue(); + for (uint64_t j = lo; j <= hi; j++) { CasesBits[i].Mask |= 1ULL << j; CasesBits[i].Bits++; } - + } std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); - + BitTestInfo BTC; // Figure out which block is immediately after the current one. @@ -1910,10 +1995,11 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); - DOUT << "Cases:\n"; + DEBUG(errs() << "Cases:\n"); for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { - DOUT << "Mask: " << CasesBits[i].Mask << ", Bits: " << CasesBits[i].Bits - << ", BB: " << CasesBits[i].BB << "\n"; + DEBUG(errs() << "Mask: " << CasesBits[i].Mask + << ", Bits: " << CasesBits[i].Bits + << ", BB: " << CasesBits[i].BB << '\n'); MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); CurMF->insert(BBI, CaseBB); @@ -1921,14 +2007,14 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, CaseBB, CasesBits[i].BB)); } - - BitTestBlock BTB(lowBound, range, SV, + + BitTestBlock BTB(lowBound, cmpRange, SV, -1U, (CR.CaseBB == CurMBB), CR.CaseBB, Default, BTC); if (CR.CaseBB == CurMBB) visitBitTestHeader(BTB); - + BitTestCases.push_back(BTB); return true; @@ -1936,12 +2022,12 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, /// Clusterify - Transform simple list of Cases into list of CaseRange's -unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, +size_t SelectionDAGLowering::Clusterify(CaseVector& Cases, const SwitchInst& SI) { - unsigned numCmps = 0; + size_t numCmps = 0; // Start with "simple" cases - for (unsigned i = 1; i < SI.getNumSuccessors(); ++i) { + for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)]; Cases.push_back(Case(SI.getSuccessorValue(i), SI.getSuccessorValue(i), @@ -1950,18 +2036,18 @@ unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, std::sort(Cases.begin(), Cases.end(), CaseCmp()); // Merge case into clusters - if (Cases.size()>=2) + if (Cases.size() >= 2) // Must recompute end() each iteration because it may be // invalidated by erase if we hold on to it - for (CaseItr I=Cases.begin(), J=++(Cases.begin()); J!=Cases.end(); ) { - int64_t nextValue = cast(J->Low)->getSExtValue(); - int64_t currentValue = cast(I->High)->getSExtValue(); + for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) { + const APInt& nextValue = cast(J->Low)->getValue(); + const APInt& currentValue = cast(I->High)->getValue(); MachineBasicBlock* nextBB = J->BB; MachineBasicBlock* currentBB = I->BB; // If the two neighboring cases go to the same destination, merge them // into a single case. - if ((nextValue-currentValue==1) && (currentBB == nextBB)) { + if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { I->High = J->High; J = Cases.erase(J); } else { @@ -1978,7 +2064,7 @@ unsigned SelectionDAGLowering::Clusterify(CaseVector& Cases, return numCmps; } -void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { +void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { // Figure out which block is immediately after the current one. MachineBasicBlock *NextBlock = 0; MachineFunction::iterator BBI = CurMBB; @@ -1993,19 +2079,20 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { // If this is not a fall-through branch, emit the branch. CurMBB->addSuccessor(Default); if (Default != NextBlock) - DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getControlRoot(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), + MVT::Other, getControlRoot(), DAG.getBasicBlock(Default))); - return; } - + // If there are any non-default case statements, create a vector of Cases // representing each one, and sort the vector so that we can efficiently // create a binary search tree from them. CaseVector Cases; - unsigned numCmps = Clusterify(Cases, SI); - DOUT << "Clusterify finished. Total clusters: " << Cases.size() - << ". Total compares: " << numCmps << "\n"; + size_t numCmps = Clusterify(Cases, SI); + DEBUG(errs() << "Clusterify finished. Total clusters: " << Cases.size() + << ". Total compares: " << numCmps << '\n'); + numCmps = 0; // Get the Value to be switched on and default basic blocks, which will be // inserted into CaseBlock records, representing basic blocks in the binary @@ -2023,18 +2110,18 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { if (handleBitTestsSwitchCase(CR, WorkList, SV, Default)) continue; - + // If the range has few cases (two or less) emit a series of specific // tests. if (handleSmallSwitchRange(CR, WorkList, SV, Default)) continue; - - // If the switch has more than 5 blocks, and at least 40% dense, and the - // target supports indirect branches, then emit a jump table rather than + + // If the switch has more than 5 blocks, and at least 40% dense, and the + // target supports indirect branches, then emit a jump table rather than // lowering the switch to a binary tree of conditional branches. if (handleJTSwitchCase(CR, WorkList, SV, Default)) continue; - + // Emit binary tree. We need to pick a pivot, and push left and right ranges // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. handleBTSplitSwitchCase(CR, WorkList, SV, Default); @@ -2055,7 +2142,8 @@ void SelectionDAGLowering::visitSub(User &I) { Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); if (CV == CNZ) { SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); + setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), + Op2.getValueType(), Op2)); return; } } @@ -2065,7 +2153,8 @@ void SelectionDAGLowering::visitSub(User &I) { if (ConstantFP *CFP = dyn_cast(I.getOperand(0))) if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2)); + setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), + Op2.getValueType(), Op2)); return; } } @@ -2076,21 +2165,25 @@ void SelectionDAGLowering::visitSub(User &I) { void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); - - setValue(&I, DAG.getNode(OpCode, Op1.getValueType(), Op1, Op2)); + + setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), + Op1.getValueType(), Op1, Op2)); } void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); if (!isa(I.getType())) { - if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) - Op2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Op2); - else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) - Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2); + if (TLI.getPointerTy().bitsLT(Op2.getValueType())) + Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + TLI.getPointerTy(), Op2); + else if (TLI.getPointerTy().bitsGT(Op2.getValueType())) + Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), + TLI.getPointerTy(), Op2); } - - setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2)); + + setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), + Op1.getValueType(), Op1, Op2)); } void SelectionDAGLowering::visitICmp(User &I) { @@ -2102,7 +2195,7 @@ void SelectionDAGLowering::visitICmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode)); } void SelectionDAGLowering::visitFCmp(User &I) { @@ -2114,7 +2207,7 @@ void SelectionDAGLowering::visitFCmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Condition = getFCmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition)); } void SelectionDAGLowering::visitVICmp(User &I) { @@ -2126,7 +2219,8 @@ void SelectionDAGLowering::visitVICmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(), + Op1, Op2, Opcode)); } void SelectionDAGLowering::visitVFCmp(User &I) { @@ -2139,8 +2233,8 @@ void SelectionDAGLowering::visitVFCmp(User &I) { SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Condition = getFCmpCondCode(predicate); MVT DestVT = TLI.getValueType(I.getType()); - - setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); + + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); } void SelectionDAGLowering::visitSelect(User &I) { @@ -2154,12 +2248,14 @@ void SelectionDAGLowering::visitSelect(User &I) { SDValue FalseVal = getValue(I.getOperand(2)); for (unsigned i = 0; i != NumValues; ++i) - Values[i] = DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond, + Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), + TrueVal.getValueType(), Cond, SDValue(TrueVal.getNode(), TrueVal.getResNo() + i), SDValue(FalseVal.getNode(), FalseVal.getResNo() + i)); - setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), - &Values[0], NumValues)); + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), + DAG.getVTList(&ValueVTs[0], NumValues), + &Values[0], NumValues)); } } @@ -2168,7 +2264,7 @@ void SelectionDAGLowering::visitTrunc(User &I) { // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); + setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitZExt(User &I) { @@ -2176,7 +2272,7 @@ void SelectionDAGLowering::visitZExt(User &I) { // ZExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitSExt(User &I) { @@ -2184,49 +2280,50 @@ void SelectionDAGLowering::visitSExt(User &I) { // SExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N)); + setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPTrunc(User &I) { // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0))); + setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), + DestVT, N, DAG.getIntPtrConstant(0))); } -void SelectionDAGLowering::visitFPExt(User &I){ +void SelectionDAGLowering::visitFPExt(User &I){ // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); } -void SelectionDAGLowering::visitFPToUI(User &I) { +void SelectionDAGLowering::visitFPToUI(User &I) { // FPToUI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToSI(User &I) { // FPToSI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); } -void SelectionDAGLowering::visitUIToFP(User &I) { +void SelectionDAGLowering::visitUIToFP(User &I) { // UIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N)); + setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); } -void SelectionDAGLowering::visitSIToFP(User &I){ +void SelectionDAGLowering::visitSIToFP(User &I){ // SIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); + setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitPtrToInt(User &I) { @@ -2237,10 +2334,10 @@ void SelectionDAGLowering::visitPtrToInt(User &I) { MVT DestVT = TLI.getValueType(I.getType()); SDValue Result; if (DestVT.bitsLT(SrcVT)) - Result = DAG.getNode(ISD::TRUNCATE, DestVT, N); - else + Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N); + else // Note: ZERO_EXTEND can handle cases where the sizes are equal too - Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N); + Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N); setValue(&I, Result); } @@ -2251,20 +2348,22 @@ void SelectionDAGLowering::visitIntToPtr(User &I) { MVT SrcVT = N.getValueType(); MVT DestVT = TLI.getValueType(I.getType()); if (DestVT.bitsLT(SrcVT)) - setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N)); - else + setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); + else // Note: ZERO_EXTEND can handle cases where the sizes are equal too - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N)); + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), + DestVT, N)); } -void SelectionDAGLowering::visitBitCast(User &I) { +void SelectionDAGLowering::visitBitCast(User &I) { SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - // BitCast assures us that source and destination are the same size so this + // BitCast assures us that source and destination are the same size so this // is either a BIT_CONVERT or a no-op. if (DestVT != N.getValueType()) - setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types + setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), + DestVT, N)); // convert types else setValue(&I, N); // noop cast. } @@ -2272,19 +2371,21 @@ void SelectionDAGLowering::visitBitCast(User &I) { void SelectionDAGLowering::visitInsertElement(User &I) { SDValue InVec = getValue(I.getOperand(0)); SDValue InVal = getValue(I.getOperand(1)); - SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), + SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), + TLI.getPointerTy(), getValue(I.getOperand(2))); - setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, + setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), TLI.getValueType(I.getType()), InVec, InVal, InIdx)); } void SelectionDAGLowering::visitExtractElement(User &I) { SDValue InVec = getValue(I.getOperand(0)); - SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), + SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), + TLI.getPointerTy(), getValue(I.getOperand(1))); - setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, + setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), TLI.getValueType(I.getType()), InVec, InIdx)); } @@ -2314,7 +2415,8 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { int SrcNumElts = SrcVT.getVectorNumElements(); if (SrcNumElts == MaskNumElts) { - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Src1, Src2, Mask)); + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), + VT, Src1, Src2, Mask)); return; } @@ -2327,13 +2429,14 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { // lengths match. if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { // The shuffle is concatenating two vectors together. - setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, VT, Src1, Src2)); + setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), + VT, Src1, Src2)); return; } // Pad both vectors with undefs to make them the same length as the mask. unsigned NumConcat = MaskNumElts / SrcNumElts; - SDValue UndefVal = DAG.getNode(ISD::UNDEF, SrcVT); + SDValue UndefVal = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), SrcVT); SDValue* MOps1 = new SDValue[NumConcat]; SDValue* MOps2 = new SDValue[NumConcat]; @@ -2343,8 +2446,10 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { MOps1[i] = UndefVal; MOps2[i] = UndefVal; } - Src1 = DAG.getNode(ISD::CONCAT_VECTORS, VT, MOps1, NumConcat); - Src2 = DAG.getNode(ISD::CONCAT_VECTORS, VT, MOps2, NumConcat); + Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), + VT, MOps1, NumConcat); + Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), + VT, MOps2, NumConcat); delete [] MOps1; delete [] MOps2; @@ -2363,10 +2468,12 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { MaskEltVT)); } } - Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), + Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), + Mask.getValueType(), &MappedOps[0], MappedOps.size()); - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Src1, Src2, Mask)); + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), + VT, Src1, Src2, Mask)); return; } @@ -2423,14 +2530,16 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { StartIdx[Input] = 0; } else { StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; - if (MaxRange[Input] - StartIdx[Input] < MaskNumElts) + if (MaxRange[Input] - StartIdx[Input] < MaskNumElts && + StartIdx[Input] + MaskNumElts < SrcNumElts) RangeUse[Input] = 1; // Extract from a multiple of the mask length. } } } if (RangeUse[0] == 0 && RangeUse[0] == 0) { - setValue(&I, DAG.getNode(ISD::UNDEF, VT)); // Vectors are not used. + setValue(&I, DAG.getNode(ISD::UNDEF, + getCurDebugLoc(), VT)); // Vectors are not used. return; } else if (RangeUse[0] < 2 && RangeUse[1] < 2) { @@ -2438,10 +2547,10 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { for (int Input=0; Input < 2; ++Input) { SDValue& Src = Input == 0 ? Src1 : Src2; if (RangeUse[Input] == 0) { - Src = DAG.getNode(ISD::UNDEF, VT); + Src = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); } else { - Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, VT, Src, - DAG.getIntPtrConstant(StartIdx[Input])); + Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, + Src, DAG.getIntPtrConstant(StartIdx[Input])); } } // Calculate new mask. @@ -2457,12 +2566,14 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { else { Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts; MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT)); - } + } } } - Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(), + Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), + Mask.getValueType(), &MappedOps[0], MappedOps.size()); - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Src1, Src2, Mask)); + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), + VT, Src1, Src2, Mask)); return; } } @@ -2476,19 +2587,21 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { for (int i = 0; i != MaskNumElts; ++i) { SDValue Arg = Mask.getOperand(i); if (Arg.getOpcode() == ISD::UNDEF) { - Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); + Ops.push_back(DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT)); } else { assert(isa(Arg) && "Invalid VECTOR_SHUFFLE mask!"); int Idx = cast(Arg)->getZExtValue(); if (Idx < SrcNumElts) - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Src1, - DAG.getConstant(Idx, PtrVT))); + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), + EltVT, Src1, DAG.getConstant(Idx, PtrVT))); else - Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Src2, + Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), + EltVT, Src2, DAG.getConstant(Idx - SrcNumElts, PtrVT))); } } - setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size())); + setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), + VT, &Ops[0], Ops.size())); } void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { @@ -2516,19 +2629,23 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { unsigned i = 0; // Copy the beginning value(s) from the original aggregate. for (; i != LinearIndex; ++i) - Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : + Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), + AggValueVTs[i]) : SDValue(Agg.getNode(), Agg.getResNo() + i); // Copy values from the inserted value(s). for (; i != LinearIndex + NumValValues; ++i) - Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : + Values[i] = FromUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), + AggValueVTs[i]) : SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); // Copy remaining value(s) from the original aggregate. for (; i != NumAggValues; ++i) - Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, AggValueVTs[i]) : + Values[i] = IntoUndef ? DAG.getNode(ISD::UNDEF, getCurDebugLoc(), + AggValueVTs[i]) : SDValue(Agg.getNode(), Agg.getResNo() + i); - setValue(&I, DAG.getMergeValues(DAG.getVTList(&AggValueVTs[0], NumAggValues), - &Values[0], NumAggValues)); + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), + DAG.getVTList(&AggValueVTs[0], NumAggValues), + &Values[0], NumAggValues)); } void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { @@ -2551,12 +2668,13 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) Values[i - LinearIndex] = OutOfUndef ? - DAG.getNode(ISD::UNDEF, + DAG.getNode(ISD::UNDEF, getCurDebugLoc(), Agg.getNode()->getValueType(Agg.getResNo() + i)) : SDValue(Agg.getNode(), Agg.getResNo() + i); - setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValValueVTs[0], NumValValues), - &Values[0], NumValValues)); + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), + DAG.getVTList(&ValValueVTs[0], NumValValues), + &Values[0], NumValValues)); } @@ -2572,7 +2690,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) { if (Field) { // N = N + Offset uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); - N = DAG.getNode(ISD::ADD, N.getValueType(), N, + N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, DAG.getIntPtrConstant(Offset)); } Ty = StTy->getElementType(Field); @@ -2582,38 +2700,43 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) { // If this is a constant subscript, handle it quickly. if (ConstantInt *CI = dyn_cast(Idx)) { if (CI->getZExtValue() == 0) continue; - uint64_t Offs = - TD->getABITypeSize(Ty)*cast(CI)->getSExtValue(); - N = DAG.getNode(ISD::ADD, N.getValueType(), N, + uint64_t Offs = + TD->getTypePaddedSize(Ty)*cast(CI)->getSExtValue(); + N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, DAG.getIntPtrConstant(Offs)); continue; } - + // N = N + Idx * ElementSize; - uint64_t ElementSize = TD->getABITypeSize(Ty); + uint64_t ElementSize = TD->getTypePaddedSize(Ty); SDValue IdxN = getValue(Idx); // If the index is smaller or larger than intptr_t, truncate or extend // it. if (IdxN.getValueType().bitsLT(N.getValueType())) - IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN); + IdxN = DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), + N.getValueType(), IdxN); else if (IdxN.getValueType().bitsGT(N.getValueType())) - IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN); + IdxN = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + N.getValueType(), IdxN); // If this is a multiply by a power of two, turn it into a shl // immediately. This is a very common case. if (ElementSize != 1) { if (isPowerOf2_64(ElementSize)) { unsigned Amt = Log2_64(ElementSize); - IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN, - DAG.getConstant(Amt, TLI.getShiftAmountTy())); + IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), + N.getValueType(), IdxN, + DAG.getConstant(Amt, TLI.getPointerTy())); } else { SDValue Scale = DAG.getIntPtrConstant(ElementSize); - IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale); + IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), + N.getValueType(), IdxN, Scale); } } - N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN); + N = DAG.getNode(ISD::ADD, getCurDebugLoc(), + N.getValueType(), N, IdxN); } } setValue(&I, N); @@ -2626,7 +2749,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { return; // getValue will auto-populate this. const Type *Ty = I.getAllocatedType(); - uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); + uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty); unsigned Align = std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), I.getAlignment()); @@ -2634,11 +2757,13 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { SDValue AllocSize = getValue(I.getArraySize()); MVT IntPtr = TLI.getPointerTy(); if (IntPtr.bitsLT(AllocSize.getValueType())) - AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize); + AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), + IntPtr, AllocSize); else if (IntPtr.bitsGT(AllocSize.getValueType())) - AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize); + AllocSize = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), + IntPtr, AllocSize); - AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize, + AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, AllocSize, DAG.getIntPtrConstant(TySize)); // Handle alignment. If the requested alignment is less than or equal to @@ -2651,16 +2776,19 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { // Round the size of the allocation up to the stack alignment size // by add SA-1 to the size. - AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize, + AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), + AllocSize.getValueType(), AllocSize, DAG.getIntPtrConstant(StackAlign-1)); // Mask out the low bits for alignment purposes. - AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize, + AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), + AllocSize.getValueType(), AllocSize, DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; const MVT *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(), MVT::Other); - SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3); + SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), + VTs, 2, Ops, 3); setValue(&I, DSA); DAG.setRoot(DSA.getValue(1)); @@ -2702,17 +2830,19 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { SmallVector Chains(NumValues); MVT PtrVT = Ptr.getValueType(); for (unsigned i = 0; i != NumValues; ++i) { - SDValue L = DAG.getLoad(ValueVTs[i], Root, - DAG.getNode(ISD::ADD, PtrVT, Ptr, + SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, + DAG.getNode(ISD::ADD, getCurDebugLoc(), + PtrVT, Ptr, DAG.getConstant(Offsets[i], PtrVT)), SV, Offsets[i], isVolatile, Alignment); Values[i] = L; Chains[i] = L.getValue(1); } - + if (!ConstantMemory) { - SDValue Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), + MVT::Other, &Chains[0], NumValues); if (isVolatile) DAG.setRoot(Chain); @@ -2720,8 +2850,9 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { PendingLoads.push_back(Chain); } - setValue(&I, DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], NumValues), - &Values[0], NumValues)); + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), + DAG.getVTList(&ValueVTs[0], NumValues), + &Values[0], NumValues)); } @@ -2748,18 +2879,21 @@ void SelectionDAGLowering::visitStore(StoreInst &I) { bool isVolatile = I.isVolatile(); unsigned Alignment = I.getAlignment(); for (unsigned i = 0; i != NumValues; ++i) - Chains[i] = DAG.getStore(Root, SDValue(Src.getNode(), Src.getResNo() + i), - DAG.getNode(ISD::ADD, PtrVT, Ptr, + Chains[i] = DAG.getStore(Root, getCurDebugLoc(), + SDValue(Src.getNode(), Src.getResNo() + i), + DAG.getNode(ISD::ADD, getCurDebugLoc(), + PtrVT, Ptr, DAG.getConstant(Offsets[i], PtrVT)), PtrV, Offsets[i], isVolatile, Alignment); - DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumValues)); + DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), + MVT::Other, &Chains[0], NumValues)); } /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC /// node. -void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, +void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, unsigned Intrinsic) { bool HasChain = !I.doesNotAccessMemory(); bool OnlyLoad = HasChain && I.onlyReadsMemory(); @@ -2770,7 +2904,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, if (OnlyLoad) { // We don't need to serialize loads against other loads. Ops.push_back(DAG.getRoot()); - } else { + } else { Ops.push_back(getRoot()); } } @@ -2779,7 +2913,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, TargetLowering::IntrinsicInfo Info; bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); - // Add the intrinsic ID as an integer operand if it's not a target intrinsic. + // Add the intrinsic ID as an integer operand if it's not a target intrinsic. if (!IsTgtIntrinsic) Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); @@ -2797,11 +2931,11 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, if (VT.isVector()) { const VectorType *DestTy = cast(I.getType()); MVT EltVT = TLI.getValueType(DestTy->getElementType()); - + VT = MVT::getVectorVT(EltVT, DestTy->getNumElements()); assert(VT != MVT::Other && "Intrinsic uses a non-legal type?"); } - + assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?"); VTs.push_back(VT); } @@ -2814,20 +2948,24 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, SDValue Result; if (IsTgtIntrinsic) { // This is target intrinsic that touches memory - Result = DAG.getMemIntrinsicNode(Info.opc, VTList, VTs.size(), + Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), + VTList, VTs.size(), &Ops[0], Ops.size(), Info.memVT, Info.ptrVal, Info.offset, Info.align, Info.vol, Info.readMem, Info.writeMem); } else if (!HasChain) - Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(), + Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), + VTList, VTs.size(), &Ops[0], Ops.size()); else if (I.getType() != Type::VoidTy) - Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(), + Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), + VTList, VTs.size(), &Ops[0], Ops.size()); else - Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(), + Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), + VTList, VTs.size(), &Ops[0], Ops.size()); if (HasChain) { @@ -2840,8 +2978,8 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, if (I.getType() != Type::VoidTy) { if (const VectorType *PTy = dyn_cast(I.getType())) { MVT VT = TLI.getValueType(PTy); - Result = DAG.getNode(ISD::BIT_CONVERT, VT, Result); - } + Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); + } setValue(&I, Result); } } @@ -2920,26 +3058,29 @@ void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI, /// /// where Op is the hexidecimal representation of floating point value. static SDValue -GetSignificand(SelectionDAG &DAG, SDValue Op) { - SDValue t1 = DAG.getNode(ISD::AND, MVT::i32, Op, - DAG.getConstant(0x007fffff, MVT::i32)); - SDValue t2 = DAG.getNode(ISD::OR, MVT::i32, t1, - DAG.getConstant(0x3f800000, MVT::i32)); - return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t2); +GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { + SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, + DAG.getConstant(0x007fffff, MVT::i32)); + SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, + DAG.getConstant(0x3f800000, MVT::i32)); + return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); } /// GetExponent - Get the exponent: /// -/// (float)((Op1 >> 23) - 127); +/// (float)(int)(((Op & 0x7f800000) >> 23) - 127); /// /// where Op is the hexidecimal representation of floating point value. static SDValue -GetExponent(SelectionDAG &DAG, SDValue Op) { - SDValue t1 = DAG.getNode(ISD::SRL, MVT::i32, Op, - DAG.getConstant(23, MVT::i32)); - SDValue t2 = DAG.getNode(ISD::SUB, MVT::i32, t1, - DAG.getConstant(127, MVT::i32)); - return DAG.getNode(ISD::UINT_TO_FP, MVT::f32, t2); +GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, + DebugLoc dl) { + SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, + DAG.getConstant(0x7f800000, MVT::i32)); + SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, + DAG.getConstant(23, TLI.getPointerTy())); + SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, + DAG.getConstant(127, MVT::i32)); + return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); } /// getF32Constant - Get 32-bit floating point constant. @@ -2948,26 +3089,46 @@ getF32Constant(SelectionDAG &DAG, unsigned Flt) { return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); } -/// Inlined utility function to implement binary input atomic intrinsics for +/// Inlined utility function to implement binary input atomic intrinsics for /// visitIntrinsicCall: I is a call instruction /// Op is the associated NodeType for I const char * SelectionDAGLowering::implVisitBinaryAtomic(CallInst& I, ISD::NodeType Op) { - SDValue Root = getRoot(); - SDValue L = DAG.getAtomic(Op, Root, - getValue(I.getOperand(1)), - getValue(I.getOperand(2)), - I.getOperand(1)); + SDValue Root = getRoot(); + SDValue L = + DAG.getAtomic(Op, getCurDebugLoc(), + getValue(I.getOperand(2)).getValueType().getSimpleVT(), + Root, + getValue(I.getOperand(1)), + getValue(I.getOperand(2)), + I.getOperand(1)); setValue(&I, L); DAG.setRoot(L.getValue(1)); return 0; } +// implVisitAluOverflow - Lower arithmetic overflow instrinsics. +const char * +SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) { + SDValue Op1 = getValue(I.getOperand(1)); + SDValue Op2 = getValue(I.getOperand(2)); + + MVT ValueVTs[] = { Op1.getValueType(), MVT::i1 }; + SDValue Ops[] = { Op1, Op2 }; + + SDValue Result = DAG.getNode(Op, getCurDebugLoc(), + DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2); + + setValue(&I, Result); + return 0; +} + /// visitExp - Lower an exp intrinsic. Handles the special sequences for /// limited-precision mode. void SelectionDAGLowering::visitExp(CallInst &I) { SDValue result; + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { @@ -2978,17 +3139,17 @@ SelectionDAGLowering::visitExp(CallInst &I) { // // #define LOG2OFe 1.4426950f // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, getF32Constant(DAG, 0x3fb8aa3b)); - SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0); + SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; - SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX); - SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1); + SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); + SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); // IntegerPartOfX <<= 23; - IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX, - DAG.getConstant(23, MVT::i32)); + IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, + DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: @@ -2998,20 +3159,20 @@ SelectionDAGLowering::visitExp(CallInst &I) { // (0.735607626f + 0.252464424f * x) * x; // // error 0.0144103317, which is 6 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3e814304)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f3c50c8)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f7f5e7e)); - SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5); + SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); // Add the exponent into the result in integer domain. - SDValue t6 = DAG.getNode(ISD::ADD, MVT::i32, + SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, TwoToFracPartOfX, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t6); + result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3021,23 +3182,23 @@ SelectionDAGLowering::visitExp(CallInst &I) { // (0.224338339f + 0.792043434e-1f * x) * x) * x; // // 0.000107046256 error, which is 13 to 14 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3da235e3)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3e65b8f3)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f324b07)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3f7ff8fd)); - SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7); + SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); // Add the exponent into the result in integer domain. - SDValue t8 = DAG.getNode(ISD::ADD, MVT::i32, + SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, TwoToFracPartOfX, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t8); + result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3050,36 +3211,37 @@ SelectionDAGLowering::visitExp(CallInst &I) { // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; // // error 2.47208000*10^(-7), which is better than 18 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3924b03e)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3ab24b87)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3c1d8c17)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3d634a1d)); - SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, getF32Constant(DAG, 0x3e75fe14)); - SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X); - SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); + SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, getF32Constant(DAG, 0x3f317234)); - SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X); - SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12, + SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); + SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, getF32Constant(DAG, 0x3f800000)); - SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13); + SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::i32, t13); // Add the exponent into the result in integer domain. - SDValue t14 = DAG.getNode(ISD::ADD, MVT::i32, + SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, TwoToFracPartOfX, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, t14); + result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); } } else { // No special expansion. - result = DAG.getNode(ISD::FEXP, + result = DAG.getNode(ISD::FEXP, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1))); } @@ -3092,20 +3254,21 @@ SelectionDAGLowering::visitExp(CallInst &I) { void SelectionDAGLowering::visitLog(CallInst &I) { SDValue result; + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); // Scale the exponent by log(2) [0.69314718f]. - SDValue Exp = GetExponent(DAG, Op1); - SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp, + SDValue Exp = GetExponent(DAG, Op1, TLI, dl); + SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, getF32Constant(DAG, 0x3f317218)); // Get the significand and build it into a floating-point number with // exponent of 1. - SDValue X = GetSignificand(DAG, Op1); + SDValue X = GetSignificand(DAG, Op1, dl); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: @@ -3113,17 +3276,18 @@ SelectionDAGLowering::visitLog(CallInst &I) { // LogofMantissa = // -1.1609546f + // (1.4034025f - 0.23903021f * x) * x; - // + // // error 0.0034276066, which is better than 8 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbe74c456)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x3fb3a2b1)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f949a29)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, LogOfMantissa); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3134,21 +3298,22 @@ SelectionDAGLowering::visitLog(CallInst &I) { // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; // // error 0.000061011436, which is 14 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbd67b6d6)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x3ee4f4b8)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x3fbc278b)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x40348e95)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, getF32Constant(DAG, 0x3fdef31a)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, LogOfMantissa); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3161,31 +3326,32 @@ SelectionDAGLowering::visitLog(CallInst &I) { // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; // // error 0.0000023660568, which is better than 18 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbc91e5ac)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x3e4350aa)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f60d3e3)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x4011cdf0)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, getF32Constant(DAG, 0x406cfd1c)); - SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, getF32Constant(DAG, 0x408797cb)); - SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X); - SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); + SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, getF32Constant(DAG, 0x4006dcab)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, LogOfMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, LogOfMantissa); } } else { // No special expansion. - result = DAG.getNode(ISD::FLOG, + result = DAG.getNode(ISD::FLOG, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1))); } @@ -3198,19 +3364,20 @@ SelectionDAGLowering::visitLog(CallInst &I) { void SelectionDAGLowering::visitLog2(CallInst &I) { SDValue result; + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); // Get the exponent. - SDValue LogOfExponent = GetExponent(DAG, Op1); + SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); // Get the significand and build it into a floating-point number with // exponent of 1. - SDValue X = GetSignificand(DAG, Op1); - + SDValue X = GetSignificand(DAG, Op1, dl); + // Different possible minimax approximations of significand in // floating-point for various degrees of accuracy over [1,2]. if (LimitFloatPrecision <= 6) { @@ -3219,15 +3386,16 @@ SelectionDAGLowering::visitLog2(CallInst &I) { // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; // // error 0.0049451742, which is more than 7 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbeb08fe0)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x40019463)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x3fd6633d)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, Log2ofMantissa); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3236,23 +3404,24 @@ SelectionDAGLowering::visitLog2(CallInst &I) { // (4.07009056f + // (-2.12067489f + // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; - // + // // error 0.0000876136000, which is better than 13 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbda7262e)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x3f25280b)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x4007b923)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x40823e2f)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, getF32Constant(DAG, 0x4020d29c)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, Log2ofMantissa); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3266,31 +3435,32 @@ SelectionDAGLowering::visitLog2(CallInst &I) { // 0.25691327e-1f * x) * x) * x) * x) * x) * x; // // error 0.0000018516, which is better than 18 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbcd2769e)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x3e8ce0b9)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x3fa22ae7)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x40525723)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FSUB, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, getF32Constant(DAG, 0x40aaf200)); - SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, getF32Constant(DAG, 0x40c39dad)); - SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X); - SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); + SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, getF32Constant(DAG, 0x4042902c)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log2ofMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, Log2ofMantissa); } } else { // No special expansion. - result = DAG.getNode(ISD::FLOG2, + result = DAG.getNode(ISD::FLOG2, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1))); } @@ -3303,38 +3473,40 @@ SelectionDAGLowering::visitLog2(CallInst &I) { void SelectionDAGLowering::visitLog10(CallInst &I) { SDValue result; + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); + SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); // Scale the exponent by log10(2) [0.30102999f]. - SDValue Exp = GetExponent(DAG, Op1); - SDValue LogOfExponent = DAG.getNode(ISD::FMUL, MVT::f32, Exp, + SDValue Exp = GetExponent(DAG, Op1, TLI, dl); + SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, getF32Constant(DAG, 0x3e9a209a)); // Get the significand and build it into a floating-point number with // exponent of 1. - SDValue X = GetSignificand(DAG, Op1); + SDValue X = GetSignificand(DAG, Op1, dl); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: - // + // // Log10ofMantissa = // -0.50419619f + // (0.60948995f - 0.10380950f * x) * x; // // error 0.0014886165, which is 6 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0xbdd49a13)); - SDValue t1 = DAG.getNode(ISD::FADD, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, getF32Constant(DAG, 0x3f1c0789)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f011300)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, Log10ofMantissa); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3344,18 +3516,19 @@ SelectionDAGLowering::visitLog10(CallInst &I) { // (-0.31664806f + 0.47637168e-1f * x) * x) * x; // // error 0.00019228036, which is better than 12 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3d431f31)); - SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, getF32Constant(DAG, 0x3ea21fb2)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f6ae232)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f25f7c3)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, Log10ofMantissa); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3367,28 +3540,29 @@ SelectionDAGLowering::visitLog10(CallInst &I) { // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; // // error 0.0000037995730, which is better than 18 bits - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3c5d51ce)); - SDValue t1 = DAG.getNode(ISD::FSUB, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, getF32Constant(DAG, 0x3e00685a)); - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3efb6798)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FSUB, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f88d192)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3fc4316c)); - SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X); - SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); + SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, getF32Constant(DAG, 0x3f57ce70)); - result = DAG.getNode(ISD::FADD, MVT::f32, LogOfExponent, Log10ofMantissa); + result = DAG.getNode(ISD::FADD, dl, + MVT::f32, LogOfExponent, Log10ofMantissa); } } else { // No special expansion. - result = DAG.getNode(ISD::FLOG10, + result = DAG.getNode(ISD::FLOG10, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1))); } @@ -3401,41 +3575,43 @@ SelectionDAGLowering::visitLog10(CallInst &I) { void SelectionDAGLowering::visitExp2(CallInst &I) { SDValue result; + DebugLoc dl = getCurDebugLoc(); if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Op); + SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); // FractionalPartOfX = x - (float)IntegerPartOfX; - SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX); - SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, Op, t1); + SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); + SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); // IntegerPartOfX <<= 23; - IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX, - DAG.getConstant(23, MVT::i32)); + IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, + DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: - // + // // TwoToFractionalPartOfX = // 0.997535578f + // (0.735607626f + 0.252464424f * x) * x; // // error 0.0144103317, which is 6 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3e814304)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f3c50c8)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f7f5e7e)); - SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5); + SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX); + result = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f32, TwoToFractionalPartOfX); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3445,21 +3621,22 @@ SelectionDAGLowering::visitExp2(CallInst &I) { // (0.224338339f + 0.792043434e-1f * x) * x) * x; // // error 0.000107046256, which is 13 to 14 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3da235e3)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3e65b8f3)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f324b07)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3f7ff8fd)); - SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7); + SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX); + result = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f32, TwoToFractionalPartOfX); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3471,34 +3648,35 @@ SelectionDAGLowering::visitExp2(CallInst &I) { // (0.961591928e-2f + // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; // error 2.47208000*10^(-7), which is better than 18 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3924b03e)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3ab24b87)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3c1d8c17)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3d634a1d)); - SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, getF32Constant(DAG, 0x3e75fe14)); - SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X); - SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); + SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, getF32Constant(DAG, 0x3f317234)); - SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X); - SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12, + SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); + SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, getF32Constant(DAG, 0x3f800000)); - SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13); + SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX); + result = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f32, TwoToFractionalPartOfX); } } else { // No special expansion. - result = DAG.getNode(ISD::FEXP2, + result = DAG.getNode(ISD::FEXP2, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1))); } @@ -3512,6 +3690,7 @@ void SelectionDAGLowering::visitPow(CallInst &I) { SDValue result; Value *Val = I.getOperand(1); + DebugLoc dl = getCurDebugLoc(); bool IsExp10 = false; if (getValue(Val).getValueType() == MVT::f32 && @@ -3533,38 +3712,39 @@ SelectionDAGLowering::visitPow(CallInst &I) { // // #define LOG2OF10 3.3219281f // IntegerPartOfX = (int32_t)(x * LOG2OF10); - SDValue t0 = DAG.getNode(ISD::FMUL, MVT::f32, Op, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, getF32Constant(DAG, 0x40549a78)); - SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, MVT::i32, t0); + SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); // FractionalPartOfX = x - (float)IntegerPartOfX; - SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, MVT::f32, IntegerPartOfX); - SDValue X = DAG.getNode(ISD::FSUB, MVT::f32, t0, t1); + SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); + SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); // IntegerPartOfX <<= 23; - IntegerPartOfX = DAG.getNode(ISD::SHL, MVT::i32, IntegerPartOfX, - DAG.getConstant(23, MVT::i32)); + IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, + DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { // For floating-point precision of 6: - // + // // twoToFractionalPartOfX = // 0.997535578f + // (0.735607626f + 0.252464424f * x) * x; - // + // // error 0.0144103317, which is 6 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3e814304)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3f3c50c8)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f7f5e7e)); - SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t5); + SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, MVT::i32, t6, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX); + result = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f32, TwoToFractionalPartOfX); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3574,21 +3754,22 @@ SelectionDAGLowering::visitPow(CallInst &I) { // (0.224338339f + 0.792043434e-1f * x) * x) * x; // // error 0.000107046256, which is 13 to 14 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3da235e3)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3e65b8f3)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3f324b07)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3f7ff8fd)); - SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t7); + SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, MVT::i32, t8, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX); + result = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f32, TwoToFractionalPartOfX); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3600,34 +3781,35 @@ SelectionDAGLowering::visitPow(CallInst &I) { // (0.961591928e-2f + // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; // error 2.47208000*10^(-7), which is better than 18 bits - SDValue t2 = DAG.getNode(ISD::FMUL, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, getF32Constant(DAG, 0x3924b03e)); - SDValue t3 = DAG.getNode(ISD::FADD, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, getF32Constant(DAG, 0x3ab24b87)); - SDValue t4 = DAG.getNode(ISD::FMUL, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, getF32Constant(DAG, 0x3c1d8c17)); - SDValue t6 = DAG.getNode(ISD::FMUL, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, getF32Constant(DAG, 0x3d634a1d)); - SDValue t8 = DAG.getNode(ISD::FMUL, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, getF32Constant(DAG, 0x3e75fe14)); - SDValue t10 = DAG.getNode(ISD::FMUL, MVT::f32, t9, X); - SDValue t11 = DAG.getNode(ISD::FADD, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); + SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, getF32Constant(DAG, 0x3f317234)); - SDValue t12 = DAG.getNode(ISD::FMUL, MVT::f32, t11, X); - SDValue t13 = DAG.getNode(ISD::FADD, MVT::f32, t12, + SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); + SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, getF32Constant(DAG, 0x3f800000)); - SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, t13); + SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, MVT::i32, t14, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, TwoToFractionalPartOfX); + result = DAG.getNode(ISD::BIT_CONVERT, dl, + MVT::f32, TwoToFractionalPartOfX); } } else { // No special expansion. - result = DAG.getNode(ISD::FPOW, + result = DAG.getNode(ISD::FPOW, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1)), getValue(I.getOperand(2))); @@ -3641,6 +3823,7 @@ SelectionDAGLowering::visitPow(CallInst &I) { /// otherwise lower it and return null. const char * SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { + DebugLoc dl = getCurDebugLoc(); switch (Intrinsic) { default: // By default, turn this into a target intrinsic node. @@ -3650,11 +3833,11 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::vaend: visitVAEnd(I); return 0; case Intrinsic::vacopy: visitVACopy(I); return 0; case Intrinsic::returnaddress: - setValue(&I, DAG.getNode(ISD::RETURNADDR, TLI.getPointerTy(), + setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), getValue(I.getOperand(1)))); return 0; case Intrinsic::frameaddress: - setValue(&I, DAG.getNode(ISD::FRAMEADDR, TLI.getPointerTy(), + setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), getValue(I.getOperand(1)))); return 0; case Intrinsic::setjmp: @@ -3668,7 +3851,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { SDValue Op2 = getValue(I.getOperand(2)); SDValue Op3 = getValue(I.getOperand(3)); unsigned Align = cast(I.getOperand(4))->getZExtValue(); - DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, + DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } @@ -3677,7 +3860,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { SDValue Op2 = getValue(I.getOperand(2)); SDValue Op3 = getValue(I.getOperand(3)); unsigned Align = cast(I.getOperand(4))->getZExtValue(); - DAG.setRoot(DAG.getMemset(getRoot(), Op1, Op2, Op3, Align, + DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, I.getOperand(1), 0)); return 0; } @@ -3694,82 +3877,96 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Size = C->getZExtValue(); if (AA->alias(I.getOperand(1), Size, I.getOperand(2), Size) == AliasAnalysis::NoAlias) { - DAG.setRoot(DAG.getMemcpy(getRoot(), Op1, Op2, Op3, Align, false, + DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, false, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } - DAG.setRoot(DAG.getMemmove(getRoot(), Op1, Op2, Op3, Align, + DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, I.getOperand(1), 0, I.getOperand(2), 0)); return 0; } case Intrinsic::dbg_stoppoint: { - MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); + DwarfWriter *DW = DAG.getDwarfWriter(); DbgStopPointInst &SPI = cast(I); - if (MMI && SPI.getContext() && MMI->Verify(SPI.getContext())) { - DebugInfoDesc *DD = MMI->getDescFor(SPI.getContext()); - assert(DD && "Not a debug information descriptor"); + if (DW && DW->ValidDebugInfo(SPI.getContext())) { DAG.setRoot(DAG.getDbgStopPoint(getRoot(), SPI.getLine(), SPI.getColumn(), - cast(DD))); + SPI.getContext())); + DICompileUnit CU(cast(SPI.getContext())); + unsigned SrcFile = DW->RecordSource(CU.getDirectory(), CU.getFilename()); + unsigned idx = DAG.getMachineFunction(). + getOrCreateDebugLocID(SrcFile, + SPI.getLine(), + SPI.getColumn()); + setCurDebugLoc(DebugLoc::get(idx)); } - return 0; } case Intrinsic::dbg_region_start: { - MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); + DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionStartInst &RSI = cast(I); - if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { - unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + if (DW && DW->ValidDebugInfo(RSI.getContext())) { + unsigned LabelID = + DW->RecordRegionStart(cast(RSI.getContext())); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); } return 0; } case Intrinsic::dbg_region_end: { - MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); + DwarfWriter *DW = DAG.getDwarfWriter(); DbgRegionEndInst &REI = cast(I); - if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { - unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + if (DW && DW->ValidDebugInfo(REI.getContext())) { + unsigned LabelID = + DW->RecordRegionEnd(cast(REI.getContext())); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); } return 0; } case Intrinsic::dbg_func_start: { - MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - if (!MMI) return 0; + DwarfWriter *DW = DAG.getDwarfWriter(); + if (!DW) return 0; DbgFuncStartInst &FSI = cast(I); Value *SP = FSI.getSubprogram(); - if (SP && MMI->Verify(SP)) { + if (SP && DW->ValidDebugInfo(SP)) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is // what (most?) gdb expects. - DebugInfoDesc *DD = MMI->getDescFor(SP); - assert(DD && "Not a debug information descriptor"); - SubprogramDesc *Subprogram = cast(DD); - const CompileUnitDesc *CompileUnit = Subprogram->getFile(); - unsigned SrcFile = MMI->RecordSource(CompileUnit); + DISubprogram Subprogram(cast(SP)); + DICompileUnit CompileUnit = Subprogram.getCompileUnit(); + unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(), + CompileUnit.getFilename()); + // Record the source line but does not create a label for the normal // function start. It will be emitted at asm emission time. However, // create a label if this is a beginning of inlined function. - unsigned LabelID = MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile); - if (MMI->getSourceLines().size() != 1) - DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); + unsigned Line = Subprogram.getLineNumber(); + unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); + + if (DW->getRecordSourceLineCount() != 1) + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getCurDebugLoc(), + getRoot(), LabelID)); + + setCurDebugLoc(DebugLoc::get(DAG.getMachineFunction(). + getOrCreateDebugLocID(SrcFile, Line, 0))); } return 0; } case Intrinsic::dbg_declare: { - MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); + DwarfWriter *DW = DAG.getDwarfWriter(); DbgDeclareInst &DI = cast(I); Value *Variable = DI.getVariable(); - if (MMI && Variable && MMI->Verify(Variable)) - DAG.setRoot(DAG.getNode(ISD::DECLARE, MVT::Other, getRoot(), + if (DW && DW->ValidDebugInfo(Variable)) + DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), getValue(DI.getAddress()), getValue(Variable))); return 0; } - + case Intrinsic::eh_exception: { if (!CurMBB->isLandingPad()) { // FIXME: Mark exception register as live in. Hack for PR1508. @@ -3780,7 +3977,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); SDValue Ops[1]; Ops[0] = DAG.getRoot(); - SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, VTs, Ops, 1); + SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); setValue(&I, Op); DAG.setRoot(Op.getValue(1)); return 0; @@ -3791,7 +3988,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64); - + if (MMI) { if (CurMBB->isLandingPad()) AddCatchInfo(I, MMI, CurMBB); @@ -3809,13 +4006,13 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { SDValue Ops[2]; Ops[0] = getValue(I.getOperand(1)); Ops[1] = getRoot(); - SDValue Op = DAG.getNode(ISD::EHSELECTION, VTs, Ops, 2); + SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); setValue(&I, Op); DAG.setRoot(Op.getValue(1)); } else { setValue(&I, DAG.getConstant(0, VT)); } - + return 0; } @@ -3843,7 +4040,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::eh_return_i64: if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { MMI->setCallsEHReturn(true); - DAG.setRoot(DAG.getNode(ISD::EH_RETURN, + DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, MVT::Other, getControlRoot(), getValue(I.getOperand(1)), @@ -3864,20 +4061,20 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { MVT VT = getValue(I.getOperand(1)).getValueType(); SDValue CfaArg; if (VT.bitsGT(TLI.getPointerTy())) - CfaArg = DAG.getNode(ISD::TRUNCATE, + CfaArg = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), getValue(I.getOperand(1))); else - CfaArg = DAG.getNode(ISD::SIGN_EXTEND, + CfaArg = DAG.getNode(ISD::SIGN_EXTEND, dl, TLI.getPointerTy(), getValue(I.getOperand(1))); - SDValue Offset = DAG.getNode(ISD::ADD, + SDValue Offset = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), - DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, + DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, TLI.getPointerTy()), CfaArg); - setValue(&I, DAG.getNode(ISD::ADD, + setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), - DAG.getNode(ISD::FRAMEADDR, + DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), DAG.getConstant(0, TLI.getPointerTy())), @@ -3908,7 +4105,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { } MVT DestVT = TLI.getValueType(I.getType()); Value* Op1 = I.getOperand(1); - setValue(&I, DAG.getConvertRndSat(DestVT, getValue(Op1), + setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), DAG.getValueType(DestVT), DAG.getValueType(getValue(Op1).getValueType()), getValue(I.getOperand(2)), @@ -3918,23 +4115,23 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { } case Intrinsic::sqrt: - setValue(&I, DAG.getNode(ISD::FSQRT, + setValue(&I, DAG.getNode(ISD::FSQRT, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1)))); return 0; case Intrinsic::powi: - setValue(&I, DAG.getNode(ISD::FPOWI, + setValue(&I, DAG.getNode(ISD::FPOWI, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1)), getValue(I.getOperand(2)))); return 0; case Intrinsic::sin: - setValue(&I, DAG.getNode(ISD::FSIN, + setValue(&I, DAG.getNode(ISD::FSIN, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1)))); return 0; case Intrinsic::cos: - setValue(&I, DAG.getNode(ISD::FCOS, + setValue(&I, DAG.getNode(ISD::FCOS, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1)))); return 0; @@ -3958,12 +4155,12 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::pcmarker: { SDValue Tmp = getValue(I.getOperand(1)); - DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); + DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); return 0; } case Intrinsic::readcyclecounter: { SDValue Op = getRoot(); - SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, + SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl, DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2, &Op, 1); setValue(&I, Tmp); @@ -3981,34 +4178,34 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { abort(); } case Intrinsic::bswap: - setValue(&I, DAG.getNode(ISD::BSWAP, + setValue(&I, DAG.getNode(ISD::BSWAP, dl, getValue(I.getOperand(1)).getValueType(), getValue(I.getOperand(1)))); return 0; case Intrinsic::cttz: { SDValue Arg = getValue(I.getOperand(1)); MVT Ty = Arg.getValueType(); - SDValue result = DAG.getNode(ISD::CTTZ, Ty, Arg); + SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctlz: { SDValue Arg = getValue(I.getOperand(1)); MVT Ty = Arg.getValueType(); - SDValue result = DAG.getNode(ISD::CTLZ, Ty, Arg); + SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctpop: { SDValue Arg = getValue(I.getOperand(1)); MVT Ty = Arg.getValueType(); - SDValue result = DAG.getNode(ISD::CTPOP, Ty, Arg); + SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::stacksave: { SDValue Op = getRoot(); - SDValue Tmp = DAG.getNode(ISD::STACKSAVE, + SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl, DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1); setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); @@ -4016,7 +4213,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { } case Intrinsic::stackrestore: { SDValue Tmp = getValue(I.getOperand(1)); - DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp)); + DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp)); return 0; } case Intrinsic::stackprotector: { @@ -4034,7 +4231,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { SDValue FIN = DAG.getFrameIndex(FI, PtrTy); // Store the stack protector onto the stack. - SDValue Result = DAG.getStore(getRoot(), Src, FIN, + SDValue Result = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, PseudoSourceValue::getFixedStack(FI), 0, true); setValue(&I, Result); @@ -4056,7 +4253,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Ops[4] = DAG.getSrcValue(I.getOperand(1)); Ops[5] = DAG.getSrcValue(F); - SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, + SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl, DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, Ops, 6); @@ -4070,7 +4267,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { if (GFI) { Value *Alloca = I.getOperand(1); Constant *TypeMap = cast(I.getOperand(2)); - + FrameIndexSDNode *FI = cast(getValue(Alloca).getNode()); GFI->addStackRoot(FI->getIndex(), TypeMap); } @@ -4082,32 +4279,27 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::flt_rounds: { - setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, MVT::i32)); + setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); return 0; } case Intrinsic::trap: { - DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); + DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); return 0; } case Intrinsic::uadd_with_overflow: - case Intrinsic::sadd_with_overflow: { - SDValue Op1 = getValue(I.getOperand(1)); - SDValue Op2 = getValue(I.getOperand(2)); - MVT Ty = Op1.getValueType(); - - MVT ValueVTs[] = { Ty, MVT::i1 }; - SDValue Ops[] = { Op1, Op2 }; - - SDValue Result = - DAG.getNode((Intrinsic == Intrinsic::sadd_with_overflow) ? - ISD::SADDO : ISD::UADDO, - DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2); - - setValue(&I, Result); - return 0; - } + return implVisitAluOverflow(I, ISD::UADDO); + case Intrinsic::sadd_with_overflow: + return implVisitAluOverflow(I, ISD::SADDO); + case Intrinsic::usub_with_overflow: + return implVisitAluOverflow(I, ISD::USUBO); + case Intrinsic::ssub_with_overflow: + return implVisitAluOverflow(I, ISD::SSUBO); + case Intrinsic::umul_with_overflow: + return implVisitAluOverflow(I, ISD::UMULO); + case Intrinsic::smul_with_overflow: + return implVisitAluOverflow(I, ISD::SMULO); case Intrinsic::prefetch: { SDValue Ops[4]; @@ -4115,213 +4307,55 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Ops[1] = getValue(I.getOperand(1)); Ops[2] = getValue(I.getOperand(2)); Ops[3] = getValue(I.getOperand(3)); - DAG.setRoot(DAG.getNode(ISD::PREFETCH, MVT::Other, &Ops[0], 4)); + DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); return 0; } - + case Intrinsic::memory_barrier: { SDValue Ops[6]; Ops[0] = getRoot(); for (int x = 1; x < 6; ++x) Ops[x] = getValue(I.getOperand(x)); - DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, MVT::Other, &Ops[0], 6)); + DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); return 0; } case Intrinsic::atomic_cmp_swap: { - SDValue Root = getRoot(); - SDValue L; - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_8, Root, - getValue(I.getOperand(1)), - getValue(I.getOperand(2)), - getValue(I.getOperand(3)), - I.getOperand(1)); - break; - case MVT::i16: - L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_16, Root, - getValue(I.getOperand(1)), - getValue(I.getOperand(2)), - getValue(I.getOperand(3)), - I.getOperand(1)); - break; - case MVT::i32: - L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_32, Root, - getValue(I.getOperand(1)), - getValue(I.getOperand(2)), - getValue(I.getOperand(3)), - I.getOperand(1)); - break; - case MVT::i64: - L = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP_64, Root, - getValue(I.getOperand(1)), - getValue(I.getOperand(2)), - getValue(I.getOperand(3)), - I.getOperand(1)); - break; - default: - assert(0 && "Invalid atomic type"); - abort(); - } + SDValue Root = getRoot(); + SDValue L = + DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(), + getValue(I.getOperand(2)).getValueType().getSimpleVT(), + Root, + getValue(I.getOperand(1)), + getValue(I.getOperand(2)), + getValue(I.getOperand(3)), + I.getOperand(1)); setValue(&I, L); DAG.setRoot(L.getValue(1)); return 0; } case Intrinsic::atomic_load_add: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD); case Intrinsic::atomic_load_sub: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB); case Intrinsic::atomic_load_or: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR); case Intrinsic::atomic_load_xor: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR); case Intrinsic::atomic_load_and: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND); case Intrinsic::atomic_load_nand: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND); case Intrinsic::atomic_load_max: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX); case Intrinsic::atomic_load_min: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN); case Intrinsic::atomic_load_umin: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN); case Intrinsic::atomic_load_umax: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX); case Intrinsic::atomic_swap: - switch (getValue(I.getOperand(2)).getValueType().getSimpleVT()) { - case MVT::i8: - return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_8); - case MVT::i16: - return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_16); - case MVT::i32: - return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_32); - case MVT::i64: - return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP_64); - default: - assert(0 && "Invalid atomic type"); - abort(); - } + return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP); } } @@ -4360,7 +4394,8 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, // Both PendingLoads and PendingExports must be flushed here; // this call might not return. (void)getRoot(); - DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(), + getControlRoot(), BeginLabel)); } std::pair Result = @@ -4370,7 +4405,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, CS.paramHasAttr(0, Attribute::InReg), CS.getCallingConv(), IsTailCall && PerformTailCallOpt, - Callee, Args, DAG); + Callee, Args, DAG, getCurDebugLoc()); if (CS.getType() != Type::VoidTy) setValue(CS.getInstruction(), Result.first); DAG.setRoot(Result.second); @@ -4379,7 +4414,8 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee, // Insert a label at the end of the invoke call to mark the try range. This // can be used to detect deletion of the invoke via the MachineModuleInfo. EndLabel = MMI->NextLabelID(); - DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getCurDebugLoc(), + getRoot(), EndLabel)); // Inform MachineModuleInfo of range. MMI->addInvoke(LandingPad, BeginLabel, EndLabel); @@ -4391,6 +4427,14 @@ void SelectionDAGLowering::visitCall(CallInst &I) { const char *RenameFn = 0; if (Function *F = I.getCalledFunction()) { if (F->isDeclaration()) { + const TargetIntrinsicInfo *II = TLI.getTargetMachine().getIntrinsicInfo(); + if (II) { + if (unsigned IID = II->getIntrinsicID(F)) { + RenameFn = visitIntrinsicCall(I, IID); + if (!RenameFn) + return; + } + } if (unsigned IID = F->getIntrinsicID()) { RenameFn = visitIntrinsicCall(I, IID); if (!RenameFn) @@ -4401,7 +4445,7 @@ void SelectionDAGLowering::visitCall(CallInst &I) { // Check for well-known libc/libm calls. If the function is internal, it // can't be a library call. unsigned NameLen = F->getNameLen(); - if (!F->hasInternalLinkage() && NameLen) { + if (!F->hasLocalLinkage() && NameLen) { const char *NameStr = F->getNameStart(); if (NameStr[0] == 'c' && ((NameLen == 8 && !strcmp(NameStr, "copysign")) || @@ -4412,8 +4456,8 @@ void SelectionDAGLowering::visitCall(CallInst &I) { I.getType() == I.getOperand(2)->getType()) { SDValue LHS = getValue(I.getOperand(1)); SDValue RHS = getValue(I.getOperand(2)); - setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(), - LHS, RHS)); + setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), + LHS.getValueType(), LHS, RHS)); return; } } else if (NameStr[0] == 'f' && @@ -4424,10 +4468,11 @@ void SelectionDAGLowering::visitCall(CallInst &I) { I.getOperand(1)->getType()->isFloatingPoint() && I.getType() == I.getOperand(1)->getType()) { SDValue Tmp = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp)); + setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), + Tmp.getValueType(), Tmp)); return; } - } else if (NameStr[0] == 's' && + } else if (NameStr[0] == 's' && ((NameLen == 3 && !strcmp(NameStr, "sin")) || (NameLen == 4 && !strcmp(NameStr, "sinf")) || (NameLen == 4 && !strcmp(NameStr, "sinl")))) { @@ -4435,7 +4480,8 @@ void SelectionDAGLowering::visitCall(CallInst &I) { I.getOperand(1)->getType()->isFloatingPoint() && I.getType() == I.getOperand(1)->getType()) { SDValue Tmp = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp)); + setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), + Tmp.getValueType(), Tmp)); return; } } else if (NameStr[0] == 'c' && @@ -4446,7 +4492,8 @@ void SelectionDAGLowering::visitCall(CallInst &I) { I.getOperand(1)->getType()->isFloatingPoint() && I.getType() == I.getOperand(1)->getType()) { SDValue Tmp = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp)); + setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), + Tmp.getValueType(), Tmp)); return; } } @@ -4467,10 +4514,10 @@ void SelectionDAGLowering::visitCall(CallInst &I) { /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from -/// this value and returns the result as a ValueVT value. This uses +/// this value and returns the result as a ValueVT value. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. -SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, +SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const { // Assemble the legal parts into the final values. @@ -4486,13 +4533,13 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, for (unsigned i = 0; i != NumRegs; ++i) { SDValue P; if (Flag == 0) - P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT); + P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); else { - P = DAG.getCopyFromReg(Chain, Regs[Part+i], RegisterVT, *Flag); + P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); *Flag = P.getValue(2); } Chain = P.getValue(1); - + // If the source register was virtual and if we know something about it, // add an assert node. if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && @@ -4501,11 +4548,11 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); if (FLI.LiveOutRegInfo.size() > SlotNo) { FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; - + unsigned RegSize = RegisterVT.getSizeInBits(); unsigned NumSignBits = LOI.NumSignBits; unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes(); - + // FIXME: We capture more information than the dag can represent. For // now, just use the tightest assertzext/assertsext possible. bool isSExt = true; @@ -4526,33 +4573,34 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 else if (NumZeroBits >= RegSize-33) isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 - + if (FromVT != MVT::Other) { - P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, + P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, RegisterVT, P, DAG.getValueType(FromVT)); } } } - + Parts[i] = P; } - - Values[Value] = getCopyFromParts(DAG, Parts.begin(), NumRegs, RegisterVT, - ValueVT); + + Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), + NumRegs, RegisterVT, ValueVT); Part += NumRegs; Parts.clear(); } - return DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], ValueVTs.size()), - &Values[0], ValueVTs.size()); + return DAG.getNode(ISD::MERGE_VALUES, dl, + DAG.getVTList(&ValueVTs[0], ValueVTs.size()), + &Values[0], ValueVTs.size()); } /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the -/// specified value into the registers specified by this object. This uses +/// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. -void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, +void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const { // Get the list of the values's legal parts. unsigned NumRegs = Regs.size(); @@ -4562,7 +4610,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, unsigned NumParts = TLI->getNumRegisters(ValueVT); MVT RegisterVT = RegVTs[Value]; - getCopyToParts(DAG, Val.getValue(Val.getResNo() + Value), + getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], NumParts, RegisterVT); Part += NumParts; } @@ -4572,16 +4620,16 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, for (unsigned i = 0; i != NumRegs; ++i) { SDValue Part; if (Flag == 0) - Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i]); + Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); else { - Part = DAG.getCopyToReg(Chain, Regs[i], Parts[i], *Flag); + Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); *Flag = Part.getValue(1); } Chains[i] = Part.getValue(0); } - + if (NumRegs == 1 || Flag) - // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is + // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is // flagged to it. That is the CopyToReg nodes and the user are considered // a single scheduling unit. If we create a TokenFactor and return it as // chain, then the TokenFactor is both a predecessor (operand) of the @@ -4593,11 +4641,11 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, // = op c3, ..., f2 Chain = Chains[NumRegs-1]; else - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Chains[0], NumRegs); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); } /// AddInlineAsmOperands - Add this value to the specified inlineasm node -/// operand list. This adds the code marker and includes the number of +/// operand list. This adds the code marker and includes the number of /// values added into it. void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, std::vector &Ops) const { @@ -4613,7 +4661,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, } } -/// isAllocatableRegister - If the specified register is safe to allocate, +/// isAllocatableRegister - If the specified register is safe to allocate, /// i.e. it isn't a stack pointer or some other special register, return the /// register class for the register. Otherwise, return null. static const TargetRegisterClass * @@ -4627,7 +4675,7 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF, MVT ThisVT = MVT::Other; const TargetRegisterClass *RC = *RCI; - // If none of the the value types for this register class are valid, we + // If none of the the value types for this register class are valid, we // can't use it. For example, 64-bit reg classes on 32-bit targets. for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); I != E; ++I) { @@ -4641,9 +4689,9 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF, } } } - + if (ThisVT == MVT::Other) continue; - + // NOTE: This isn't ideal. In particular, this might allocate the // frame pointer in functions that need it (due to them not being taken // out of allocation, because a variable sized allocation hasn't been seen @@ -4659,13 +4707,13 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF, } } return FoundRC; -} +} namespace llvm { /// AsmOperandInfo - This contains information for each constraint that we are /// lowering. -struct VISIBILITY_HIDDEN SDISelAsmOperandInfo : +struct VISIBILITY_HIDDEN SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { /// CallOperand - If this is the result output operand or a clobber /// this is null, otherwise it is the incoming operand to the CallInst. @@ -4675,15 +4723,15 @@ struct VISIBILITY_HIDDEN SDISelAsmOperandInfo : /// AssignedRegs - If this is a register or register class operand, this /// contains the set of register corresponding to the operand. RegsForValue AssignedRegs; - + explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info) : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { } - + /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers /// busy in OutputRegs/InputRegs. void MarkAllocatedRegs(bool isOutReg, bool isInReg, - std::set &OutputRegs, + std::set &OutputRegs, std::set &InputRegs, const TargetRegisterInfo &TRI) const { if (isOutReg) { @@ -4695,24 +4743,24 @@ struct VISIBILITY_HIDDEN SDISelAsmOperandInfo : MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); } } - + /// getCallOperandValMVT - Return the MVT of the Value* that this operand /// corresponds to. If there is no Value* for this operand, it returns /// MVT::Other. MVT getCallOperandValMVT(const TargetLowering &TLI, const TargetData *TD) const { if (CallOperandVal == 0) return MVT::Other; - + if (isa(CallOperandVal)) return TLI.getPointerTy(); - + const llvm::Type *OpTy = CallOperandVal->getType(); - + // If this is an indirect operand, the operand is a pointer to the // accessed type. if (isIndirect) OpTy = cast(OpTy)->getElementType(); - + // If OpTy is not a single value, it may be a struct/union that we // can tile with integers. if (!OpTy->isSingleValueType() && OpTy->isSized()) { @@ -4729,14 +4777,14 @@ struct VISIBILITY_HIDDEN SDISelAsmOperandInfo : break; } } - + return TLI.getValueType(OpTy, true); } - + private: /// MarkRegAndAliases - Mark the specified register and all aliases in the /// specified set. - static void MarkRegAndAliases(unsigned Reg, std::set &Regs, + static void MarkRegAndAliases(unsigned Reg, std::set &Regs, const TargetRegisterInfo &TRI) { assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); Regs.insert(Reg); @@ -4759,7 +4807,7 @@ private: /// void SelectionDAGLowering:: GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, - std::set &OutputRegs, + std::set &OutputRegs, std::set &InputRegs) { // Compute whether this value requires an input register, an output register, // or both. @@ -4768,8 +4816,8 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, switch (OpInfo.Type) { case InlineAsm::isOutput: isOutReg = true; - - // If there is an input constraint that matches this, we need to reserve + + // If there is an input constraint that matches this, we need to reserve // the input register so no other inputs allocate to it. isInReg = OpInfo.hasMatchingInput(); break; @@ -4782,14 +4830,14 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, isInReg = true; break; } - - + + MachineFunction &MF = DAG.getMachineFunction(); SmallVector Regs; - + // If this is a constraint for a single physreg, or a constraint for a // register class, find it. - std::pair PhysReg = + std::pair PhysReg = TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); @@ -4805,8 +4853,8 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // vector types). MVT RegVT = *PhysReg.second->vt_begin(); if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { - OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, RegVT, - OpInfo.CallOperand); + OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), + RegVT, OpInfo.CallOperand); OpInfo.ConstraintVT = RegVT; } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { // If the input is a FP value and we want it in FP registers, do a @@ -4814,15 +4862,15 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // into i64, which can be passed with two i32 values on a 32-bit // machine. RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); - OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, RegVT, - OpInfo.CallOperand); + OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), + RegVT, OpInfo.CallOperand); OpInfo.ConstraintVT = RegVT; } } - + NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); } - + MVT RegVT; MVT ValueVT = OpInfo.ConstraintVT; @@ -4831,12 +4879,12 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, if (PhysReg.first) { if (OpInfo.ConstraintVT == MVT::Other) ValueVT = *PhysReg.second->vt_begin(); - + // Get the actual register value type. This is important, because the user // may have asked for (e.g.) the AX register in i32 type. We need to // remember that AX is actually i16 to get the right extension. RegVT = *PhysReg.second->vt_begin(); - + // This is a explicit reference to a physical register. Regs.push_back(PhysReg.first); @@ -4844,8 +4892,8 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, if (NumRegs != 1) { TargetRegisterClass::iterator I = PhysReg.second->begin(); for (; *I != PhysReg.first; ++I) - assert(I != PhysReg.second->end() && "Didn't find reg!"); - + assert(I != PhysReg.second->end() && "Didn't find reg!"); + // Already added the first reg. --NumRegs; ++I; for (; NumRegs; --NumRegs, ++I) { @@ -4858,13 +4906,13 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); return; } - + // Otherwise, if this was a reference to an LLVM register class, create vregs // for this reference. std::vector RegClassRegs; const TargetRegisterClass *RC = PhysReg.second; if (RC) { - // If this is a tied register, our regalloc doesn't know how to maintain + // If this is a tied register, our regalloc doesn't know how to maintain // the constraint, so we have to pick a register to pin the input/output to. // If it isn't a matched constraint, go ahead and create vreg and let the // regalloc do its thing. @@ -4877,15 +4925,15 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, MachineRegisterInfo &RegInfo = MF.getRegInfo(); for (; NumRegs; --NumRegs) Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second)); - + OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); return; } - + // Otherwise, we can't allocate it. Let the code below figure out how to // maintain these constraints. RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end()); - + } else { // This is a reference to a register class that doesn't directly correspond // to an LLVM register class. Allocate NumRegs consecutive, available, @@ -4893,7 +4941,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT); } - + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); unsigned NumAllocated = 0; for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { @@ -4905,7 +4953,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, NumAllocated = 0; continue; } - + // Check to see if this register is allocatable (i.e. don't give out the // stack pointer). if (RC == 0) { @@ -4916,7 +4964,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, continue; } } - + // Okay, this register is good, we can use it. ++NumAllocated; @@ -4927,14 +4975,14 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // Mark all of the allocated registers used. for (unsigned i = RegStart; i != RegEnd; ++i) Regs.push_back(RegClassRegs[i]); - - OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), + + OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), OpInfo.ConstraintVT); OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); return; } } - + // Otherwise, we couldn't allocate enough registers for this. } @@ -4942,7 +4990,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, /// processed uses a memory 'm' constraint. static bool hasInlineAsmMemConstraint(std::vector &CInfos, - TargetLowering &TLI) { + const TargetLowering &TLI) { for (unsigned i = 0, e = CInfos.size(); i != e; ++i) { InlineAsm::ConstraintInfo &CI = CInfos[i]; for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) { @@ -4962,10 +5010,10 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { /// ConstraintOperands - Information about all of the constraints. std::vector ConstraintOperands; - + SDValue Chain = getRoot(); SDValue Flag; - + std::set OutputRegs, InputRegs; // Do a prepass over the constraints, canonicalizing them, and building up the @@ -4974,13 +5022,13 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { ConstraintInfos = IA->ParseConstraints(); bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI); - + unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. unsigned ResNo = 0; // ResNo - The result number of the next output. for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); - + MVT OpVT = MVT::Other; // Compute the value type for each operand. @@ -4991,7 +5039,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { OpInfo.CallOperandVal = CS.getArgument(ArgNo++); break; } - + // The return value of the call is this value. As such, there is no // corresponding argument. assert(CS.getType() != Type::VoidTy && "Bad inline asm!"); @@ -5019,36 +5067,37 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { } else { OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); } - + OpVT = OpInfo.getCallOperandValMVT(TLI, TD); } - + OpInfo.ConstraintVT = OpVT; } - + // Second pass over the constraints: compute which constraint option to use // and assign registers to constraints that want a specific physreg. for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) { SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; - + // If this is an output operand with a matching input operand, look up the - // matching input. It might have a different type (e.g. the output might be - // i32 and the input i64) and we need to pick the larger width to ensure we - // reserve the right number of registers. + // matching input. If their types mismatch, e.g. one is an integer, the + // other is floating point, or their sizes are different, flag it as an + // error. if (OpInfo.hasMatchingInput()) { SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; if (OpInfo.ConstraintVT != Input.ConstraintVT) { - assert(OpInfo.ConstraintVT.isInteger() && - Input.ConstraintVT.isInteger() && - "Asm constraints must be the same or different sized integers"); - if (OpInfo.ConstraintVT.getSizeInBits() < - Input.ConstraintVT.getSizeInBits()) - OpInfo.ConstraintVT = Input.ConstraintVT; - else - Input.ConstraintVT = OpInfo.ConstraintVT; + if ((OpInfo.ConstraintVT.isInteger() != + Input.ConstraintVT.isInteger()) || + (OpInfo.ConstraintVT.getSizeInBits() != + Input.ConstraintVT.getSizeInBits())) { + cerr << "Unsupported asm: input constraint with a matching output " + << "constraint of incompatible type!\n"; + exit(1); + } + Input.ConstraintVT = OpInfo.ConstraintVT; } } - + // Compute the constraint code and ConstraintType to use. TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, hasMemory, &DAG); @@ -5058,11 +5107,11 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { !OpInfo.isIndirect) { assert(OpInfo.Type == InlineAsm::isInput && "Can only indirectify direct input operands!"); - + // Memory operands really want the address of the value. If we don't have // an indirect input, put it in the constpool if we can, otherwise spill // it to a stack slot. - + // If the operand is a float, integer, or vector constant, spill to a // constant pool entry to get its address. Value *OpVal = OpInfo.CallOperandVal; @@ -5074,54 +5123,55 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // Otherwise, create a stack slot and emit a store to it before the // asm. const Type *Ty = OpVal->getType(); - uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); + uint64_t TySize = TLI.getTargetData()->getTypePaddedSize(Ty); unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); - Chain = DAG.getStore(Chain, OpInfo.CallOperand, StackSlot, NULL, 0); + Chain = DAG.getStore(Chain, getCurDebugLoc(), + OpInfo.CallOperand, StackSlot, NULL, 0); OpInfo.CallOperand = StackSlot; } - + // There is no longer a Value* corresponding to this operand. OpInfo.CallOperandVal = 0; // It is now an indirect operand. OpInfo.isIndirect = true; } - + // If this constraint is for a specific register, allocate it before // anything else. if (OpInfo.ConstraintType == TargetLowering::C_Register) GetRegistersForValue(OpInfo, OutputRegs, InputRegs); } ConstraintInfos.clear(); - - + + // Second pass - Loop over all of the operands, assigning virtual or physregs // to register class operands. for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; - + // C_Register operands have already been allocated, Other/Memory don't need // to be. if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) GetRegistersForValue(OpInfo, OutputRegs, InputRegs); - } - + } + // AsmNodeOperands - The operands for the ISD::INLINEASM node. std::vector AsmNodeOperands; AsmNodeOperands.push_back(SDValue()); // reserve space for input chain AsmNodeOperands.push_back( DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); - - + + // Loop over all of the inputs, copying the operand values into the // appropriate registers and processing the output regs. RegsForValue RetValRegs; - + // IndirectStoresToEmit - The set of stores to emit after the inline asm node. std::vector > IndirectStoresToEmit; - + for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; @@ -5161,7 +5211,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // Concatenate this output onto the outputs list. RetValRegs.append(OpInfo.AssignedRegs); } - + // Add information to the INLINEASM node to know that this register is // set. OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? @@ -5172,18 +5222,18 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { } case InlineAsm::isInput: { SDValue InOperandVal = OpInfo.CallOperand; - + if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? // If this is required to match an output register we have already set, // just use its register. unsigned OperandNo = OpInfo.getMatchedOperand(); - + // Scan until we find the definition we already emitted of this operand. // When we find it, create a RegsForValue operand. unsigned CurOp = 2; // The first operand. for (; OperandNo; --OperandNo) { // Advance to the next operand. - unsigned NumOps = + unsigned NumOps = cast(AsmNodeOperands[CurOp])->getZExtValue(); assert(((NumOps & 7) == 2 /*REGDEF*/ || (NumOps & 7) == 6 /*EARLYCLOBBER REGDEF*/ || @@ -5192,9 +5242,9 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { CurOp += (NumOps>>3)+1; } - unsigned NumOps = + unsigned NumOps = cast(AsmNodeOperands[CurOp])->getZExtValue(); - if ((NumOps & 7) == 2 /*REGDEF*/ + if ((NumOps & 7) == 2 /*REGDEF*/ || (NumOps & 7) == 6 /* EARLYCLOBBER REGDEF */) { // Add NumOps>>3 registers to MatchedRegs. RegsForValue MatchedRegs; @@ -5206,14 +5256,15 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { cast(AsmNodeOperands[++CurOp])->getReg(); MatchedRegs.Regs.push_back(Reg); } - - // Use the produced MatchedRegs object to - MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); + + // Use the produced MatchedRegs object to + MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), + Chain, &Flag); MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); break; } else { assert(((NumOps & 7) == 4) && "Unknown matching constraint!"); - assert((NumOps >> 3) == 1 && "Unexpected number of operands"); + assert((NumOps >> 3) == 1 && "Unexpected number of operands"); // Add information to the INLINEASM node to know about this input. AsmNodeOperands.push_back(DAG.getTargetConstant(NumOps, TLI.getPointerTy())); @@ -5221,11 +5272,11 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { break; } } - + if (OpInfo.ConstraintType == TargetLowering::C_Other) { - assert(!OpInfo.isIndirect && + assert(!OpInfo.isIndirect && "Don't know how to handle indirect other inputs yet!"); - + std::vector Ops; TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], hasMemory, Ops, DAG); @@ -5234,10 +5285,10 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { << OpInfo.ConstraintCode << "'!\n"; exit(1); } - + // Add information to the INLINEASM node to know about this input. unsigned ResOpType = 3 /*IMM*/ | (Ops.size() << 3); - AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, + AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, TLI.getPointerTy())); AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); break; @@ -5245,7 +5296,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); assert(InOperandVal.getValueType() == TLI.getPointerTy() && "Memory operands expect pointer values"); - + // Add information to the INLINEASM node to know about this input. unsigned ResOpType = 4/*MEM*/ | (1<<3); AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, @@ -5253,11 +5304,11 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { AsmNodeOperands.push_back(InOperandVal); break; } - + assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || OpInfo.ConstraintType == TargetLowering::C_Register) && "Unknown constraint type!"); - assert(!OpInfo.isIndirect && + assert(!OpInfo.isIndirect && "Don't know how to handle indirect register inputs yet!"); // Copy the input into the appropriate registers. @@ -5267,8 +5318,9 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { exit(1); } - OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, Chain, &Flag); - + OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), + Chain, &Flag); + OpInfo.AssignedRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); break; @@ -5283,12 +5335,12 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { } } } - + // Finish up input operands. AsmNodeOperands[0] = Chain; if (Flag.getNode()) AsmNodeOperands.push_back(Flag); - - Chain = DAG.getNode(ISD::INLINEASM, + + Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2, &AsmNodeOperands[0], AsmNodeOperands.size()); Flag = Chain.getValue(1); @@ -5296,53 +5348,57 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // If this asm returns a register value, copy the result from that register // and set it as the value of the call. if (!RetValRegs.Regs.empty()) { - SDValue Val = RetValRegs.getCopyFromRegs(DAG, Chain, &Flag); - + SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(), + Chain, &Flag); + // FIXME: Why don't we do this for inline asms with MRVs? if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { MVT ResultType = TLI.getValueType(CS.getType()); - + // If any of the results of the inline asm is a vector, it may have the // wrong width/num elts. This can happen for register classes that can // contain multiple different value types. The preg or vreg allocated may // not have the same VT as was expected. Convert it to the right type // with bit_convert. if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { - Val = DAG.getNode(ISD::BIT_CONVERT, ResultType, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), + ResultType, Val); - } else if (ResultType != Val.getValueType() && + } else if (ResultType != Val.getValueType() && ResultType.isInteger() && Val.getValueType().isInteger()) { // If a result value was tied to an input value, the computed result may // have a wider width than the expected result. Extract the relevant // portion. - Val = DAG.getNode(ISD::TRUNCATE, ResultType, Val); + Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); } - + assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); } setValue(CS.getInstruction(), Val); } - + std::vector > StoresToEmit; - + // Process indirect outputs, first output all of the flagged copies out of // physregs. for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { RegsForValue &OutRegs = IndirectStoresToEmit[i].first; Value *Ptr = IndirectStoresToEmit[i].second; - SDValue OutVal = OutRegs.getCopyFromRegs(DAG, Chain, &Flag); + SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(), + Chain, &Flag); StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); } - + // Emit the non-flagged stores from the physregs. SmallVector OutChains; for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) - OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first, + OutChains.push_back(DAG.getStore(Chain, getCurDebugLoc(), + StoresToEmit[i].first, getValue(StoresToEmit[i].second), StoresToEmit[i].second, 0)); if (!OutChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &OutChains[0], OutChains.size()); DAG.setRoot(Chain); } @@ -5354,13 +5410,13 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) { MVT IntPtr = TLI.getPointerTy(); if (IntPtr.bitsLT(Src.getValueType())) - Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src); + Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src); else if (IntPtr.bitsGT(Src.getValueType())) - Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src); + Src = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), IntPtr, Src); // Scale the source by the type size. - uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType()); - Src = DAG.getNode(ISD::MUL, Src.getValueType(), + uint64_t ElementSize = TD->getTypePaddedSize(I.getType()->getElementType()); + Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(), Src, DAG.getIntPtrConstant(ElementSize)); TargetLowering::ArgListTy Args; @@ -5371,9 +5427,9 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) { std::pair Result = TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false, - CallingConv::C, PerformTailCallOpt, + CallingConv::C, PerformTailCallOpt, DAG.getExternalSymbol("malloc", IntPtr), - Args, DAG); + Args, DAG, getCurDebugLoc()); setValue(&I, Result.first); // Pointers always fit in registers DAG.setRoot(Result.second); } @@ -5388,33 +5444,37 @@ void SelectionDAGLowering::visitFree(FreeInst &I) { std::pair Result = TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false, CallingConv::C, PerformTailCallOpt, - DAG.getExternalSymbol("free", IntPtr), Args, DAG); + DAG.getExternalSymbol("free", IntPtr), Args, DAG, + getCurDebugLoc()); DAG.setRoot(Result.second); } void SelectionDAGLowering::visitVAStart(CallInst &I) { - DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), - getValue(I.getOperand(1)), + DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), + MVT::Other, getRoot(), + getValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(1)))); } void SelectionDAGLowering::visitVAArg(VAArgInst &I) { - SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(), - getValue(I.getOperand(0)), - DAG.getSrcValue(I.getOperand(0))); + SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), + getRoot(), getValue(I.getOperand(0)), + DAG.getSrcValue(I.getOperand(0))); setValue(&I, V); DAG.setRoot(V.getValue(1)); } void SelectionDAGLowering::visitVAEnd(CallInst &I) { - DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(), - getValue(I.getOperand(1)), + DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), + MVT::Other, getRoot(), + getValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(1)))); } void SelectionDAGLowering::visitVACopy(CallInst &I) { - DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(), - getValue(I.getOperand(1)), + DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), + MVT::Other, getRoot(), + getValue(I.getOperand(1)), getValue(I.getOperand(2)), DAG.getSrcValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(2)))); @@ -5422,10 +5482,11 @@ void SelectionDAGLowering::visitVACopy(CallInst &I) { /// TargetLowering::LowerArguments - This is the default LowerArguments /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all -/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be +/// targets are migrated to using FORMAL_ARGUMENTS, this hook should be /// integrated into SDISel. void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, - SmallVectorImpl &ArgValues) { + SmallVectorImpl &ArgValues, + DebugLoc dl) { // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node. SmallVector Ops; Ops.push_back(DAG.getRoot()); @@ -5460,7 +5521,7 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, const PointerType *Ty = cast(I->getType()); const Type *ElementTy = Ty->getElementType(); unsigned FrameAlign = getByValTypeAlignment(ElementTy); - unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); + unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy); // For ByVal, alignment should be passed from FE. BE will guess if // this info is not there but there are cases it cannot get right. if (F.getParamAlignment(j)) @@ -5488,17 +5549,17 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, } RetVals.push_back(MVT::Other); - + // Create the node. - SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, + SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl, DAG.getVTList(&RetVals[0], RetVals.size()), &Ops[0], Ops.size()).getNode(); - + // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but // allows exposing the loads that may be part of the argument access to the // first DAGCombiner pass. SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG); - + // The number of results should match up, except that the lowered one may have // an extra flag result. assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() || @@ -5513,14 +5574,14 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, } Result = TmpRes.getNode(); - + unsigned NumArgRegs = Result->getNumValues() - 1; DAG.setRoot(SDValue(Result, NumArgRegs)); // Set up the return result vector. unsigned i = 0; unsigned Idx = 1; - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++Idx) { SmallVector ValueVTs; ComputeValueVTs(*this, I->getType(), ValueVTs); @@ -5540,8 +5601,8 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG, else if (F.paramHasAttr(Idx, Attribute::ZExt)) AssertOp = ISD::AssertZext; - ArgValues.push_back(getCopyFromParts(DAG, &Parts[0], NumParts, PartVT, VT, - AssertOp)); + ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts, + PartVT, VT, AssertOp)); } } assert(i == NumArgRegs && "Argument register count mismatch!"); @@ -5558,14 +5619,14 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, bool isInreg, unsigned CallingConv, bool isTailCall, SDValue Callee, - ArgListTy &Args, SelectionDAG &DAG) { + ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { assert((!isTailCall || PerformTailCallOpt) && "isTailCall set when tail-call optimizations are disabled!"); SmallVector Ops; Ops.push_back(Chain); // Op#0 - Chain Ops.push_back(Callee); - + // Handle all of the outgoing arguments. for (unsigned i = 0, e = Args.size(); i != e; ++i) { SmallVector ValueVTs; @@ -5593,7 +5654,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, const PointerType *Ty = cast(Args[i].Ty); const Type *ElementTy = Ty->getElementType(); unsigned FrameAlign = getByValTypeAlignment(ElementTy); - unsigned FrameSize = getTargetData()->getABITypeSize(ElementTy); + unsigned FrameSize = getTargetData()->getTypePaddedSize(ElementTy); // For ByVal, alignment should come from FE. BE will guess if this // info is not there but there are cases it cannot get right. if (Args[i].Alignment) @@ -5615,7 +5676,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, else if (Args[i].isZExt) ExtendKind = ISD::ZERO_EXTEND; - getCopyToParts(DAG, Op, &Parts[0], NumParts, PartVT, ExtendKind); + getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind); for (unsigned i = 0; i != NumParts; ++i) { // if it isn't first piece, alignment must be 1 @@ -5630,7 +5691,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, } } } - + // Figure out the result value types. We start by making a list of // the potentially illegal return value types. SmallVector LoweredRetTys; @@ -5645,11 +5706,12 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, for (unsigned i = 0; i != NumRegs; ++i) LoweredRetTys.push_back(RegisterVT); } - + LoweredRetTys.push_back(MVT::Other); // Always has a chain. - + // Create the CALL node. - SDValue Res = DAG.getCall(CallingConv, isVarArg, isTailCall, isInreg, + SDValue Res = DAG.getCall(CallingConv, dl, + isVarArg, isTailCall, isInreg, DAG.getVTList(&LoweredRetTys[0], LoweredRetTys.size()), &Ops[0], Ops.size() @@ -5676,17 +5738,26 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, for (; RegNo != RegNoEnd; ++RegNo) Results.push_back(Res.getValue(RegNo)); SDValue ReturnValue = - getCopyFromParts(DAG, &Results[0], NumRegs, RegisterVT, VT, + getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT, AssertOp); ReturnValues.push_back(ReturnValue); } - Res = DAG.getMergeValues(DAG.getVTList(&RetTys[0], RetTys.size()), - &ReturnValues[0], ReturnValues.size()); + Res = DAG.getNode(ISD::MERGE_VALUES, dl, + DAG.getVTList(&RetTys[0], RetTys.size()), + &ReturnValues[0], ReturnValues.size()); } return std::make_pair(Res, Chain); } +void TargetLowering::LowerOperationWrapper(SDNode *N, + SmallVectorImpl &Results, + SelectionDAG &DAG) { + SDValue Res = LowerOperation(SDValue(N, 0), DAG); + if (Res.getNode()) + Results.push_back(Res); +} + SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { assert(0 && "LowerOperation not implemented for this target!"); abort(); @@ -5703,7 +5774,7 @@ void SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, unsigned Reg) { RegsForValue RFV(TLI, Reg, V->getType()); SDValue Chain = DAG.getEntryNode(); - RFV.getCopyToRegs(Op, DAG, Chain, 0); + RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); PendingExports.push_back(Chain); } @@ -5715,7 +5786,7 @@ LowerArguments(BasicBlock *LLVMBB) { Function &F = *LLVMBB->getParent(); SDValue OldRoot = SDL->DAG.getRoot(); SmallVector Args; - TLI.LowerArguments(F, SDL->DAG, Args); + TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc()); unsigned a = 0; for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end(); @@ -5759,11 +5830,11 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) { BasicBlock *SuccBB = TI->getSuccessor(succ); if (!isa(SuccBB->begin())) continue; MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB]; - + // If this terminator has multiple identical successors (common for // switches), only handle each succ once. if (!SuccsHandled.insert(SuccMBB)) continue; - + MachineBasicBlock::iterator MBBI = SuccMBB->begin(); PHINode *PN; @@ -5830,11 +5901,11 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, BasicBlock *SuccBB = TI->getSuccessor(succ); if (!isa(SuccBB->begin())) continue; MachineBasicBlock *SuccMBB = FuncInfo->MBBMap[SuccBB]; - + // If this terminator has multiple identical successors (common for // switches), only handle each succ once. if (!SuccsHandled.insert(SuccMBB)) continue; - + MachineBasicBlock::iterator MBBI = SuccMBB->begin(); PHINode *PN;