X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FRegAllocLocal.cpp;h=456c457a316e033262c469dc6bcba5d74ef56aad;hb=be6781b5d00107f4b60797c3ebdc0aab110487ff;hp=bea603ce49667b7a8c6f4053816b24d9ebbb4c0d;hpb=7848e68c1635ccba5a08d55314d4e5aed5ab54b9;p=oota-llvm.git diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index bea603ce496..456c457a316 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -13,26 +13,40 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "regalloc" +#include "llvm/BasicBlock.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "Support/CommandLine.h" -#include "Support/Debug.h" -#include "Support/DenseMap.h" -#include "Support/Statistic.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/Compiler.h" +#include "llvm/ADT/IndexedMap.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/Statistic.h" +#include using namespace llvm; +STATISTIC(NumStores, "Number of stores added"); +STATISTIC(NumLoads , "Number of loads added"); +STATISTIC(NumFolded, "Number of loads/stores folded into instructions"); + namespace { - Statistic<> NumStores("ra-local", "Number of stores added"); - Statistic<> NumLoads ("ra-local", "Number of loads added"); - Statistic<> NumFolded("ra-local", "Number of loads/stores folded into " - "instructions"); - class RA : public MachineFunctionPass { + static RegisterRegAlloc + localRegAlloc("local", " local register allocator", + createLocalRegisterAllocator); + + + class VISIBILITY_HIDDEN RALocal : public MachineFunctionPass { + public: + static char ID; + RALocal() : MachineFunctionPass((intptr_t)&ID) {} + private: const TargetMachine *TM; MachineFunction *MF; const MRegisterInfo *RegInfo; @@ -44,7 +58,7 @@ namespace { // Virt2PhysRegMap - This map contains entries for each virtual register // that is currently available in a physical register. - DenseMap Virt2PhysRegMap; + IndexedMap Virt2PhysRegMap; unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) { return Virt2PhysRegMap[VirtReg]; @@ -55,8 +69,9 @@ namespace { // Virt2PhysRegMap). The value mapped to is the virtual register // corresponding to the physical register (the inverse of the // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned - // because it is used by a future instruction. If the entry for a physical - // register is -1, then the physical register is "not in the map". + // because it is used by a future instruction, and to -2 if it is not + // allocatable. If the entry for a physical register is -1, then the + // physical register is "not in the map". // std::vector PhysRegsUsed; @@ -91,9 +106,17 @@ namespace { return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; } + void AddToPhysRegsUseOrder(unsigned Reg) { + std::vector::iterator It = + std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg); + if (It != PhysRegsUseOrder.end()) + PhysRegsUseOrder.erase(It); + PhysRegsUseOrder.push_back(Reg); + } + void MarkPhysRegRecentlyUsed(unsigned Reg) { - if(PhysRegsUseOrder.empty() || - PhysRegsUseOrder.back() == Reg) return; // Already most recently used + if (PhysRegsUseOrder.empty() || + PhysRegsUseOrder.back() == Reg) return; // Already most recently used for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) if (areRegsEqual(Reg, PhysRegsUseOrder[i-1])) { @@ -169,13 +192,6 @@ namespace { /// void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg); - /// liberatePhysReg - Make sure the specified physical register is available - /// for use. If there is currently a value in it, it is either moved out of - /// the way or spilled to memory. - /// - void liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, - unsigned PhysReg); - /// isPhysRegAvailable - Return true if the specified physical register is /// free and available for use. This also includes checking to see if /// aliased registers are all free... @@ -208,16 +224,17 @@ namespace { /// MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, unsigned OpNum); - + void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, unsigned PhysReg); }; + char RALocal::ID = 0; } /// getStackSpaceFor - This allocates space for the specified virtual register /// to be held on the stack. -int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { +int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { // Find the location Reg would belong... std::map::iterator I =StackSlotForVirtReg.lower_bound(VirtReg); @@ -225,7 +242,8 @@ int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { return I->second; // Already has space allocated? // Allocate a new stack object for this spill location... - int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC); + int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(), + RC->getAlignment()); // Assign the slot... StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx)); @@ -236,7 +254,7 @@ int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { /// removePhysReg - This method marks the specified physical register as no /// longer being in use. /// -void RA::removePhysReg(unsigned PhysReg) { +void RALocal::removePhysReg(unsigned PhysReg) { PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used std::vector::iterator It = @@ -250,15 +268,16 @@ void RA::removePhysReg(unsigned PhysReg) { /// virtual register slot specified by VirtReg. It then updates the RA data /// structures to indicate the fact that PhysReg is now available. /// -void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg) { +void RALocal::spillVirtReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned VirtReg, unsigned PhysReg) { assert(VirtReg && "Spilling a physical register is illegal!" " Must not have appropriate kill for the register or use exists beyond" " the intended one."); - DEBUG(std::cerr << " Spilling register " << RegInfo->getName(PhysReg); - std::cerr << " containing %reg" << VirtReg; - if (!isVirtRegModified(VirtReg)) - std::cerr << " which has not been modified, so no store necessary!"); + DOUT << " Spilling register " << RegInfo->getName(PhysReg) + << " containing %reg" << VirtReg; + if (!isVirtRegModified(VirtReg)) + DOUT << " which has not been modified, so no store necessary!"; // Otherwise, there is a virtual register corresponding to this physical // register. We only need to spill it into its stack slot if it has been @@ -266,14 +285,14 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (isVirtRegModified(VirtReg)) { const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); int FrameIndex = getStackSpaceFor(VirtReg, RC); - DEBUG(std::cerr << " to stack slot #" << FrameIndex); + DOUT << " to stack slot #" << FrameIndex; RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC); ++NumStores; // Update statistics } getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available - DEBUG(std::cerr << "\n"); + DOUT << "\n"; removePhysReg(PhysReg); } @@ -283,19 +302,21 @@ void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, /// then the request is ignored if the physical register does not contain a /// virtual register. /// -void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, - unsigned PhysReg, bool OnlyVirtRegs) { +void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, + unsigned PhysReg, bool OnlyVirtRegs) { if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used! + assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!"); if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs) spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg); } else { // If the selected register aliases any other registers, we must make - // sure that one of the aliases isn't alive... + // sure that one of the aliases isn't alive. for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); *AliasSet; ++AliasSet) - if (PhysRegsUsed[*AliasSet] != -1) // Spill aliased register... - if (PhysRegsUsed[*AliasSet] || !OnlyVirtRegs) - spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); + if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. + PhysRegsUsed[*AliasSet] != -2) // If allocatable. + if (PhysRegsUsed[*AliasSet]) + spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); } } @@ -304,13 +325,13 @@ void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, /// that PhysReg is the proper container for VirtReg now. The physical /// register must not be used for anything else when this is called. /// -void RA::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { +void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!"); // Update information to note the fact that this register was just used, and // it holds VirtReg. PhysRegsUsed[PhysReg] = VirtReg; getVirt2PhysRegMapSlot(VirtReg) = PhysReg; - PhysRegsUseOrder.push_back(PhysReg); // New use of PhysReg + AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg } @@ -318,7 +339,7 @@ void RA::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { /// and available for use. This also includes checking to see if aliased /// registers are all free... /// -bool RA::isPhysRegAvailable(unsigned PhysReg) const { +bool RALocal::isPhysRegAvailable(unsigned PhysReg) const { if (PhysRegsUsed[PhysReg] != -1) return false; // If the selected register aliases any other allocated registers, it is @@ -334,7 +355,7 @@ bool RA::isPhysRegAvailable(unsigned PhysReg) const { /// getFreeReg - Look to see if there is a free register available in the /// specified register class. If not, return 0. /// -unsigned RA::getFreeReg(const TargetRegisterClass *RC) { +unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) { // Get iterators defining the range of registers that are valid to allocate in // this class, which also specifies the preferred allocation order. TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); @@ -349,55 +370,12 @@ unsigned RA::getFreeReg(const TargetRegisterClass *RC) { } -/// liberatePhysReg - Make sure the specified physical register is available for -/// use. If there is currently a value in it, it is either moved out of the way -/// or spilled to memory. -/// -void RA::liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, - unsigned PhysReg) { - // FIXME: This code checks to see if a register is available, but it really - // wants to know if a reg is available BEFORE the instruction executes. If - // called after killed operands are freed, it runs the risk of reallocating a - // used operand... -#if 0 - if (isPhysRegAvailable(PhysReg)) return; // Already available... - - // Check to see if the register is directly used, not indirectly used through - // aliases. If aliased registers are the ones actually used, we cannot be - // sure that we will be able to save the whole thing if we do a reg-reg copy. - if (PhysRegsUsed[PhysReg] != -1) { - // The virtual register held... - unsigned VirtReg = PhysRegsUsed[PhysReg]->second; - - // Check to see if there is a compatible register available. If so, we can - // move the value into the new register... - // - const TargetRegisterClass *RC = RegInfo->getRegClass(PhysReg); - if (unsigned NewReg = getFreeReg(RC)) { - // Emit the code to copy the value... - RegInfo->copyRegToReg(MBB, I, NewReg, PhysReg, RC); - - // Update our internal state to indicate that PhysReg is available and Reg - // isn't. - getVirt2PhysRegMapSlot[VirtReg] = 0; - removePhysReg(PhysReg); // Free the physreg - - // Move reference over to new register... - assignVirtToPhysReg(VirtReg, NewReg); - return; - } - } -#endif - spillPhysReg(MBB, I, PhysReg); -} - - /// getReg - Find a physical register to hold the specified virtual /// register. If all compatible physical registers are used, this method spills /// the last used virtual register to the stack, and uses that register. /// -unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I, - unsigned VirtReg) { +unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I, + unsigned VirtReg) { const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg); // First check to see if we have a free register of the requested type... @@ -421,18 +399,27 @@ unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I, // physical register! assert(PhysRegsUsed[R] != -1 && "PhysReg in PhysRegsUseOrder, but is not allocated?"); - if (PhysRegsUsed[R]) { + if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) { // If the current register is compatible, use it. - if (RegInfo->getRegClass(R) == RC) { + if (RC->contains(R)) { PhysReg = R; break; } else { // If one of the registers aliased to the current register is // compatible, use it. - for (const unsigned *AliasSet = RegInfo->getAliasSet(R); - *AliasSet; ++AliasSet) { - if (RegInfo->getRegClass(*AliasSet) == RC) { - PhysReg = *AliasSet; // Take an aliased register + for (const unsigned *AliasIt = RegInfo->getAliasSet(R); + *AliasIt; ++AliasIt) { + if (RC->contains(*AliasIt) && + // If this is pinned down for some reason, don't use it. For + // example, if CL is pinned, and we run across CH, don't use + // CH as justification for using scavenging ECX (which will + // fail). + PhysRegsUsed[*AliasIt] != 0 && + + // Make sure the register is allocatable. Don't allocate SIL on + // x86-32. + PhysRegsUsed[*AliasIt] != -2) { + PhysReg = *AliasIt; // Take an aliased register break; } } @@ -464,15 +451,15 @@ unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I, /// subsequent instructions can use the reloaded value. This method returns the /// modified instruction. /// -MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, - unsigned OpNum) { +MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, + unsigned OpNum) { unsigned VirtReg = MI->getOperand(OpNum).getReg(); // If the virtual register is already available, just update the instruction // and return. if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) { MarkPhysRegRecentlyUsed(PR); // Already have this value available! - MI->SetMachineOperandReg(OpNum, PR); // Assign the input register + MI->getOperand(OpNum).setReg(PR); // Assign the input register return MI; } @@ -502,37 +489,103 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded - DEBUG(std::cerr << " Reloading %reg" << VirtReg << " into " - << RegInfo->getName(PhysReg) << "\n"); + DOUT << " Reloading %reg" << VirtReg << " into " + << RegInfo->getName(PhysReg) << "\n"; // Add move instruction(s) RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC); ++NumLoads; // Update statistics - MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register + MF->setPhysRegUsed(PhysReg); + MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register return MI; } +/// isReadModWriteImplicitKill - True if this is an implicit kill for a +/// read/mod/write register, i.e. update partial register. +static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && + MO.isDef() && !MO.isDead()) + return true; + } + return false; +} +/// isReadModWriteImplicitDef - True if this is an implicit def for a +/// read/mod/write register, i.e. update partial register. +static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.getReg() == Reg && MO.isImplicit() && + !MO.isDef() && MO.isKill()) + return true; + } + return false; +} -void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { +void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { // loop over each instruction - MachineBasicBlock::iterator MI = MBB.begin(); - for (; MI != MBB.end(); ++MI) { - const TargetInstrDescriptor &TID = TM->getInstrInfo()->get(MI->getOpcode()); - DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI; - std::cerr << " Regs have values: "; + MachineBasicBlock::iterator MII = MBB.begin(); + const TargetInstrInfo &TII = *TM->getInstrInfo(); + + DEBUG(const BasicBlock *LBB = MBB.getBasicBlock(); + if (LBB) DOUT << "\nStarting RegAlloc of BB: " << LBB->getName()); + + // If this is the first basic block in the machine function, add live-in + // registers as active. + if (&MBB == &*MF->begin()) { + for (MachineFunction::livein_iterator I = MF->livein_begin(), + E = MF->livein_end(); I != E; ++I) { + unsigned Reg = I->first; + MF->setPhysRegUsed(Reg); + PhysRegsUsed[Reg] = 0; // It is free and reserved now + AddToPhysRegsUseOrder(Reg); + for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + AddToPhysRegsUseOrder(*AliasSet); + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + MF->setPhysRegUsed(*AliasSet); + } + } + } + } + + // Otherwise, sequentially allocate each instruction in the MBB. + while (MII != MBB.end()) { + MachineInstr *MI = MII++; + const TargetInstrDescriptor &TID = TII.get(MI->getOpcode()); + DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; + DOUT << " Regs have values: "; for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) - if (PhysRegsUsed[i] != -1) - std::cerr << "[" << RegInfo->getName(i) - << ",%reg" << PhysRegsUsed[i] << "] "; - std::cerr << "\n"); + if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) + DOUT << "[" << RegInfo->getName(i) + << ",%reg" << PhysRegsUsed[i] << "] "; + DOUT << "\n"); // Loop over the implicit uses, making sure that they are at the head of the // use order list, so they don't get reallocated. - for (const unsigned *ImplicitUses = TID.ImplicitUses; - *ImplicitUses; ++ImplicitUses) - MarkPhysRegRecentlyUsed(*ImplicitUses); + if (TID.ImplicitUses) { + for (const unsigned *ImplicitUses = TID.ImplicitUses; + *ImplicitUses; ++ImplicitUses) + MarkPhysRegRecentlyUsed(*ImplicitUses); + } + + SmallVector Kills; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.isKill()) { + if (!MO.isImplicit()) + Kills.push_back(MO.getReg()); + else if (!isReadModWriteImplicitKill(MI, MO.getReg())) + // These are extra physical register kills when a sub-register + // is defined (def of a sub-register is a read/mod/write of the + // larger registers). Ignore. + Kills.push_back(MO.getReg()); + } + } // Get the used operands into registers. This has the potential to spill // incoming values if we are out of registers. Note that we completely @@ -543,18 +596,17 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) - if (!MO.isDef() && MO.isRegister() && MO.getReg() && + if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && MRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } - // If this instruction is the last user of anything in registers, kill the + // If this instruction is the last user of this register, kill the // value, freeing the register being used, so it doesn't need to be // spilled to memory. // - for (LiveVariables::killed_iterator KI = LV->killed_begin(MI), - KE = LV->killed_end(MI); KI != KE; ++KI) { - unsigned VirtReg = KI->second; + for (unsigned i = 0, e = Kills.size(); i != e; ++i) { + unsigned VirtReg = Kills[i]; unsigned PhysReg = VirtReg; if (MRegisterInfo::isVirtualRegister(VirtReg)) { // If the virtual register was never materialized into a register, it @@ -562,12 +614,27 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; PhysRegSlot = 0; + } else if (PhysRegsUsed[PhysReg] == -2) { + // Unallocatable register dead, ignore. + continue; + } else { + assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) && + "Silently clearing a virtual register?"); } if (PhysReg) { - DEBUG(std::cerr << " Last use of " << RegInfo->getName(PhysReg) - << "[%reg" << VirtReg <<"], removing it from live set\n"); + DOUT << " Last use of " << RegInfo->getName(PhysReg) + << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(PhysReg); + for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + DOUT << " Last use of " + << RegInfo->getName(*AliasSet) + << "[%reg" << VirtReg <<"], removing it from live set\n"; + removePhysReg(*AliasSet); + } + } } } @@ -575,42 +642,68 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // are defined, and marking explicit destinations in the PhysRegsUsed map. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isDef() && MO.isRegister() && MO.getReg() && + if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && MRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); - spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg + if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. + // These are extra physical register defs when a sub-register + // is defined (def of a sub-register is a read/mod/write of the + // larger registers). Ignore. + if (isReadModWriteImplicitDef(MI, MO.getReg())) continue; + + MF->setPhysRegUsed(Reg); + spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg PhysRegsUsed[Reg] = 0; // It is free and reserved now - PhysRegsUseOrder.push_back(Reg); - for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); + AddToPhysRegsUseOrder(Reg); + + for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); *AliasSet; ++AliasSet) { - PhysRegsUseOrder.push_back(*AliasSet); - PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + if (PhysRegsUsed[*AliasSet] != -2) { + MF->setPhysRegUsed(*AliasSet); + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + AddToPhysRegsUseOrder(*AliasSet); + } } } } // Loop over the implicit defs, spilling them as well. - for (const unsigned *ImplicitDefs = TID.ImplicitDefs; - *ImplicitDefs; ++ImplicitDefs) { - unsigned Reg = *ImplicitDefs; - spillPhysReg(MBB, MI, Reg, true); - PhysRegsUseOrder.push_back(Reg); - PhysRegsUsed[Reg] = 0; // It is free and reserved now - for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); - *AliasSet; ++AliasSet) { - PhysRegsUseOrder.push_back(*AliasSet); - PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + if (TID.ImplicitDefs) { + for (const unsigned *ImplicitDefs = TID.ImplicitDefs; + *ImplicitDefs; ++ImplicitDefs) { + unsigned Reg = *ImplicitDefs; + if (PhysRegsUsed[Reg] != -2) { + spillPhysReg(MBB, MI, Reg, true); + AddToPhysRegsUseOrder(Reg); + PhysRegsUsed[Reg] = 0; // It is free and reserved now + } + MF->setPhysRegUsed(Reg); + for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + AddToPhysRegsUseOrder(*AliasSet); + PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + MF->setPhysRegUsed(*AliasSet); + } + } } } + SmallVector DeadDefs; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand& MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDead()) + DeadDefs.push_back(MO.getReg()); + } + // Okay, we have allocated all of the source operands and spilled any values // that would be destroyed by defs of this instruction. Loop over the - // implicit defs and assign them to a register, spilling incoming values if + // explicit defs and assign them to a register, spilling incoming values if // we need to scavenge a register. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); - if (MO.isDef() && MO.isRegister() && MO.getReg() && + if (MO.isRegister() && MO.isDef() && MO.getReg() && MRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; @@ -618,50 +711,71 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // If DestVirtReg already has a value, use it. if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) DestPhysReg = getReg(MBB, MI, DestVirtReg); + MF->setPhysRegUsed(DestPhysReg); markVirtRegModified(DestVirtReg); - MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register + MI->getOperand(i).setReg(DestPhysReg); // Assign the output register } } // If this instruction defines any registers that are immediately dead, // kill them now. // - for (LiveVariables::killed_iterator KI = LV->dead_begin(MI), - KE = LV->dead_end(MI); KI != KE; ++KI) { - unsigned VirtReg = KI->second; + for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { + unsigned VirtReg = DeadDefs[i]; unsigned PhysReg = VirtReg; if (MRegisterInfo::isVirtualRegister(VirtReg)) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; assert(PhysReg != 0); PhysRegSlot = 0; + } else if (PhysRegsUsed[PhysReg] == -2) { + // Unallocatable register dead, ignore. + continue; } if (PhysReg) { - DEBUG(std::cerr << " Register " << RegInfo->getName(PhysReg) + DOUT << " Register " << RegInfo->getName(PhysReg) << " [%reg" << VirtReg - << "] is never used, removing it frame live list\n"); + << "] is never used, removing it frame live list\n"; removePhysReg(PhysReg); + for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg); + *AliasSet; ++AliasSet) { + if (PhysRegsUsed[*AliasSet] != -2) { + DOUT << " Register " << RegInfo->getName(*AliasSet) + << " [%reg" << *AliasSet + << "] is never used, removing it frame live list\n"; + removePhysReg(*AliasSet); + } + } } } + + // Finally, if this is a noop copy instruction, zap it. + unsigned SrcReg, DstReg; + if (TII.isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg) { + LV->removeVirtualRegistersKilled(MI); + LV->removeVirtualRegistersDead(MI); + MBB.erase(MI); + } } - MI = MBB.getFirstTerminator(); + MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); // Spill all physical registers holding virtual registers now. for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) - if (PhysRegsUsed[i] != -1) + if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) if (unsigned VirtReg = PhysRegsUsed[i]) spillVirtReg(MBB, MI, VirtReg, i); else removePhysReg(i); -#ifndef NDEBUG +#if 0 + // This checking code is very expensive. bool AllOk = true; for (unsigned i = MRegisterInfo::FirstVirtualRegister, e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i) if (unsigned PR = Virt2PhysRegMap[i]) { - std::cerr << "Register still mapped: " << i << " -> " << PR << "\n"; + cerr << "Register still mapped: " << i << " -> " << PR << "\n"; AllOk = false; } assert(AllOk && "Virtual registers still in phys regs?"); @@ -676,14 +790,24 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { /// runOnMachineFunction - Register allocate the whole function /// -bool RA::runOnMachineFunction(MachineFunction &Fn) { - DEBUG(std::cerr << "Machine Function " << "\n"); +bool RALocal::runOnMachineFunction(MachineFunction &Fn) { + DOUT << "Machine Function " << "\n"; MF = &Fn; TM = &Fn.getTarget(); RegInfo = TM->getRegisterInfo(); LV = &getAnalysis(); PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); + + // At various places we want to efficiently check to see whether a register + // is allocatable. To handle this, we mark all unallocatable registers as + // being pinned down, permanently. + { + BitVector Allocable = RegInfo->getAllocatableSet(Fn); + for (unsigned i = 0, e = Allocable.size(); i != e; ++i) + if (!Allocable[i]) + PhysRegsUsed[i] = -2; // Mark the reg unallocable. + } // initialize the virtual->physical register map to have a 'null' // mapping for all virtual registers @@ -702,5 +826,5 @@ bool RA::runOnMachineFunction(MachineFunction &Fn) { } FunctionPass *llvm::createLocalRegisterAllocator() { - return new RA(); + return new RALocal(); }