X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMachineInstr.cpp;h=a3485bc524c9bd7e9baca5e5f08498f465d05fca;hb=be6781b5d00107f4b60797c3ebdc0aab110487ff;hp=34a2a7d62842aafb2aa7d18b7755b957fe2fa276;hpb=48d7c069c76882475c23de153bda9483cd3c9bb4;p=oota-llvm.git diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 34a2a7d6284..a3485bc524c 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -9,51 +9,66 @@ // // Methods common to all machine instructions. // -// FIXME: Now that MachineInstrs have parent pointers, they should always -// print themselves using their MachineFunction's TargetMachine. -// //===----------------------------------------------------------------------===// #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Value.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/MRegisterInfo.h" #include "llvm/Support/LeakDetector.h" -#include - +#include "llvm/Support/Streams.h" +#include using namespace llvm; -// Global variable holding an array of descriptors for machine instructions. -// The actual object needs to be created separately for each target machine. -// This variable is initialized and reset by class TargetInstrInfo. -// -// FIXME: This should be a property of the target so that more than one target -// at a time can be active... -// -namespace llvm { - extern const TargetInstrDescriptor *TargetInstrDescriptors; -} - -// Constructor for instructions with variable #operands -MachineInstr::MachineInstr(short opcode, unsigned numOperands) - : Opcode(opcode), - numImplicitRefs(0), - operands(numOperands, MachineOperand()), - parent(0) { +/// MachineInstr ctor - This constructor creates a dummy MachineInstr with +/// TID NULL and no operands. +MachineInstr::MachineInstr() + : TID(0), NumImplicitOps(0), parent(0) { // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); } -/// MachineInstr ctor - This constructor only does a _reserve_ of the operands, -/// not a resize for them. It is expected that if you use this that you call -/// add* methods below to fill up the operands, instead of the Set methods. -/// Eventually, the "resizing" ctors will be phased out. -/// -MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) - : Opcode(opcode), numImplicitRefs(0), parent(0) { - operands.reserve(numOperands); +void MachineInstr::addImplicitDefUseOperands() { + if (TID->ImplicitDefs) + for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) { + MachineOperand Op; + Op.opType = MachineOperand::MO_Register; + Op.IsDef = true; + Op.IsImp = true; + Op.IsKill = false; + Op.IsDead = false; + Op.contents.RegNo = *ImpDefs; + Operands.push_back(Op); + } + if (TID->ImplicitUses) + for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) { + MachineOperand Op; + Op.opType = MachineOperand::MO_Register; + Op.IsDef = false; + Op.IsImp = true; + Op.IsKill = false; + Op.IsDead = false; + Op.contents.RegNo = *ImpUses; + Operands.push_back(Op); + } +} + +/// MachineInstr ctor - This constructor create a MachineInstr and add the +/// implicit operands. It reserves space for number of operands specified by +/// TargetInstrDescriptor or the numOperands if it is not zero. (for +/// instructions with variable number of operands). +MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp) + : TID(&tid), NumImplicitOps(0), parent(0) { + if (!NoImp && TID->ImplicitDefs) + for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (!NoImp && TID->ImplicitUses) + for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->numOperands); + if (!NoImp) + addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); } @@ -61,11 +76,18 @@ MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) /// MachineInstr ctor - Work exactly the same as the ctor above, except that the /// MachineInstr is created and added to the end of the specified basic block. /// -MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, - unsigned numOperands) - : Opcode(opcode), numImplicitRefs(0), parent(0) { +MachineInstr::MachineInstr(MachineBasicBlock *MBB, + const TargetInstrDescriptor &tid) + : TID(&tid), NumImplicitOps(0), parent(0) { assert(MBB && "Cannot use inserting ctor with null basic block!"); - operands.reserve(numOperands); + if (TID->ImplicitDefs) + for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) + NumImplicitOps++; + if (TID->ImplicitUses) + for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) + NumImplicitOps++; + Operands.reserve(NumImplicitOps + TID->numOperands); + addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); MBB->push_back(this); // Add instruction to end of basic block! @@ -74,13 +96,13 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, /// MachineInstr ctor - Copies MachineInstr arg exactly /// MachineInstr::MachineInstr(const MachineInstr &MI) { - Opcode = MI.getOpcode(); - numImplicitRefs = MI.getNumImplicitRefs(); - operands.reserve(MI.getNumOperands()); + TID = MI.getInstrDescriptor(); + NumImplicitOps = MI.NumImplicitOps; + Operands.reserve(MI.getNumOperands()); // Add operands - for (unsigned i = 0; i < MI.getNumOperands(); ++i) - operands.push_back(MachineOperand(MI.getOperand(i))); + for (unsigned i = 0; i != MI.getNumOperands(); ++i) + Operands.push_back(MI.getOperand(i)); // Set parent, next, and prev to null parent = 0; @@ -93,11 +115,10 @@ MachineInstr::~MachineInstr() { LeakDetector::removeGarbageObject(this); } -/// clone - Create a copy of 'this' instruction that is identical in all ways -/// except the following: the new instruction has no parent and it has no name +/// getOpcode - Returns the opcode of this MachineInstr. /// -MachineInstr* MachineInstr::clone() const { - return new MachineInstr(*this); +int MachineInstr::getOpcode() const { + return TID->Opcode; } /// removeFromParent - This method unlinks 'this' from the containing basic @@ -112,123 +133,152 @@ MachineInstr *MachineInstr::removeFromParent() { /// OperandComplete - Return true if it's illegal to add a new operand /// bool MachineInstr::OperandsComplete() const { - int NumOperands = TargetInstrDescriptors[Opcode].numOperands; - if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) + unsigned short NumOperands = TID->numOperands; + if ((TID->Flags & M_VARIABLE_OPS) == 0 && + getNumOperands()-NumImplicitOps >= NumOperands) return true; // Broken: we have all the operands of this instruction! return false; } -/// replace - Support for replacing opcode and operands of a MachineInstr in -/// place. This only resets the size of the operand vector and initializes it. -/// The new operands must be set explicitly later. +/// getNumExplicitOperands - Returns the number of non-implicit operands. /// -void MachineInstr::replace(short opcode, unsigned numOperands) { - assert(getNumImplicitRefs() == 0 && - "This is probably broken because implicit refs are going to be lost."); - Opcode = opcode; - operands.clear(); - operands.resize(numOperands, MachineOperand()); +unsigned MachineInstr::getNumExplicitOperands() const { + unsigned NumOperands = TID->numOperands; + if ((TID->Flags & M_VARIABLE_OPS) == 0) + return NumOperands; + + for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { + const MachineOperand &MO = getOperand(NumOperands); + if (!MO.isRegister() || !MO.isImplicit()) + NumOperands++; + } + return NumOperands; } -void MachineInstr::SetMachineOperandVal(unsigned i, - MachineOperand::MachineOperandType opTy, - Value* V) { - assert(i < operands.size()); // may be explicit or implicit op - operands[i].opType = opTy; - operands[i].contents.value = V; - operands[i].extra.regNum = -1; +/// isIdenticalTo - Return true if this operand is identical to the specified +/// operand. +bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { + if (getType() != Other.getType()) return false; + + switch (getType()) { + default: assert(0 && "Unrecognized operand type"); + case MachineOperand::MO_Register: + return getReg() == Other.getReg() && isDef() == Other.isDef(); + case MachineOperand::MO_Immediate: + return getImm() == Other.getImm(); + case MachineOperand::MO_MachineBasicBlock: + return getMBB() == Other.getMBB(); + case MachineOperand::MO_FrameIndex: + return getFrameIndex() == Other.getFrameIndex(); + case MachineOperand::MO_ConstantPoolIndex: + return getConstantPoolIndex() == Other.getConstantPoolIndex() && + getOffset() == Other.getOffset(); + case MachineOperand::MO_JumpTableIndex: + return getJumpTableIndex() == Other.getJumpTableIndex(); + case MachineOperand::MO_GlobalAddress: + return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); + case MachineOperand::MO_ExternalSymbol: + return !strcmp(getSymbolName(), Other.getSymbolName()) && + getOffset() == Other.getOffset(); + } } -void -MachineInstr::SetMachineOperandConst(unsigned i, - MachineOperand::MachineOperandType opTy, - int intValue) { - assert(i < getNumOperands()); // must be explicit op - assert(TargetInstrDescriptors[Opcode].resultPos != (int) i && - "immed. constant cannot be defined"); - - operands[i].opType = opTy; - operands[i].contents.value = NULL; - operands[i].contents.immedVal = intValue; - operands[i].extra.regNum = -1; - operands[i].flags = 0; +/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of +/// the specific register or -1 if it is not found. It further tightening +/// the search criteria to a use that kills the register if isKill is true. +int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const { + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + const MachineOperand &MO = getOperand(i); + if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg) + if (!isKill || MO.isKill()) + return i; + } + return -1; } - -void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { - assert(i < getNumOperands()); // must be explicit op - - operands[i].opType = MachineOperand::MO_MachineRegister; - operands[i].contents.value = NULL; - operands[i].extra.regNum = regNum; + +/// findRegisterDefOperand() - Returns the MachineOperand that is a def of +/// the specific register or NULL if it is not found. +MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) { + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + MachineOperand &MO = getOperand(i); + if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) + return &MO; + } + return NULL; } -// Used only by the SPARC back-end. -void MachineInstr::SetRegForOperand(unsigned i, int regNum) { - assert(i < getNumOperands()); // must be explicit op - operands[i].setRegForValue(regNum); -} +/// findFirstPredOperandIdx() - Find the index of the first operand in the +/// operand list that is used to represent the predicate. It returns -1 if +/// none is found. +int MachineInstr::findFirstPredOperandIdx() const { + const TargetInstrDescriptor *TID = getInstrDescriptor(); + if (TID->Flags & M_PREDICABLE) { + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) + if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) + return i; + } -// Used only by the SPARC back-end. -void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) { - getImplicitOp(i).setRegForValue(regNum); + return -1; +} + +/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due +/// to two addr elimination. +bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const { + const TargetInstrDescriptor *TID = getInstrDescriptor(); + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + const MachineOperand &MO1 = getOperand(i); + if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { + for (unsigned j = i+1; j < e; ++j) { + const MachineOperand &MO2 = getOperand(j); + if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && + TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i) + return true; + } + } + } + return false; } -/// substituteValue - Substitute all occurrences of Value* oldVal with newVal -/// in all operands and all implicit refs. If defsOnly == true, substitute defs -/// only. -/// -/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865, -/// or make it a static function in that file. +/// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// -unsigned -MachineInstr::substituteValue(const Value* oldVal, Value* newVal, - bool defsOnly, bool notDefsAndUses, - bool& someArgsWereIgnored) -{ - assert((!defsOnly || !notDefsAndUses) && - "notDefsAndUses is irrelevant if defsOnly == true."); - - unsigned numSubst = 0; - - // Substitute operands - for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) - if (*O == oldVal) - if (!defsOnly || - notDefsAndUses && (O.isDef() && !O.isUse()) || - !notDefsAndUses && O.isDef()) - { - O.getMachineOperand().contents.value = newVal; - ++numSubst; - } else - someArgsWereIgnored = true; - - // Substitute implicit refs - for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i) - if (getImplicitRef(i) == oldVal) { - MachineOperand Op = getImplicitOp(i); - if (!defsOnly || - notDefsAndUses && (Op.isDef() && !Op.isUse()) || - !notDefsAndUses && Op.isDef()) - { - Op.contents.value = newVal; - ++numSubst; - } else - someArgsWereIgnored = true; +void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) + continue; + for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { + MachineOperand &MOp = getOperand(j); + if (!MOp.isIdenticalTo(MO)) + continue; + if (MO.isKill()) + MOp.setIsKill(); + else + MOp.setIsDead(); + break; } - return numSubst; + } } -void MachineInstr::dump() const { - std::cerr << " " << *this; +/// copyPredicates - Copies predicate operand(s) from MI. +void MachineInstr::copyPredicates(const MachineInstr *MI) { + const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); + if (TID->Flags & M_PREDICABLE) { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) { + const MachineOperand &MO = MI->getOperand(i); + // Predicated operands must be last operands. + if (MO.isRegister()) + addRegOperand(MO.getReg(), false); + else { + addImmOperand(MO.getImm()); + } + } + } + } } -static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { - os << "(val "; - os << (void*) val; // print address always - if (val && val->hasName()) - os << " " << val->getName(); // print name also, if available - os << ")"; - return os; +void MachineInstr::dump() const { + cerr << " " << *this; } static inline void OutputReg(std::ostream &os, unsigned RegNo, @@ -248,57 +298,13 @@ static void print(const MachineOperand &MO, std::ostream &OS, if (TM) MRI = TM->getRegisterInfo(); - bool CloseParen = true; - if (MO.isHiBits32()) - OS << "%lm("; - else if (MO.isLoBits32()) - OS << "%lo("; - else if (MO.isHiBits64()) - OS << "%hh("; - else if (MO.isLoBits64()) - OS << "%hm("; - else - CloseParen = false; - switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: - if (MO.getVRegValue()) { - OS << "%reg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) - OS << "=="; - } - if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getReg(), MRI); + case MachineOperand::MO_Register: + OutputReg(OS, MO.getReg(), MRI); break; - case MachineOperand::MO_CCRegister: - OS << "%ccreg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) { - OS << "=="; - OutputReg(OS, MO.getReg(), MRI); - } + case MachineOperand::MO_Immediate: + OS << MO.getImmedValue(); break; - case MachineOperand::MO_MachineRegister: - OutputReg(OS, MO.getMachineRegNum(), MRI); - break; - case MachineOperand::MO_SignExtendedImmed: - OS << (long)MO.getImmedValue(); - break; - case MachineOperand::MO_UnextendedImmed: - OS << (long)MO.getImmedValue(); - break; - case MachineOperand::MO_PCRelativeDisp: { - const Value* opVal = MO.getVRegValue(); - bool isLabel = isa(opVal) || isa(opVal); - OS << "%disp(" << (isLabel? "label " : "addr-of-val "); - if (opVal->hasName()) - OS << opVal->getName(); - else - OS << (const void*) opVal; - OS << ")"; - break; - } case MachineOperand::MO_MachineBasicBlock: OS << "mbb<" << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() @@ -310,6 +316,9 @@ static void print(const MachineOperand &MO, std::ostream &OS, case MachineOperand::MO_ConstantPoolIndex: OS << ""; break; + case MachineOperand::MO_JumpTableIndex: + OS << ""; + break; case MachineOperand::MO_GlobalAddress: OS << "getName(); if (MO.getOffset()) OS << "+" << MO.getOffset(); @@ -323,25 +332,22 @@ static void print(const MachineOperand &MO, std::ostream &OS, default: assert(0 && "Unrecognized operand type"); } - - if (CloseParen) - OS << ")"; } void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { unsigned StartOp = 0; // Specialize printing if op#0 is definition - if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { + if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { ::print(getOperand(0), OS, TM); + if (getOperand(0).isDead()) + OS << ""; OS << " = "; ++StartOp; // Don't print this operand again! } - // Must check if Target machine is not null because machine BB could not - // be attached to a Machine function yet - if (TM) - OS << TM->getInstrInfo()->getName(getOpcode()); + if (TID) + OS << TID->Name; for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { const MachineOperand& mop = getOperand(i); @@ -350,149 +356,88 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { OS << " "; ::print(mop, OS, TM); - if (mop.isDef()) - if (mop.isUse()) - OS << ""; - else - OS << ""; - } - - // code for printing implicit references - if (getNumImplicitRefs()) { - OS << "\tImplicitRefs: "; - for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { - OS << "\t"; - OutputValue(OS, getImplicitRef(i)); - if (getImplicitOp(i).isDef()) - if (getImplicitOp(i).isUse()) - OS << ""; - else - OS << ""; + if (mop.isRegister()) { + if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) { + OS << "<"; + bool NeedComma = false; + if (mop.isImplicit()) { + OS << (mop.isDef() ? "imp-def" : "imp-use"); + NeedComma = true; + } else if (mop.isDef()) { + OS << "def"; + NeedComma = true; + } + if (mop.isKill() || mop.isDead()) { + if (NeedComma) + OS << ","; + if (mop.isKill()) + OS << "kill"; + if (mop.isDead()) + OS << "dead"; + } + OS << ">"; + } } } OS << "\n"; } -namespace llvm { -std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { +void MachineInstr::print(std::ostream &os) const { // If the instruction is embedded into a basic block, we can find the target // info for the instruction. - if (const MachineBasicBlock *MBB = MI.getParent()) { + if (const MachineBasicBlock *MBB = getParent()) { const MachineFunction *MF = MBB->getParent(); if (MF) - MI.print(os, &MF->getTarget()); + print(os, &MF->getTarget()); else - MI.print(os, 0); - return os; + print(os, 0); } // Otherwise, print it out in the "raw" format without symbolic register names // and such. - os << TargetInstrDescriptors[MI.getOpcode()].Name; + os << getInstrDescriptor()->Name; - for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) { - os << "\t" << MI.getOperand(i); - if (MI.getOperand(i).isDef()) - if (MI.getOperand(i).isUse()) - os << ""; - else - os << ""; - } - - // code for printing implicit references - unsigned NumOfImpRefs = MI.getNumImplicitRefs(); - if (NumOfImpRefs > 0) { - os << "\tImplicit: "; - for (unsigned z = 0; z < NumOfImpRefs; z++) { - OutputValue(os, MI.getImplicitRef(z)); - if (MI.getImplicitOp(z).isDef()) - if (MI.getImplicitOp(z).isUse()) - os << ""; - else - os << ""; - os << "\t"; - } + for (unsigned i = 0, N = getNumOperands(); i < N; i++) { + os << "\t" << getOperand(i); + if (getOperand(i).isRegister() && getOperand(i).isDef()) + os << ""; } - return os << "\n"; + os << "\n"; } -std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { - if (MO.isHiBits32()) - OS << "%lm("; - else if (MO.isLoBits32()) - OS << "%lo("; - else if (MO.isHiBits64()) - OS << "%hh("; - else if (MO.isLoBits64()) - OS << "%hm("; - - switch (MO.getType()) { - case MachineOperand::MO_VirtualRegister: - if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getReg()); - - if (MO.getVRegValue()) { - if (MO.hasAllocatedReg()) OS << "=="; - OS << "%vreg"; - OutputValue(OS, MO.getVRegValue()); - } +void MachineOperand::print(std::ostream &OS) const { + switch (getType()) { + case MO_Register: + OutputReg(OS, getReg()); break; - case MachineOperand::MO_CCRegister: - OS << "%ccreg"; - OutputValue(OS, MO.getVRegValue()); - if (MO.hasAllocatedReg()) { - OS << "=="; - OutputReg(OS, MO.getReg()); - } + case MO_Immediate: + OS << (long)getImmedValue(); break; - case MachineOperand::MO_MachineRegister: - OutputReg(OS, MO.getMachineRegNum()); - break; - case MachineOperand::MO_SignExtendedImmed: - OS << (long)MO.getImmedValue(); - break; - case MachineOperand::MO_UnextendedImmed: - OS << (long)MO.getImmedValue(); - break; - case MachineOperand::MO_PCRelativeDisp: { - const Value* opVal = MO.getVRegValue(); - bool isLabel = isa(opVal) || isa(opVal); - OS << "%disp(" << (isLabel? "label " : "addr-of-val "); - if (opVal->hasName()) - OS << opVal->getName(); - else - OS << (const void*) opVal; - OS << ")"; - break; - } - case MachineOperand::MO_MachineBasicBlock: + case MO_MachineBasicBlock: OS << "getBasicBlock())->getName() - << "@" << (void*)MO.getMachineBasicBlock() << ">"; + << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName() + << "@" << (void*)getMachineBasicBlock() << ">"; break; - case MachineOperand::MO_FrameIndex: - OS << ""; + case MO_FrameIndex: + OS << ""; break; - case MachineOperand::MO_ConstantPoolIndex: - OS << ""; + case MO_ConstantPoolIndex: + OS << ""; break; - case MachineOperand::MO_GlobalAddress: - OS << "getName() << ">"; + case MO_JumpTableIndex: + OS << ""; break; - case MachineOperand::MO_ExternalSymbol: - OS << ""; + case MO_GlobalAddress: + OS << "getName() << ">"; + break; + case MO_ExternalSymbol: + OS << ""; break; default: assert(0 && "Unrecognized operand type"); break; } - - if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) - OS << ")"; - - return OS; } -}