X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FMIRPrinter.cpp;h=175cb0d51437aa84b4cec13c36ad6245d607384e;hb=748e8f493ab4e6f4b346a95cfcb8f05b0a40bc3b;hp=67fd5c226a59e24106a31512dafabbc6d7a42345;hpb=6f3cafb93e92e37c994e47cc2e3aa0a4095a9cfc;p=oota-llvm.git diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp index 67fd5c226a5..175cb0d5143 100644 --- a/lib/CodeGen/MIRPrinter.cpp +++ b/lib/CodeGen/MIRPrinter.cpp @@ -27,6 +27,7 @@ #include "llvm/IR/IRPrintingPasses.h" #include "llvm/IR/Module.h" #include "llvm/IR/ModuleSlotTracker.h" +#include "llvm/MC/MCSymbol.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/YAMLTraits.h" @@ -84,7 +85,8 @@ public: void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI, const MachineJumpTableInfo &JTI); void convertStackObjects(yaml::MachineFunction &MF, - const MachineFrameInfo &MFI, ModuleSlotTracker &MST, + const MachineFrameInfo &MFI, MachineModuleInfo &MMI, + ModuleSlotTracker &MST, const TargetRegisterInfo *TRI); private: @@ -115,7 +117,8 @@ public: void printStackObjectReference(int FrameIndex); void printOffset(int64_t Offset); void printTargetFlags(const MachineOperand &Op); - void print(const MachineOperand &Op, const TargetRegisterInfo *TRI); + void print(const MachineOperand &Op, const TargetRegisterInfo *TRI, + unsigned I, bool ShouldPrintRegisterTies, bool IsDef = false); void print(const MachineMemOperand &Op); void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI); @@ -171,7 +174,7 @@ void MIRPrinter::print(const MachineFunction &MF) { ModuleSlotTracker MST(MF.getFunction()->getParent()); MST.incorporateFunction(*MF.getFunction()); convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo()); - convertStackObjects(YamlMF, *MF.getFrameInfo(), MST, + convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST, MF.getSubtarget().getRegisterInfo()); if (const auto *ConstantPool = MF.getConstantPool()) convert(YamlMF, *ConstantPool); @@ -265,6 +268,7 @@ void MIRPrinter::convert(ModuleSlotTracker &MST, void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF, const MachineFrameInfo &MFI, + MachineModuleInfo &MMI, ModuleSlotTracker &MST, const TargetRegisterInfo *TRI) { // Process fixed stack objects. @@ -342,6 +346,29 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF, MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping) .printStackObjectReference(MFI.getStackProtectorIndex()); } + + // Print the debug variable information. + for (MachineModuleInfo::VariableDbgInfo &DebugVar : + MMI.getVariableDbgInfo()) { + auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot); + assert(StackObjectInfo != StackObjectOperandMapping.end() && + "Invalid stack object index"); + const FrameIndexOperand &StackObject = StackObjectInfo->second; + assert(!StackObject.IsFixed && "Expected a non-fixed stack object"); + auto &Object = MF.StackObjects[StackObject.ID]; + { + raw_string_ostream StrOS(Object.DebugVar.Value); + DebugVar.Var->printAsOperand(StrOS, MST); + } + { + raw_string_ostream StrOS(Object.DebugExpr.Value); + DebugVar.Expr->printAsOperand(StrOS, MST); + } + { + raw_string_ostream StrOS(Object.DebugLoc.Value); + DebugVar.Loc->printAsOperand(StrOS, MST); + } + } } void MIRPrinter::convert(yaml::MachineFunction &MF, @@ -412,7 +439,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { OS << "address-taken"; HasAttributes = true; } - if (MBB.isLandingPad()) { + if (MBB.isEHPad()) { OS << (HasAttributes ? ", " : " ("); OS << "landing-pad"; HasAttributes = true; @@ -434,8 +461,8 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { if (I != MBB.succ_begin()) OS << ", "; printMBBReference(**I); - if (MBB.hasSuccessorWeights()) - OS << '(' << MBB.getSuccWeight(I) << ')'; + if (MBB.hasSuccessorProbabilities()) + OS << '(' << MBB.getSuccProbability(I) << ')'; } OS << "\n"; HasLineAttributes = true; @@ -446,10 +473,14 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { assert(TRI && "Expected target register info"); if (!MBB.livein_empty()) { OS.indent(2) << "liveins: "; - for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) { - if (I != MBB.livein_begin()) + bool First = true; + for (const auto &LI : MBB.liveins()) { + if (!First) OS << ", "; - printReg(*I, OS, TRI); + First = false; + printReg(LI.PhysReg, OS, TRI); + if (LI.LaneMask != ~0u) + OS << ':' << PrintLaneMask(LI.LaneMask); } OS << "\n"; HasLineAttributes = true; @@ -476,6 +507,23 @@ void MIPrinter::print(const MachineBasicBlock &MBB) { OS.indent(2) << "}\n"; } +/// Return true when an instruction has tied register that can't be determined +/// by the instruction's descriptor. +static bool hasComplexRegisterTies(const MachineInstr &MI) { + const MCInstrDesc &MCID = MI.getDesc(); + for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) { + const auto &Operand = MI.getOperand(I); + if (!Operand.isReg() || Operand.isDef()) + // Ignore the defined registers as MCID marks only the uses as tied. + continue; + int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); + int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1; + if (ExpectedTiedIdx != TiedIdx) + return true; + } + return false; +} + void MIPrinter::print(const MachineInstr &MI) { const auto &SubTarget = MI.getParent()->getParent()->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); @@ -485,13 +533,14 @@ void MIPrinter::print(const MachineInstr &MI) { if (MI.isCFIInstruction()) assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); + bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); ++I) { if (I) OS << ", "; - print(MI.getOperand(I), TRI); + print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, /*IsDef=*/true); } if (I) @@ -506,7 +555,7 @@ void MIPrinter::print(const MachineInstr &MI) { for (; I < E; ++I) { if (NeedComma) OS << ", "; - print(MI.getOperand(I), TRI); + print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies); NeedComma = true; } @@ -537,6 +586,13 @@ void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) { } } +static void printIRSlotNumber(raw_ostream &OS, int Slot) { + if (Slot == -1) + OS << ""; + else + OS << Slot; +} + void MIPrinter::printIRBlockReference(const BasicBlock &BB) { OS << "%ir-block."; if (BB.hasName()) { @@ -553,20 +609,27 @@ void MIPrinter::printIRBlockReference(const BasicBlock &BB) { CustomMST.incorporateFunction(*F); Slot = CustomMST.getLocalSlot(&BB); } - if (Slot == -1) - OS << ""; - else - OS << Slot; + printIRSlotNumber(OS, Slot); } void MIPrinter::printIRValueReference(const Value &V) { + if (isa(V)) { + V.printAsOperand(OS, /*PrintType=*/false, MST); + return; + } + if (isa(V)) { + // Machine memory operands can load/store to/from constant value pointers. + OS << '`'; + V.printAsOperand(OS, /*PrintType=*/true, MST); + OS << '`'; + return; + } OS << "%ir."; if (V.hasName()) { printLLVMNameWithoutPrefix(OS, V.getName()); return; } - // TODO: Serialize the unnamed IR value references. - OS << ""; + printIRSlotNumber(OS, MST.getLocalSlot(&V)); } void MIPrinter::printStackObjectReference(int FrameIndex) { @@ -663,13 +726,16 @@ static const char *getTargetIndexName(const MachineFunction &MF, int Index) { return nullptr; } -void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) { +void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, + unsigned I, bool ShouldPrintRegisterTies, bool IsDef) { printTargetFlags(Op); switch (Op.getType()) { case MachineOperand::MO_Register: - // FIXME: Serialize the tied register. if (Op.isImplicit()) OS << (Op.isDef() ? "implicit-def " : "implicit "); + else if (!IsDef && Op.isDef()) + // Print the 'def' flag only when the operand is defined after '='. + OS << "def "; if (Op.isInternalRead()) OS << "internal "; if (Op.isDead()) @@ -686,6 +752,8 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) { // Print the sub register. if (Op.getSubReg() != 0) OS << ':' << TRI->getSubRegIndexName(Op.getSubReg()); + if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef()) + OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")"; break; case MachineOperand::MO_Immediate: OS << Op.getImm(); @@ -764,14 +832,14 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) { case MachineOperand::MO_Metadata: Op.getMetadata()->printAsOperand(OS, MST); break; + case MachineOperand::MO_MCSymbol: + OS << ""; + break; case MachineOperand::MO_CFIIndex: { const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI(); print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI); break; } - default: - // TODO: Print the other machine operands. - llvm_unreachable("Can't print this machine operand at the moment"); } } @@ -814,11 +882,12 @@ void MIPrinter::print(const MachineMemOperand &Op) { cast(PVal)->getFrameIndex()); break; case PseudoSourceValue::GlobalValueCallEntry: + OS << "call-entry "; cast(PVal)->getValue()->printAsOperand( OS, /*PrintType=*/false, MST); break; case PseudoSourceValue::ExternalSymbolCallEntry: - OS << '$'; + OS << "call-entry $"; printLLVMNameWithoutPrefix( OS, cast(PVal)->getSymbol()); break;