X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLiveIntervalAnalysis.cpp;h=e657c46c721eb69b180a8931b05ebc50714889a8;hb=226dd2ba992b1f00491c10c59ca1889825bf92b6;hp=854fb4d7f6d85f398ec1ea4dcb21adc031c800ed;hpb=3de23e6f6cf337451a0934159da494d645b93133;p=oota-llvm.git diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index 854fb4d7f6d..e657c46c721 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -53,15 +53,9 @@ static cl::opt DisableReMat("disable-rematerialization", static cl::opt EnableFastSpilling("fast-spill", cl::init(false), cl::Hidden); -static cl::opt EarlyCoalescing("early-coalescing", cl::init(false)); - -static cl::opt CoalescingLimit("early-coalescing-limit", - cl::init(-1), cl::Hidden); - STATISTIC(numIntervals , "Number of original intervals"); STATISTIC(numFolds , "Number of loads/stores folded into instructions"); STATISTIC(numSplits , "Number of intervals split"); -STATISTIC(numCoalescing, "Number of early coalescing performed"); char LiveIntervals::ID = 0; static RegisterPass X("liveintervals", "Live Interval Analysis"); @@ -95,7 +89,6 @@ void LiveIntervals::releaseMemory() { delete I->second; r2iMap_.clear(); - phiJoinCopies.clear(); // Release VNInfo memroy regions after all VNInfo objects are dtor'd. VNInfoAllocator.Reset(); @@ -120,7 +113,6 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { allocatableRegs_ = tri_->getAllocatableSet(fn); computeIntervals(); - performEarlyCoalescing(); numIntervals += getNumIntervals(); @@ -144,62 +136,91 @@ void LiveIntervals::printInstrs(raw_ostream &OS) const { for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); mbbi != mbbe; ++mbbi) { - OS << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; + OS << "BB#" << mbbi->getNumber() + << ":\t\t# derived from " << mbbi->getName() << "\n"; for (MachineBasicBlock::iterator mii = mbbi->begin(), mie = mbbi->end(); mii != mie; ++mii) { - OS << getInstructionIndex(mii) << '\t' << *mii; + if (mii->isDebugValue()) + OS << " \t" << *mii; + else + OS << getInstructionIndex(mii) << '\t' << *mii; } } } void LiveIntervals::dumpInstrs() const { - printInstrs(errs()); + printInstrs(dbgs()); } -/// conflictsWithPhysRegDef - Returns true if the specified register -/// is defined during the duration of the specified interval. -bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, - VirtRegMap &vrm, unsigned reg) { - for (LiveInterval::Ranges::const_iterator - I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) { - for (SlotIndex index = I->start.getBaseIndex(), - end = I->end.getPrevSlot().getBaseIndex().getNextIndex(); - index != end; - index = index.getNextIndex()) { - // skip deleted instructions - while (index != end && !getInstructionFromIndex(index)) - index = index.getNextIndex(); - if (index == end) break; +bool LiveIntervals::conflictsWithPhysReg(const LiveInterval &li, + VirtRegMap &vrm, unsigned reg) { + // We don't handle fancy stuff crossing basic block boundaries + if (li.ranges.size() != 1) + return true; + const LiveRange &range = li.ranges.front(); + SlotIndex idx = range.start.getBaseIndex(); + SlotIndex end = range.end.getPrevSlot().getBaseIndex().getNextIndex(); + + // Skip deleted instructions + MachineInstr *firstMI = getInstructionFromIndex(idx); + while (!firstMI && idx != end) { + idx = idx.getNextIndex(); + firstMI = getInstructionFromIndex(idx); + } + if (!firstMI) + return false; - MachineInstr *MI = getInstructionFromIndex(index); - unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) - if (SrcReg == li.reg || DstReg == li.reg) - continue; - for (unsigned i = 0; i != MI->getNumOperands(); ++i) { - MachineOperand& mop = MI->getOperand(i); - if (!mop.isReg()) - continue; - unsigned PhysReg = mop.getReg(); - if (PhysReg == 0 || PhysReg == li.reg) + // Find last instruction in range + SlotIndex lastIdx = end.getPrevIndex(); + MachineInstr *lastMI = getInstructionFromIndex(lastIdx); + while (!lastMI && lastIdx != idx) { + lastIdx = lastIdx.getPrevIndex(); + lastMI = getInstructionFromIndex(lastIdx); + } + if (!lastMI) + return false; + + // Range cannot cross basic block boundaries or terminators + MachineBasicBlock *MBB = firstMI->getParent(); + if (MBB != lastMI->getParent() || lastMI->getDesc().isTerminator()) + return true; + + MachineBasicBlock::const_iterator E = lastMI; + ++E; + for (MachineBasicBlock::const_iterator I = firstMI; I != E; ++I) { + const MachineInstr &MI = *I; + + // Allow copies to and from li.reg + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (tii_->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) + if (SrcReg == li.reg || DstReg == li.reg) + continue; + + // Check for operands using reg + for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand& mop = MI.getOperand(i); + if (!mop.isReg()) + continue; + unsigned PhysReg = mop.getReg(); + if (PhysReg == 0 || PhysReg == li.reg) + continue; + if (TargetRegisterInfo::isVirtualRegister(PhysReg)) { + if (!vrm.hasPhys(PhysReg)) continue; - if (TargetRegisterInfo::isVirtualRegister(PhysReg)) { - if (!vrm.hasPhys(PhysReg)) - continue; - PhysReg = vrm.getPhys(PhysReg); - } - if (PhysReg && tri_->regsOverlap(PhysReg, reg)) - return true; + PhysReg = vrm.getPhys(PhysReg); } + if (PhysReg && tri_->regsOverlap(PhysReg, reg)) + return true; } } + // No conflicts found. return false; } -/// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except -/// it can check use as well. -bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li, +/// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except +/// it checks for sub-register reference and it can check use as well. +bool LiveIntervals::conflictsWithSubPhysRegRef(LiveInterval &li, unsigned Reg, bool CheckUse, SmallPtrSet &JoinedCopies) { for (LiveInterval::Ranges::const_iterator @@ -208,15 +229,9 @@ bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li, end = I->end.getPrevSlot().getBaseIndex().getNextIndex(); index != end; index = index.getNextIndex()) { - // Skip deleted instructions. - MachineInstr *MI = 0; - while (index != end) { - MI = getInstructionFromIndex(index); - if (MI) - break; - index = index.getNextIndex(); - } - if (index == end) break; + MachineInstr *MI = getInstructionFromIndex(index); + if (!MI) + continue; // skip deleted instructions if (JoinedCopies.count(MI)) continue; @@ -241,9 +256,9 @@ bool LiveIntervals::conflictsWithPhysRegRef(LiveInterval &li, #ifndef NDEBUG static void printRegName(unsigned reg, const TargetRegisterInfo* tri_) { if (TargetRegisterInfo::isPhysicalRegister(reg)) - errs() << tri_->getName(reg); + dbgs() << tri_->getName(reg); else - errs() << "%reg" << reg; + dbgs() << "%reg" << reg; } #endif @@ -254,7 +269,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, unsigned MOIdx, LiveInterval &interval) { DEBUG({ - errs() << "\t\tregister: "; + dbgs() << "\t\tregister: "; printRegName(interval.reg, tri_); }); @@ -273,9 +288,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, VNInfo *ValNo; MachineInstr *CopyMI = NULL; unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || - mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || + if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg() || tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = mi; // Earlyclobbers move back one. @@ -302,7 +315,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, "Shouldn't be alive across any blocks!"); LiveRange LR(defIndex, killIdx, ValNo); interval.addRange(LR); - DEBUG(errs() << " +" << LR << "\n"); + DEBUG(dbgs() << " +" << LR << "\n"); ValNo->addKill(killIdx); return; } @@ -312,34 +325,50 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // of the defining block, potentially live across some blocks, then is // live into some number of blocks, but gets killed. Start by adding a // range that goes from this definition to the end of the defining block. - LiveRange NewLR(defIndex, getMBBEndIdx(mbb).getNextIndex().getLoadIndex(), - ValNo); - DEBUG(errs() << " +" << NewLR); + LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo); + DEBUG(dbgs() << " +" << NewLR); interval.addRange(NewLR); - // Iterate over all of the blocks that the variable is completely - // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the - // live interval. - for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(), - E = vi.AliveBlocks.end(); I != E; ++I) { - LiveRange LR( - getMBBStartIdx(mf_->getBlockNumbered(*I)), - getMBBEndIdx(mf_->getBlockNumbered(*I)).getNextIndex().getLoadIndex(), - ValNo); - interval.addRange(LR); - DEBUG(errs() << " +" << LR); + bool PHIJoin = lv_->isPHIJoin(interval.reg); + + if (PHIJoin) { + // A phi join register is killed at the end of the MBB and revived as a new + // valno in the killing blocks. + assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks"); + DEBUG(dbgs() << " phi-join"); + ValNo->addKill(indexes_->getTerminatorGap(mbb)); + ValNo->setHasPHIKill(true); + } else { + // Iterate over all of the blocks that the variable is completely + // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the + // live interval. + for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(), + E = vi.AliveBlocks.end(); I != E; ++I) { + MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I); + LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo); + interval.addRange(LR); + DEBUG(dbgs() << " +" << LR); + } } // Finally, this virtual register is live from the start of any killing // block to the 'use' slot of the killing instruction. for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { MachineInstr *Kill = vi.Kills[i]; - SlotIndex killIdx = - getInstructionIndex(Kill).getDefIndex(); - LiveRange LR(getMBBStartIdx(Kill->getParent()), killIdx, ValNo); + SlotIndex Start = getMBBStartIdx(Kill->getParent()); + SlotIndex killIdx = getInstructionIndex(Kill).getDefIndex(); + + // Create interval with one of a NEW value number. Note that this value + // number isn't actually defined by an instruction, weird huh? :) + if (PHIJoin) { + ValNo = interval.getNextValue(SlotIndex(Start, true), 0, false, + VNInfoAllocator); + ValNo->setIsPHIDef(true); + } + LiveRange LR(Start, killIdx, ValNo); interval.addRange(LR); ValNo->addKill(killIdx); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " +" << LR); } } else { @@ -381,12 +410,10 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, // Value#0 is now defined by the 2-addr instruction. OldValNo->def = RedefIndex; OldValNo->setCopy(0); - if (MO.isEarlyClobber()) - OldValNo->setHasRedefByEC(true); // Add the new live interval which replaces the range for the input copy. LiveRange LR(DefIndex, RedefIndex, ValNo); - DEBUG(errs() << " replace range with " << LR); + DEBUG(dbgs() << " replace range with " << LR); interval.addRange(LR); ValNo->addKill(RedefIndex); @@ -397,54 +424,15 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, OldValNo)); DEBUG({ - errs() << " RESULT: "; - interval.print(errs(), tri_); + dbgs() << " RESULT: "; + interval.print(dbgs(), tri_); }); } else { - // Otherwise, this must be because of phi elimination. If this is the - // first redefinition of the vreg that we have seen, go back and change - // the live range in the PHI block to be a different value number. - if (interval.containsOneValue()) { - // Remove the old range that we now know has an incorrect number. - VNInfo *VNI = interval.getValNumInfo(0); - MachineInstr *Killer = vi.Kills[0]; - phiJoinCopies.push_back(Killer); - SlotIndex Start = getMBBStartIdx(Killer->getParent()); - SlotIndex End = getInstructionIndex(Killer).getDefIndex(); - DEBUG({ - errs() << " Removing [" << Start << "," << End << "] from: "; - interval.print(errs(), tri_); - errs() << "\n"; - }); - interval.removeRange(Start, End); - assert(interval.ranges.size() == 1 && - "Newly discovered PHI interval has >1 ranges."); - MachineBasicBlock *killMBB = getMBBFromIndex(interval.endIndex()); - VNI->addKill(indexes_->getTerminatorGap(killMBB)); - VNI->setHasPHIKill(true); - DEBUG({ - errs() << " RESULT: "; - interval.print(errs(), tri_); - }); - - // Replace the interval with one of a NEW value number. Note that this - // value number isn't actually defined by an instruction, weird huh? :) - LiveRange LR(Start, End, - interval.getNextValue(SlotIndex(getMBBStartIdx(mbb), true), - 0, false, VNInfoAllocator)); - LR.valno->setIsPHIDef(true); - DEBUG(errs() << " replace range with " << LR); - interval.addRange(LR); - LR.valno->addKill(End); - DEBUG({ - errs() << " RESULT: "; - interval.print(errs(), tri_); - }); - } - + assert(lv_->isPHIJoin(interval.reg) && "Multiply defined register"); // In the case of PHI elimination, each variable definition is only // live until the end of the block. We've already taken care of the // rest of the live range. + SlotIndex defIndex = MIIdx.getDefIndex(); if (MO.isEarlyClobber()) defIndex = MIIdx.getUseIndex(); @@ -452,23 +440,21 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, VNInfo *ValNo; MachineInstr *CopyMI = NULL; unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || - mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - mi->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || + if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg()|| tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = mi; ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator); - SlotIndex killIndex = getMBBEndIdx(mbb).getNextIndex().getLoadIndex(); + SlotIndex killIndex = getMBBEndIdx(mbb); LiveRange LR(defIndex, killIndex, ValNo); interval.addRange(LR); ValNo->addKill(indexes_->getTerminatorGap(mbb)); ValNo->setHasPHIKill(true); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " phi-join +" << LR); } } - DEBUG(errs() << '\n'); + DEBUG(dbgs() << '\n'); } void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, @@ -480,7 +466,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, // A physical register cannot be live across basic block, so its // lifetime must end somewhere in its defining basic block. DEBUG({ - errs() << "\t\tregister: "; + dbgs() << "\t\tregister: "; printRegName(interval.reg, tri_); }); @@ -497,7 +483,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, // For earlyclobbers, the defSlot was pushed back one; the extra // advance below compensates. if (MO.isDead()) { - DEBUG(errs() << " dead"); + DEBUG(dbgs() << " dead"); end = start.getStoreIndex(); goto exit; } @@ -508,11 +494,13 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, baseIndex = baseIndex.getNextIndex(); while (++mi != MBB->end()) { + if (mi->isDebugValue()) + continue; if (getInstructionFromIndex(baseIndex) == 0) baseIndex = indexes_->getNextNonNullIndex(baseIndex); if (mi->killsRegister(interval.reg, tri_)) { - DEBUG(errs() << " killed"); + DEBUG(dbgs() << " killed"); end = baseIndex.getDefIndex(); goto exit; } else { @@ -521,14 +509,12 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, if (mi->isRegTiedToUseOperand(DefIdx)) { // Two-address instruction. end = baseIndex.getDefIndex(); - assert(!mi->getOperand(DefIdx).isEarlyClobber() && - "Two address instruction is an early clobber?"); } else { // Another instruction redefines the register before it is ever read. - // Then the register is essentially dead at the instruction that defines - // it. Hence its interval is: + // Then the register is essentially dead at the instruction that + // defines it. Hence its interval is: // [defSlot(def), defSlot(def)+1) - DEBUG(errs() << " dead"); + DEBUG(dbgs() << " dead"); end = start.getStoreIndex(); } goto exit; @@ -557,7 +543,7 @@ exit: LiveRange LR(start, end, ValNo); interval.addRange(LR); LR.valno->addKill(end); - DEBUG(errs() << " +" << LR << '\n'); + DEBUG(dbgs() << " +" << LR << '\n'); } void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, @@ -571,9 +557,7 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, else if (allocatableRegs_[MO.getReg()]) { MachineInstr *CopyMI = NULL; unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG || - MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG || + if (MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg() || tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) CopyMI = MI; handlePhysicalRegisterDef(MBB, MI, MIIdx, MO, @@ -592,13 +576,23 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, SlotIndex MIIdx, LiveInterval &interval, bool isAlias) { DEBUG({ - errs() << "\t\tlivein register: "; + dbgs() << "\t\tlivein register: "; printRegName(interval.reg, tri_); }); // Look for kills, if it reaches a def before it's killed, then it shouldn't // be considered a livein. MachineBasicBlock::iterator mi = MBB->begin(); + MachineBasicBlock::iterator E = MBB->end(); + // Skip over DBG_VALUE at the start of the MBB. + if (mi != E && mi->isDebugValue()) { + while (++mi != E && mi->isDebugValue()) + ; + if (mi == E) + // MBB is empty except for DBG_VALUE's. + return; + } + SlotIndex baseIndex = MIIdx; SlotIndex start = baseIndex; if (getInstructionFromIndex(baseIndex) == 0) @@ -606,10 +600,10 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, SlotIndex end = baseIndex; bool SeenDefUse = false; - - while (mi != MBB->end()) { + + while (mi != E) { if (mi->killsRegister(interval.reg, tri_)) { - DEBUG(errs() << " killed"); + DEBUG(dbgs() << " killed"); end = baseIndex.getDefIndex(); SeenDefUse = true; break; @@ -618,25 +612,26 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, // Then the register is essentially dead at the instruction that defines // it. Hence its interval is: // [defSlot(def), defSlot(def)+1) - DEBUG(errs() << " dead"); + DEBUG(dbgs() << " dead"); end = start.getStoreIndex(); SeenDefUse = true; break; } - ++mi; - if (mi != MBB->end()) { + while (++mi != E && mi->isDebugValue()) + // Skip over DBG_VALUE. + ; + if (mi != E) baseIndex = indexes_->getNextNonNullIndex(baseIndex); - } } // Live-in register might not be used at all. if (!SeenDefUse) { if (isAlias) { - DEBUG(errs() << " dead"); + DEBUG(dbgs() << " dead"); end = MIIdx.getStoreIndex(); } else { - DEBUG(errs() << " live through"); + DEBUG(dbgs() << " live through"); end = baseIndex; } } @@ -649,134 +644,7 @@ void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, interval.addRange(LR); LR.valno->addKill(end); - DEBUG(errs() << " +" << LR << '\n'); -} - -bool LiveIntervals:: -isSafeAndProfitableToCoalesce(LiveInterval &DstInt, - LiveInterval &SrcInt, - SmallVector &IdentCopies, - SmallVector &OtherCopies) { - unsigned NumIdent = 0; - for (MachineRegisterInfo::def_iterator ri = mri_->def_begin(SrcInt.reg), - re = mri_->def_end(); ri != re; ++ri) { - MachineInstr *MI = &*ri; - unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) - return false; - if (SrcReg != DstInt.reg) { - // Non-identity copy - we cannot handle overlapping intervals - if (DstInt.liveAt(getInstructionIndex(MI))) - return false; - OtherCopies.push_back(MI); - } else { - IdentCopies.push_back(MI); - ++NumIdent; - } - } - - return IdentCopies.size() > OtherCopies.size(); -} - -void LiveIntervals::performEarlyCoalescing() { - if (!EarlyCoalescing) - return; - - /// Perform early coalescing: eliminate copies which feed into phi joins - /// and whose sources are defined by the phi joins. - for (unsigned i = 0, e = phiJoinCopies.size(); i != e; ++i) { - MachineInstr *Join = phiJoinCopies[i]; - if (CoalescingLimit != -1 && (int)numCoalescing == CoalescingLimit) - break; - - unsigned PHISrc, PHIDst, SrcSubReg, DstSubReg; - bool isMove= tii_->isMoveInstr(*Join, PHISrc, PHIDst, SrcSubReg, DstSubReg); -#ifndef NDEBUG - assert(isMove && "PHI join instruction must be a move!"); -#else - isMove = isMove; -#endif - - LiveInterval &DstInt = getInterval(PHIDst); - LiveInterval &SrcInt = getInterval(PHISrc); - SmallVector IdentCopies; - SmallVector OtherCopies; - if (!isSafeAndProfitableToCoalesce(DstInt, SrcInt, - IdentCopies, OtherCopies)) - continue; - - DEBUG(errs() << "PHI Join: " << *Join); - assert(DstInt.containsOneValue() && "PHI join should have just one val#!"); - assert(std::distance(mri_->use_begin(PHISrc), mri_->use_end()) == 1 && - "PHI join src should not be used elsewhere"); - VNInfo *VNI = DstInt.getValNumInfo(0); - - // Change the non-identity copies to directly target the phi destination. - for (unsigned i = 0, e = OtherCopies.size(); i != e; ++i) { - MachineInstr *PHICopy = OtherCopies[i]; - SlotIndex MIIndex = getInstructionIndex(PHICopy); - DEBUG(errs() << "Moving: " << MIIndex << ' ' << *PHICopy); - SlotIndex DefIndex = MIIndex.getDefIndex(); - LiveRange *SLR = SrcInt.getLiveRangeContaining(DefIndex); - SlotIndex StartIndex = SLR->start; - SlotIndex EndIndex = SLR->end; - - // Delete val# defined by the now identity copy and add the range from - // beginning of the mbb to the end of the range. - SrcInt.removeValNo(SLR->valno); - DEBUG(errs() << " added range [" << StartIndex << ',' - << EndIndex << "] to reg" << DstInt.reg << '\n'); - assert (!DstInt.liveAt(StartIndex) && "Cannot coalesce when dst live!"); - VNInfo *NewVNI = DstInt.getNextValue(DefIndex, PHICopy, true, - VNInfoAllocator); - NewVNI->setHasPHIKill(true); - DstInt.addRange(LiveRange(StartIndex, EndIndex, NewVNI)); - for (unsigned j = 0, ee = PHICopy->getNumOperands(); j != ee; ++j) { - MachineOperand &MO = PHICopy->getOperand(j); - if (!MO.isReg() || MO.getReg() != PHISrc) - continue; - MO.setReg(PHIDst); - } - } - - // Now let's eliminate all the would-be identity copies. - for (unsigned i = 0, e = IdentCopies.size(); i != e; ++i) { - MachineInstr *PHICopy = IdentCopies[i]; - DEBUG(errs() << "Coalescing: " << *PHICopy); - - SlotIndex MIIndex = getInstructionIndex(PHICopy); - SlotIndex DefIndex = MIIndex.getDefIndex(); - LiveRange *SLR = SrcInt.getLiveRangeContaining(DefIndex); - SlotIndex StartIndex = SLR->start; - SlotIndex EndIndex = SLR->end; - - // Delete val# defined by the now identity copy and add the range from - // beginning of the mbb to the end of the range. - SrcInt.removeValNo(SLR->valno); - RemoveMachineInstrFromMaps(PHICopy); - PHICopy->eraseFromParent(); - DEBUG(errs() << " added range [" << StartIndex << ',' - << EndIndex << "] to reg" << DstInt.reg << '\n'); - DstInt.addRange(LiveRange(StartIndex, EndIndex, VNI)); - } - - // Remove the phi join and update the phi block liveness. - SlotIndex MIIndex = getInstructionIndex(Join); - SlotIndex UseIndex = MIIndex.getUseIndex(); - SlotIndex DefIndex = MIIndex.getDefIndex(); - LiveRange *SLR = SrcInt.getLiveRangeContaining(UseIndex); - LiveRange *DLR = DstInt.getLiveRangeContaining(DefIndex); - DLR->valno->setCopy(0); - DLR->valno->setIsDefAccurate(false); - DstInt.addRange(LiveRange(SLR->start, SLR->end, DLR->valno)); - SrcInt.removeRange(SLR->start, SLR->end); - assert(SrcInt.empty()); - removeInterval(PHISrc); - RemoveMachineInstrFromMaps(Join); - Join->eraseFromParent(); - - ++numCoalescing; - } + DEBUG(dbgs() << " +" << LR << '\n'); } /// computeIntervals - computes the live intervals for virtual @@ -784,7 +652,7 @@ void LiveIntervals::performEarlyCoalescing() { /// live interval is an interval [i, j) where 1 <= i <= j < N for /// which a variable is live void LiveIntervals::computeIntervals() { - DEBUG(errs() << "********** COMPUTING LIVE INTERVALS **********\n" + DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n" << "********** Function: " << ((Value*)mf_->getFunction())->getName() << '\n'); @@ -792,11 +660,12 @@ void LiveIntervals::computeIntervals() { for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); MBBI != E; ++MBBI) { MachineBasicBlock *MBB = MBBI; + if (MBB->empty()) + continue; + // Track the index of the current machine instr. SlotIndex MIIndex = getMBBStartIdx(MBB); - DEBUG(errs() << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); - - MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); + DEBUG(dbgs() << MBB->getName() << ":\n"); // Create intervals for live-ins to this BB first. for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(), @@ -813,8 +682,11 @@ void LiveIntervals::computeIntervals() { if (getInstructionFromIndex(MIIndex) == 0) MIIndex = indexes_->getNextNonNullIndex(MIIndex); - for (; MI != miEnd; ++MI) { - DEBUG(errs() << MIIndex << "\t" << *MI); + for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); + MI != miEnd; ++MI) { + DEBUG(dbgs() << MIIndex << "\t" << *MI); + if (MI->isDebugValue()) + continue; // Handle defs. for (int i = MI->getNumOperands() - 1; i >= 0; --i) { @@ -862,14 +734,22 @@ unsigned LiveIntervals::getVNInfoSourceReg(const VNInfo *VNI) const { if (!VNI->getCopy()) return 0; - if (VNI->getCopy()->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { + if (VNI->getCopy()->isExtractSubreg()) { // If it's extracting out of a physical register, return the sub-register. unsigned Reg = VNI->getCopy()->getOperand(1).getReg(); - if (TargetRegisterInfo::isPhysicalRegister(Reg)) + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { + unsigned SrcSubReg = VNI->getCopy()->getOperand(2).getImm(); + unsigned DstSubReg = VNI->getCopy()->getOperand(0).getSubReg(); + if (SrcSubReg == DstSubReg) + // %reg1034:3 = EXTRACT_SUBREG %EDX, 3 + // reg1034 can still be coalesced to EDX. + return Reg; + assert(DstSubReg == 0); Reg = tri_->getSubReg(Reg, VNI->getCopy()->getOperand(2).getImm()); + } return Reg; - } else if (VNI->getCopy()->getOpcode() == TargetInstrInfo::INSERT_SUBREG || - VNI->getCopy()->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) + } else if (VNI->getCopy()->isInsertSubreg() || + VNI->getCopy()->isSubregToReg()) return VNI->getCopy()->getOperand(2).getReg(); unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; @@ -939,8 +819,9 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, unsigned ImpUse = getReMatImplicitUse(li, MI); if (ImpUse) { const LiveInterval &ImpLi = getInterval(ImpUse); - for (MachineRegisterInfo::use_iterator ri = mri_->use_begin(li.reg), - re = mri_->use_end(); ri != re; ++ri) { + for (MachineRegisterInfo::use_nodbg_iterator + ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end(); + ri != re; ++ri) { MachineInstr *UseMI = &*ri; SlotIndex UseIdx = getInstructionIndex(UseMI); if (li.FindLiveRangeContaining(UseIdx)->valno != ValNo) @@ -1031,7 +912,7 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI, SmallVector &Ops, bool isSS, int Slot, unsigned Reg) { // If it is an implicit def instruction, just delete it. - if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { + if (MI->isImplicitDef()) { RemoveMachineInstrFromMaps(MI); vrm.RemoveMachineInstrFromMaps(MI); MI->eraseFromParent(); @@ -1171,8 +1052,8 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, // If this is the rematerializable definition MI itself and // all of its uses are rematerialized, simply delete it. if (MI == ReMatOrigDefMI && CanDelete) { - DEBUG(errs() << "\t\t\t\tErasing re-materlizable def: " - << MI << '\n'); + DEBUG(dbgs() << "\t\t\t\tErasing re-materializable def: " + << *MI << '\n'); RemoveMachineInstrFromMaps(MI); vrm.RemoveMachineInstrFromMaps(MI); MI->eraseFromParent(); @@ -1230,6 +1111,12 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, NewVReg = mri_->createVirtualRegister(rc); vrm.grow(); CreatedNewVReg = true; + + // The new virtual register should get the same allocation hints as the + // old one. + std::pair Hint = mri_->getRegAllocationHint(Reg); + if (Hint.first || Hint.second) + mri_->setRegAllocationHint(NewVReg, Hint.first, Hint.second); } if (!TryFold) @@ -1318,28 +1205,28 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, if (CreatedNewVReg) { LiveRange LR(index.getLoadIndex(), index.getDefIndex(), nI.getNextValue(SlotIndex(), 0, false, VNInfoAllocator)); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " +" << LR); nI.addRange(LR); } else { // Extend the split live interval to this def / use. SlotIndex End = index.getDefIndex(); LiveRange LR(nI.ranges[nI.ranges.size()-1].end, End, nI.getValNumInfo(nI.getNumValNums()-1)); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " +" << LR); nI.addRange(LR); } } if (HasDef) { LiveRange LR(index.getDefIndex(), index.getStoreIndex(), nI.getNextValue(SlotIndex(), 0, false, VNInfoAllocator)); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " +" << LR); nI.addRange(LR); } DEBUG({ - errs() << "\t\t\t\tAdded new interval: "; - nI.print(errs(), tri_); - errs() << '\n'; + dbgs() << "\t\t\t\tAdded new interval: "; + nI.print(dbgs(), tri_); + dbgs() << '\n'; }); } return CanFold; @@ -1354,7 +1241,7 @@ bool LiveIntervals::anyKillInMBBAfterIdx(const LiveInterval &li, continue; SlotIndex KillIdx = VNI->kills[j]; - if (KillIdx > Idx && KillIdx < End) + if (KillIdx > Idx && KillIdx <= End) return true; } return false; @@ -1408,6 +1295,12 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, MachineInstr *MI = &*ri; MachineOperand &O = ri.getOperand(); ++ri; + if (MI->isDebugValue()) { + // Remove debug info for now. + O.setReg(0U); + DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI); + continue; + } assert(!O.isImplicit() && "Spilling register that's used as implicit use?"); SlotIndex index = getInstructionIndex(MI); if (index < start || index >= end) @@ -1451,11 +1344,9 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, MachineBasicBlock *MBB = MI->getParent(); if (ImpUse && MI != ReMatDefMI) { - // Re-matting an instruction with virtual register use. Update the - // register interval's spill weight to HUGE_VALF to prevent it from - // being spilled. - LiveInterval &ImpLi = getInterval(ImpUse); - ImpLi.weight = HUGE_VALF; + // Re-matting an instruction with virtual register use. Prevent interval + // from being spilled. + getInterval(ImpUse).markNotSpillable(); } unsigned MBBId = MBB->getNumber(); @@ -1507,7 +1398,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, LiveInterval &nI = getOrCreateInterval(NewVReg); if (!TrySplit) { // The spill weight is now infinity as it cannot be spilled again. - nI.weight = HUGE_VALF; + nI.markNotSpillable(); continue; } @@ -1630,8 +1521,14 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, MachineOperand &O = ri.getOperand(); MachineInstr *MI = &*ri; ++ri; + if (MI->isDebugValue()) { + // Remove debug info for now. + O.setReg(0U); + DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI); + continue; + } if (O.isDef()) { - assert(MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF && + assert(MI->isImplicitDef() && "Register def was not rewritten?"); RemoveMachineInstrFromMaps(MI); vrm.RemoveMachineInstrFromMaps(MI); @@ -1655,6 +1552,28 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, } } +float +LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) { + // Limit the loop depth ridiculousness. + if (loopDepth > 200) + loopDepth = 200; + + // The loop depth is used to roughly estimate the number of times the + // instruction is executed. Something like 10^d is simple, but will quickly + // overflow a float. This expression behaves like 10^d for small d, but is + // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of + // headroom before overflow. + float lc = powf(1 + (100.0f / (loopDepth+10)), (float)loopDepth); + + return (isDef + isUse) * lc; +} + +void +LiveIntervals::normalizeSpillWeights(std::vector &NewLIs) { + for (unsigned i = 0, e = NewLIs.size(); i != e; ++i) + normalizeSpillWeight(*NewLIs[i]); +} + std::vector LiveIntervals:: addIntervalsForSpillsFast(const LiveInterval &li, const MachineLoopInfo *loopInfo, @@ -1663,13 +1582,12 @@ addIntervalsForSpillsFast(const LiveInterval &li, std::vector added; - assert(li.weight != HUGE_VALF && - "attempt to spill already spilled interval!"); + assert(li.isSpillable() && "attempt to spill already spilled interval!"); DEBUG({ - errs() << "\t\t\t\tadding intervals for spills for interval: "; + dbgs() << "\t\t\t\tadding intervals for spills for interval: "; li.dump(); - errs() << '\n'; + dbgs() << '\n'; }); const TargetRegisterClass* rc = mri_->getRegClass(li.reg); @@ -1700,10 +1618,7 @@ addIntervalsForSpillsFast(const LiveInterval &li, // create a new register for this spill LiveInterval &nI = getOrCreateInterval(NewVReg); - - // the spill weight is now infinity as it - // cannot be spilled again - nI.weight = HUGE_VALF; + nI.markNotSpillable(); // Rewrite register operands to use the new vreg. for (SmallVectorImpl::iterator I = Indices.begin(), @@ -1720,7 +1635,7 @@ addIntervalsForSpillsFast(const LiveInterval &li, LiveRange LR(index.getLoadIndex(), index.getUseIndex(), nI.getNextValue(SlotIndex(), 0, false, getVNInfoAllocator())); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " +" << LR); nI.addRange(LR); vrm.addRestorePoint(NewVReg, MI); } @@ -1728,7 +1643,7 @@ addIntervalsForSpillsFast(const LiveInterval &li, LiveRange LR(index.getDefIndex(), index.getStoreIndex(), nI.getNextValue(SlotIndex(), 0, false, getVNInfoAllocator())); - DEBUG(errs() << " +" << LR); + DEBUG(dbgs() << " +" << LR); nI.addRange(LR); vrm.addSpillPoint(NewVReg, true, MI); } @@ -1736,9 +1651,9 @@ addIntervalsForSpillsFast(const LiveInterval &li, added.push_back(&nI); DEBUG({ - errs() << "\t\t\t\tadded new interval: "; + dbgs() << "\t\t\t\tadded new interval: "; nI.dump(); - errs() << '\n'; + dbgs() << '\n'; }); } @@ -1757,13 +1672,12 @@ addIntervalsForSpills(const LiveInterval &li, if (EnableFastSpilling) return addIntervalsForSpillsFast(li, loopInfo, vrm); - assert(li.weight != HUGE_VALF && - "attempt to spill already spilled interval!"); + assert(li.isSpillable() && "attempt to spill already spilled interval!"); DEBUG({ - errs() << "\t\t\t\tadding intervals for spills for interval: "; - li.print(errs(), tri_); - errs() << '\n'; + dbgs() << "\t\t\t\tadding intervals for spills for interval: "; + li.print(dbgs(), tri_); + dbgs() << '\n'; }); // Each bit specify whether a spill is required in the MBB. @@ -1832,6 +1746,7 @@ addIntervalsForSpills(const LiveInterval &li, } handleSpilledImpDefs(li, vrm, rc, NewLIs); + normalizeSpillWeights(NewLIs); return NewLIs; } @@ -1907,6 +1822,7 @@ addIntervalsForSpills(const LiveInterval &li, // Insert spills / restores if we are splitting. if (!TrySplit) { handleSpilledImpDefs(li, vrm, rc, NewLIs); + normalizeSpillWeights(NewLIs); return NewLIs; } @@ -2023,11 +1939,10 @@ addIntervalsForSpills(const LiveInterval &li, unsigned ImpUse = getReMatImplicitUse(li, ReMatDefMI); if (ImpUse) { // Re-matting an instruction with virtual register use. Add the - // register as an implicit use on the use MI and update the register - // interval's spill weight to HUGE_VALF to prevent it from being - // spilled. + // register as an implicit use on the use MI and mark the register + // interval as unspillable. LiveInterval &ImpLi = getInterval(ImpUse); - ImpLi.weight = HUGE_VALF; + ImpLi.markNotSpillable(); MI->addOperand(MachineOperand::CreateReg(ImpUse, false, true)); } } @@ -2066,6 +1981,7 @@ addIntervalsForSpills(const LiveInterval &li, } handleSpilledImpDefs(li, vrm, rc, RetNewLIs); + normalizeSpillWeights(RetNewLIs); return RetNewLIs; } @@ -2103,6 +2019,8 @@ unsigned LiveIntervals::getNumConflictsWithPhysReg(const LiveInterval &li, E = mri_->reg_end(); I != E; ++I) { MachineOperand &O = I.getOperand(); MachineInstr *MI = O.getParent(); + if (MI->isDebugValue()) + continue; SlotIndex Index = getInstructionIndex(MI); if (pli.liveAt(Index)) ++NumConflicts; @@ -2143,7 +2061,7 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, E = mri_->reg_end(); I != E; ++I) { MachineOperand &O = I.getOperand(); MachineInstr *MI = O.getParent(); - if (SeenMIs.count(MI)) + if (MI->isDebugValue() || SeenMIs.count(MI)) continue; SeenMIs.insert(MI); SlotIndex Index = getInstructionIndex(MI); @@ -2162,7 +2080,7 @@ bool LiveIntervals::spillPhysRegAroundRegDefsUses(const LiveInterval &li, std::string msg; raw_string_ostream Msg(msg); Msg << "Ran out of registers during register allocation!"; - if (MI->getOpcode() == TargetInstrInfo::INLINEASM) { + if (MI->isInlineAsm()) { Msg << "\nPlease check your inline asm statement for invalid " << "constraints:\n"; MI->print(Msg, tm_); @@ -2192,7 +2110,7 @@ LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg, VN->kills.push_back(indexes_->getTerminatorGap(startInst->getParent())); LiveRange LR( SlotIndex(getInstructionIndex(startInst).getDefIndex()), - getMBBEndIdx(startInst->getParent()).getNextIndex().getBaseIndex(), VN); + getMBBEndIdx(startInst->getParent()), VN); Interval.addRange(LR); return LR;