X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FLLVMTargetMachine.cpp;h=fb918f35ec1f4167a00c9e4afff468016df7955d;hb=cb3718832375a581c5ea23f15918f3ea447a446c;hp=641c04653a07a2f68b24cf99ad2f201cb5729836;hpb=31442f9dc5512b6a29cdb332b12ae09a1c9e8176;p=oota-llvm.git diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 641c04653a0..fb918f35ec1 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by Chris Lattner and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -17,16 +17,41 @@ #include "llvm/Assembly/PrintModulePass.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/GCStrategy.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetAsmInfo.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; -static cl::opt PrintLSR("print-lsr-output"); +static cl::opt PrintLSR("print-lsr-output", cl::Hidden, + cl::desc("Print LLVM IR produced by the loop-reduce pass")); +static cl::opt PrintISelInput("print-isel-input", cl::Hidden, + cl::desc("Print LLVM IR input to isel pass")); +static cl::opt PrintEmittedAsm("print-emitted-asm", cl::Hidden, + cl::desc("Dump emitter generated instructions as assembly")); +static cl::opt PrintGCInfo("print-gc", cl::Hidden, + cl::desc("Dump garbage collector data")); + +// Hidden options to help debugging +static cl::opt +EnableSinking("enable-sinking", cl::init(false), cl::Hidden, + cl::desc("Perform sinking on machine code")); +static cl::opt +EnableLICM("machine-licm", + cl::init(false), cl::Hidden, + cl::desc("Perform loop-invariant code motion on machine code")); + +// When this works it will be on by default. +static cl::opt +DisablePostRAScheduler("disable-post-RA-scheduler", + cl::desc("Disable scheduling after register allocation"), + cl::init(true)); FileModel::Model -LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, - std::ostream &Out, +LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, + raw_ostream &Out, CodeGenFileType FileType, bool Fast) { // Standard LLVM-Level Passes. @@ -35,19 +60,24 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, if (!Fast) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) - PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr)); + PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr)); } - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); - - // FIXME: Implement the invoke/unwind instructions! - if (!ExceptionHandling) + PM.add(createGCLoweringPass()); + + if (!getTargetAsmInfo()->doesSupportExceptionHandling()) PM.add(createLowerInvokePass(getTargetLowering())); - + // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); + if (!Fast) + PM.add(createCodeGenPreparePass(getTargetLowering())); + + if (PrintISelInput) + PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n", + &cerr)); + // Ask the target for an isel. if (addInstSelector(PM, Fast)) return FileModel::Error; @@ -55,24 +85,57 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + + if (EnableLICM) + PM.add(createMachineLICMPass()); + if (EnableSinking) + PM.add(createMachineSinkingPass()); + + // Run pre-ra passes. + if (addPreRegAlloc(PM, Fast) && PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + // Perform register allocation to convert to a concrete x86 representation PM.add(createRegisterAllocator()); - if (PrintMachineCode) - PM.add(createMachineFunctionPrinterPass(cerr)); + // Perform stack slot coloring. + if (!Fast) + PM.add(createStackSlotColoringPass()); + if (PrintMachineCode) // Print the register-allocated code + PM.add(createMachineFunctionPrinterPass(cerr)); + // Run post-ra passes. if (addPostRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + PM.add(createLowerSubregsPass()); + + if (PrintMachineCode) // Print the subreg lowered code + PM.add(createMachineFunctionPrinterPass(cerr)); + // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + // Second pass scheduler. + if (!Fast && !DisablePostRAScheduler) + PM.add(createPostRAScheduler()); + // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) - PM.add(createBranchFoldingPass()); - + PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); + + PM.add(createGCMachineCodeAnalysisPass()); + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + if (PrintGCInfo) + PM.add(createGCInfoPrinter(*cerr)); + // Fold redundant debug labels. PM.add(createDebugLabelFoldingPass()); @@ -82,6 +145,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + if (!Fast && !OptimizeForSize) + PM.add(createLoopAlignerPass()); + switch (FileType) { default: break; @@ -102,11 +168,13 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, /// addPassesToEmitFileFinish - If the passes to emit the specified file had to /// be split up (e.g., to add an object writer pass), this method can be used to /// finish up adding passes to emit the file, if necessary. -bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM, +bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, bool Fast) { if (MCE) - addSimpleCodeEmitter(PM, Fast, *MCE); + addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE); + + PM.add(createGCInfoDeleter()); // Delete machine code for this function PM.add(createMachineCodeDeleter()); @@ -120,23 +188,33 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM, /// of functions. This method should returns true if machine code emission is /// not supported. /// -bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, +bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, bool Fast) { // Standard LLVM-Level Passes. // Run loop strength reduction before anything else. - if (!Fast) PM.add(createLoopStrengthReducePass(getTargetLowering())); + if (!Fast) { + PM.add(createLoopStrengthReducePass(getTargetLowering())); + if (PrintLSR) + PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr)); + } - // FIXME: Implement efficient support for garbage collection intrinsics. - PM.add(createLowerGCPass()); + PM.add(createGCLoweringPass()); - // FIXME: Implement the invoke/unwind instructions! - PM.add(createLowerInvokePass(getTargetLowering())); + if (!getTargetAsmInfo()->doesSupportExceptionHandling()) + PM.add(createLowerInvokePass(getTargetLowering())); // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); + if (!Fast) + PM.add(createCodeGenPreparePass(getTargetLowering())); + + if (PrintISelInput) + PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n", + &cerr)); + // Ask the target for an isel. if (addInstSelector(PM, Fast)) return true; @@ -144,31 +222,67 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + + if (EnableLICM) + PM.add(createMachineLICMPass()); - // Perform register allocation to convert to a concrete x86 representation + if (EnableSinking) + PM.add(createMachineSinkingPass()); + + // Run pre-ra passes. + if (addPreRegAlloc(PM, Fast) && PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + // Perform register allocation. PM.add(createRegisterAllocator()); - + + // Perform stack slot coloring. + if (!Fast) + PM.add(createStackSlotColoringPass()); + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - + // Run post-ra passes. if (addPostRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + if (PrintMachineCode) // Print the register-allocated code + PM.add(createMachineFunctionPrinterPass(cerr)); + + PM.add(createLowerSubregsPass()); + + if (PrintMachineCode) // Print the subreg lowered code + PM.add(createMachineFunctionPrinterPass(cerr)); + // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); - if (PrintMachineCode) // Print the register-allocated code + if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); + // Second pass scheduler. + if (!Fast) + PM.add(createPostRAScheduler()); + // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) - PM.add(createBranchFoldingPass()); + PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); + + PM.add(createGCMachineCodeAnalysisPass()); + + if (PrintMachineCode) + PM.add(createMachineFunctionPrinterPass(cerr)); + + if (PrintGCInfo) + PM.add(createGCInfoPrinter(*cerr)); if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - addCodeEmitter(PM, Fast, MCE); + addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE); + + PM.add(createGCInfoDeleter()); // Delete machine code for this function PM.add(createMachineCodeDeleter());