X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FInstrSched%2FSchedGraph.cpp;h=00b48d537d3eee8089fb54d58f2dd5fd1ee442b6;hb=551ccae044b0ff658fe629dd67edd5ffe75d10e8;hp=65f1511e9608af3d77bce9b89acfcc028274e62d;hpb=0dc5753f2b3e2f2f4be1439ba57a3f749bbe51cb;p=oota-llvm.git diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index 65f1511e960..00b48d537d3 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -15,13 +15,15 @@ #include "SchedGraph.h" #include "llvm/Function.h" -#include "llvm/iOther.h" -#include "llvm/CodeGen/MachineCodeForInstruction.h" +#include "llvm/Instructions.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegInfo.h" -#include "Support/STLExtras.h" +#include "../../Target/SparcV9/MachineCodeForInstruction.h" +#include "../../Target/SparcV9/SparcV9RegInfo.h" +#include "../../Target/SparcV9/SparcV9InstrInfo.h" +#include "llvm/ADT/STLExtras.h" +#include namespace llvm { @@ -53,12 +55,16 @@ struct ValueToDefVecMap: public hash_map { SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb, int indexInBB, const TargetMachine& Target) - : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) { - if (MI) { - MachineOpCode mopCode = MI->getOpCode(); - latency = Target.getInstrInfo().hasResultInterlock(mopCode) - ? Target.getInstrInfo().minLatency(mopCode) - : Target.getInstrInfo().maxLatency(mopCode); + : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) { + if (mbb) { + MachineBasicBlock::iterator I = MBB->begin(); + std::advance(I, indexInBB); + MI = I; + + MachineOpCode mopCode = MI->getOpcode(); + latency = Target.getInstrInfo()->hasResultInterlock(mopCode) + ? Target.getInstrInfo()->minLatency(mopCode) + : Target.getInstrInfo()->maxLatency(mopCode); } } @@ -102,7 +108,7 @@ SchedGraph::~SchedGraph() { void SchedGraph::dump() const { std::cerr << " Sched Graph for Basic Block: " << MBB.getBasicBlock()->getName() - << " (" << MBB.getBasicBlock() << ")" + << " (" << *MBB.getBasicBlock() << ")" << "\n\n Actual Root nodes: "; for (SchedGraphNodeCommon::const_iterator I = graphRoot->beginOutEdges(), E = graphRoot->endOutEdges(); @@ -134,14 +140,14 @@ void SchedGraph::addDummyEdges() { void SchedGraph::addCDEdges(const TerminatorInst* term, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term); // Find the first branch instr in the sequence of machine instrs for term // unsigned first = 0; - while (! mii.isBranch(termMvec[first]->getOpCode()) && - ! mii.isReturn(termMvec[first]->getOpCode())) + while (! mii.isBranch(termMvec[first]->getOpcode()) && + ! mii.isReturn(termMvec[first]->getOpcode())) ++first; assert(first < termMvec.size() && "No branch instructions for terminator? Ok, but weird!"); @@ -159,8 +165,8 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, assert(toNode && "No node for instr generated for branch/ret?"); for (unsigned j = i-1; j != 0; --j) - if (mii.isBranch(termMvec[j-1]->getOpCode()) || - mii.isReturn(termMvec[j-1]->getOpCode())) { + if (mii.isBranch(termMvec[j-1]->getOpcode()) || + mii.isReturn(termMvec[j-1]->getOpcode())) { SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]); assert(brNode && "No node for instr generated for branch/ret?"); (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep, @@ -182,11 +188,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, // Now add CD edges to the first branch instruction in the sequence from // all preceding instructions in the basic block. Use 0 latency again. // - for (unsigned i=0, N=MBB.size(); i < N; i++) { - if (MBB[i] == termMvec[first]) // reached the first branch + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ + if (&*I == termMvec[first]) // reached the first branch break; - SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]); + SchedGraphNode* fromNode = getGraphNodeForInstr(I); if (fromNode == NULL) continue; // dummy instruction, e.g., PHI @@ -198,11 +204,11 @@ void SchedGraph::addCDEdges(const TerminatorInst* term, // the terminator) that also have delay slots, add an outgoing edge // from the instruction to the instructions in the delay slots. // - unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode()); - assert(i+d < N && "Insufficient delay slots for instruction?"); - - for (unsigned j=1; j <= d; j++) { - SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]); + unsigned d = mii.getNumDelaySlots(I->getOpcode()); + + MachineBasicBlock::iterator J = I; ++J; + for (unsigned j=1; j <= d; j++, ++J) { + SchedGraphNode* toNode = this->getGraphNodeForInstr(J); assert(toNode && "No node for machine instr in delay slot?"); (void) new SchedGraphEdge(fromNode, toNode, SchedGraphEdge::CtrlDep, @@ -236,18 +242,18 @@ static const unsigned int SG_DepOrderArray[][3] = { // void SchedGraph::addMemEdges(const std::vector& memNodeVec, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, // so simply look at all pairs i]>. // for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) { - MachineOpCode fromOpCode = memNodeVec[im]->getOpCode(); + MachineOpCode fromOpCode = memNodeVec[im]->getOpcode(); int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF : (mii.isLoad(fromOpCode)? SG_LOAD_REF : SG_STORE_REF)); for (unsigned jm=im+1; jm < NM; jm++) { - MachineOpCode toOpCode = memNodeVec[jm]->getOpCode(); + MachineOpCode toOpCode = memNodeVec[jm]->getOpcode(); int toType = (mii.isCall(toOpCode)? SG_CALL_REF : (mii.isLoad(toOpCode)? SG_LOAD_REF : SG_STORE_REF)); @@ -268,13 +274,13 @@ void SchedGraph::addMemEdges(const std::vector& memNodeVec, // void SchedGraph::addCallDepEdges(const std::vector& callDepNodeVec, const TargetMachine& target) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Instructions in memNodeVec are in execution order within the basic block, // so simply look at all pairs i]>. // for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++) - if (mii.isCall(callDepNodeVec[ic]->getOpCode())) { + if (mii.isCall(callDepNodeVec[ic]->getOpcode())) { // Add SG_CALL_REF edges from all preds to this instruction. for (unsigned jc=0; jc < ic; jc++) (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic], @@ -292,7 +298,7 @@ void SchedGraph::addCallDepEdges(const std::vector& callDepNode // Find the call instruction nodes and put them in a vector. std::vector callNodeVec; for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) - if (mii.isCall(memNodeVec[im]->getOpCode())) + if (mii.isCall(memNodeVec[im]->getOpcode())) callNodeVec.push_back(memNodeVec[im]); // Now walk the entire basic block, looking for CC instructions *and* @@ -302,14 +308,14 @@ void SchedGraph::addCallDepEdges(const std::vector& callDepNode // int lastCallNodeIdx = -1; for (unsigned i=0, N=bbMvec.size(); i < N; i++) - if (mii.isCall(bbMvec[i]->getOpCode())) { + if (mii.isCall(bbMvec[i]->getOpcode())) { ++lastCallNodeIdx; for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx) if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i]) break; assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?"); } - else if (mii.isCCInstr(bbMvec[i]->getOpCode())) { + else if (mii.isCCInstr(bbMvec[i]->getOpcode())) { // Add incoming/outgoing edges from/to preceding/later calls SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]); int j=0; @@ -467,9 +473,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, std::vector& callDepNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); - MachineOpCode opCode = node->getOpCode(); + MachineOpCode opCode = node->getOpcode(); if (mii.isCall(opCode) || mii.isCCInstr(opCode)) callDepNodeVec.push_back(node); @@ -486,11 +492,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, // if this references a register other than the hardwired // "zero" register, record the reference. if (mop.hasAllocatedReg()) { - int regNum = mop.getAllocatedRegNum(); + unsigned regNum = mop.getReg(); // If this is not a dummy zero register, record the reference in order - if (regNum != target.getRegInfo().getZeroRegNum()) - regToRefVecMap[mop.getAllocatedRegNum()] + if (regNum != target.getRegInfo()->getZeroRegNum()) + regToRefVecMap[mop.getReg()] .push_back(std::make_pair(node, i)); // If this is a volatile register, add the instruction to callDepVec @@ -498,8 +504,8 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node) { unsigned rcid; - int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid); - if (target.getRegInfo().getMachineRegClass(rcid) + int regInClass = target.getRegInfo()->getClassRegNum(regNum, rcid); + if (target.getRegInfo()->getMachineRegClass(rcid) ->isRegVolatile(regInClass)) callDepNodeVec.push_back(node); } @@ -527,9 +533,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target, for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) { const MachineOperand& mop = MI.getImplicitOp(i); if (mop.hasAllocatedReg()) { - int regNum = mop.getAllocatedRegNum(); - if (regNum != target.getRegInfo().getZeroRegNum()) - regToRefVecMap[mop.getAllocatedRegNum()] + unsigned regNum = mop.getReg(); + if (regNum != target.getRegInfo()->getZeroRegNum()) + regToRefVecMap[mop.getReg()] .push_back(std::make_pair(node, i + MI.getNumOperands())); continue; // nothing more to do } @@ -549,14 +555,16 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target, std::vector& callDepNodeVec, RegToRefVecMap& regToRefVecMap, ValueToDefVecMap& valueToDefVecMap) { - const TargetInstrInfo& mii = target.getInstrInfo(); + const TargetInstrInfo& mii = *target.getInstrInfo(); // Build graph nodes for each VM instruction and gather def/use info. // Do both those together in a single pass over all machine instructions. - for (unsigned i=0; i < MBB.size(); i++) - if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) { + unsigned i = 0; + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; + ++I, ++i) + if (I->getOpcode() != V9::PHI) { SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target); - noteGraphNodeForInstr(MBB[i], node); + noteGraphNodeForInstr(I, node); // Remember all register references and value defs findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec, @@ -631,8 +639,8 @@ void SchedGraph::buildGraph(const TargetMachine& target) { this->addCallDepEdges(callDepNodeVec, target); // Then add incoming def-use (SSA) edges for each machine instruction. - for (unsigned i=0, N=MBB.size(); i < N; i++) - addEdgesForInstruction(*MBB[i], valueToDefVecMap, target); + for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) + addEdgesForInstruction(*I, valueToDefVecMap, target); // Then add edges for dependences on machine registers this->addMachineRegEdges(regToRefVecMap, target); @@ -687,7 +695,7 @@ void SchedGraphEdge::print(std::ostream &os) const { os<< "Control Dep"; break; case SchedGraphEdge::ValueDep: - os<< "Reg Value " << val; + os<< "Reg Value " << *val; break; case SchedGraphEdge::MemoryDep: os<< "Memory Dep";