X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FIfConversion.cpp;h=3ac78b258540db94132c38796aee8cb6dafefa65;hb=e2007c9e7e58f66ad9976e89d83b3ea315b5dc93;hp=938c9cf603910d5eeca27c1ae57abfa0adae3ed7;hpb=5ffc7bfc9a61b4c90d56c183fdcdc16836fa6600;p=oota-llvm.git

diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp
index 938c9cf6039..3ac78b25854 100644
--- a/lib/CodeGen/IfConversion.cpp
+++ b/lib/CodeGen/IfConversion.cpp
@@ -985,6 +985,19 @@ static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
     // take a mutable instruction instead of const.
     MachineInstr *OpMI = const_cast<MachineInstr*>(Op.getParent());
     MachineInstrBuilder MIB(*OpMI->getParent()->getParent(), OpMI);
+    if (Op.isRegMask()) {
+      // First handle regmasks.  They clobber any entries in the mask which
+      // means that we need a def for those registers.
+      MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
+
+      // We also need to add an implicit def of this register for the later
+      // use to read from.
+      // For the register allocator to have allocated a register clobbered
+      // by the call which is used later, it must be the case that
+      // the call doesn't return.
+      MIB.addReg(Reg.first, RegState::Implicit | RegState::Define);
+      continue;
+    }
     assert(Op.isReg() && "Register operand required");
     MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
   }