X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FCodeGen%2FDFAPacketizer.cpp;h=0a188c0935adba07a0b6eca2b737e0ed468c82a9;hb=355ec009e5a1d7c3defa4e0740f45a292b7bdcbf;hp=5b40ae13690939794acd8c9426c1ce6a1f00d90f;hpb=9f998de8918c1dd5a8b8ec564af00107859898e0;p=oota-llvm.git diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp index 5b40ae13690..0a188c0935a 100644 --- a/lib/CodeGen/DFAPacketizer.cpp +++ b/lib/CodeGen/DFAPacketizer.cpp @@ -106,31 +106,30 @@ namespace llvm { class DefaultVLIWScheduler : public ScheduleDAGInstrs { public: DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, - MachineDominatorTree &MDT, bool IsPostRA); + bool IsPostRA); // Schedule - Actual scheduling work. void schedule() override; }; } -DefaultVLIWScheduler::DefaultVLIWScheduler( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - bool IsPostRA) : - ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) { +DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF, + MachineLoopInfo &MLI, bool IsPostRA) + : ScheduleDAGInstrs(MF, &MLI, IsPostRA) { CanHandleTerminators = true; } void DefaultVLIWScheduler::schedule() { // Build the scheduling graph. - buildSchedGraph(0); + buildSchedGraph(nullptr); } // VLIWPacketizerList Ctor -VLIWPacketizerList::VLIWPacketizerList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - bool IsPostRA) : TM(MF.getTarget()), MF(MF) { - TII = TM.getInstrInfo(); - ResourceTracker = TII->CreateTargetScheduleState(&TM, 0); - VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA); +VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF, + MachineLoopInfo &MLI, bool IsPostRA) + : MF(MF) { + TII = MF.getSubtarget().getInstrInfo(); + ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget()); + VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA); } // VLIWPacketizerList Dtor