X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetInstrInfo.h;h=76cfb392aef367149097822df9742782beba4807;hb=6fbcc26f1460eaee4e0eb8b426fc1ff0c7af11be;hp=81920ccc1a43b5195a51838d09ae8f1722ce73de;hpb=c864fde15c68fe56d2af48ddeaddfd4e13006f4a;p=oota-llvm.git diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 81920ccc1a4..76cfb392aef 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -1,23 +1,29 @@ -//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// +//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// // // This file describes the target machine instructions to the code generator. // -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MACHINEINSTRINFO_H -#define LLVM_TARGET_MACHINEINSTRINFO_H +#ifndef LLVM_TARGET_TARGETINSTRINFO_H +#define LLVM_TARGET_TARGETINSTRINFO_H -#include "Support/NonCopyable.h" #include "Support/DataTypes.h" -#include #include +#include -class MachineInstrDescriptor; -class TmpInstruction; class MachineInstr; class TargetMachine; class Value; +class Type; class Instruction; +class Constant; class Function; class MachineCodeForInstruction; @@ -26,170 +32,186 @@ class MachineCodeForInstruction; //--------------------------------------------------------------------------- typedef int MachineOpCode; -typedef int OpCodeMask; -typedef int InstrSchedClass; +typedef unsigned InstrSchedClass; const MachineOpCode INVALID_MACHINE_OPCODE = -1; -// Global variable holding an array of descriptors for machine instructions. -// The actual object needs to be created separately for each target machine. -// This variable is initialized and reset by class MachineInstrInfo. -// -// FIXME: This should be a property of the target so that more than one target -// at a time can be active... -// -extern const MachineInstrDescriptor *TargetInstrDescriptors; - - //--------------------------------------------------------------------------- -// struct MachineInstrDescriptor: +// struct TargetInstrDescriptor: // Predefined information about each machine instruction. // Designed to initialized statically. -// -// class MachineInstructionInfo -// Interface to description of machine instructions -// -//--------------------------------------------------------------------------- +// + +const unsigned M_NOP_FLAG = 1 << 0; +const unsigned M_BRANCH_FLAG = 1 << 1; +const unsigned M_CALL_FLAG = 1 << 2; +const unsigned M_RET_FLAG = 1 << 3; +const unsigned M_ARITH_FLAG = 1 << 4; +const unsigned M_CC_FLAG = 1 << 6; +const unsigned M_LOGICAL_FLAG = 1 << 6; +const unsigned M_INT_FLAG = 1 << 7; +const unsigned M_FLOAT_FLAG = 1 << 8; +const unsigned M_CONDL_FLAG = 1 << 9; +const unsigned M_LOAD_FLAG = 1 << 10; +const unsigned M_PREFETCH_FLAG = 1 << 11; +const unsigned M_STORE_FLAG = 1 << 12; +const unsigned M_DUMMY_PHI_FLAG = 1 << 13; +const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction +// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub +const unsigned M_2_ADDR_FLAG = 1 << 15; +// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic +// block? Typically this is things like return and branch instructions. +// Various passes use this to insert code into the bottom of a basic block, but +// before control flow occurs. +const unsigned M_TERMINATOR_FLAG = 1 << 16; -const unsigned int M_NOP_FLAG = 1; -const unsigned int M_BRANCH_FLAG = 1 << 1; -const unsigned int M_CALL_FLAG = 1 << 2; -const unsigned int M_RET_FLAG = 1 << 3; -const unsigned int M_ARITH_FLAG = 1 << 4; -const unsigned int M_CC_FLAG = 1 << 6; -const unsigned int M_LOGICAL_FLAG = 1 << 6; -const unsigned int M_INT_FLAG = 1 << 7; -const unsigned int M_FLOAT_FLAG = 1 << 8; -const unsigned int M_CONDL_FLAG = 1 << 9; -const unsigned int M_LOAD_FLAG = 1 << 10; -const unsigned int M_PREFETCH_FLAG = 1 << 11; -const unsigned int M_STORE_FLAG = 1 << 12; -const unsigned int M_DUMMY_PHI_FLAG = 1 << 13; -const unsigned int M_PSEUDO_FLAG = 1 << 14; - - -struct MachineInstrDescriptor { - std::string opCodeString; // Assembly language mnemonic for the opcode. - int numOperands; // Number of args; -1 if variable #args - int resultPos; // Position of the result; -1 if no result - unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0. +struct TargetInstrDescriptor { + const char * Name; // Assembly language mnemonic for the opcode. + int numOperands; // Number of args; -1 if variable #args + int resultPos; // Position of the result; -1 if no result + unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. bool immedIsSignExtended; // Is IMMED field sign-extended? If so, - // smallest -ve value is -(maxImmedConst+1). - unsigned int numDelaySlots; // Number of delay slots after instruction - unsigned int latency; // Latency in machine cycles - InstrSchedClass schedClass; // enum identifying instr sched class - unsigned int iclass; // flags identifying machine instr class + // smallest -ve value is -(maxImmedConst+1). + unsigned numDelaySlots; // Number of delay slots after instruction + unsigned latency; // Latency in machine cycles + InstrSchedClass schedClass; // enum identifying instr sched class + unsigned Flags; // flags identifying machine instr class + unsigned TSFlags; // Target Specific Flag values + const unsigned *ImplicitUses; // Registers implicitly read by this instr + const unsigned *ImplicitDefs; // Registers implicitly defined by this instr }; -class MachineInstrInfo : public NonCopyableV { -public: - const TargetMachine& target; - -protected: - const MachineInstrDescriptor* desc; // raw array to allow static init'n - unsigned int descSize; // number of entries in the desc array - unsigned int numRealOpCodes; // number of non-dummy op codes +//--------------------------------------------------------------------------- +/// +/// TargetInstrInfo - Interface to description of machine instructions +/// +class TargetInstrInfo { + const TargetInstrDescriptor* desc; // raw array to allow static init'n + unsigned descSize; // number of entries in the desc array + unsigned numRealOpCodes; // number of non-dummy op codes + TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT + void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT public: - MachineInstrInfo(const TargetMachine& tgt, - const MachineInstrDescriptor *desc, unsigned descSize, - unsigned numRealOpCodes); - virtual ~MachineInstrInfo(); + TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize, + unsigned numRealOpCodes); + virtual ~TargetInstrInfo(); + + // Invariant: All instruction sets use opcode #0 as the PHI instruction + enum { PHI = 0 }; unsigned getNumRealOpCodes() const { return numRealOpCodes; } unsigned getNumTotalOpCodes() const { return descSize; } - const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { + /// get - Return the machine instruction descriptor that corresponds to the + /// specified instruction opcode. + /// + const TargetInstrDescriptor& get(MachineOpCode opCode) const { assert(opCode >= 0 && opCode < (int)descSize); return desc[opCode]; } + + const char *getName(MachineOpCode opCode) const { + return get(opCode).Name; + } int getNumOperands(MachineOpCode opCode) const { - return getDescriptor(opCode).numOperands; + return get(opCode).numOperands; } int getResultPos(MachineOpCode opCode) const { - return getDescriptor(opCode).resultPos; + return get(opCode).resultPos; } unsigned getNumDelaySlots(MachineOpCode opCode) const { - return getDescriptor(opCode).numDelaySlots; + return get(opCode).numDelaySlots; } InstrSchedClass getSchedClass(MachineOpCode opCode) const { - return getDescriptor(opCode).schedClass; + return get(opCode).schedClass; } - + + const unsigned *getImplicitUses(MachineOpCode opCode) const { + return get(opCode).ImplicitUses; + } + + const unsigned *getImplicitDefs(MachineOpCode opCode) const { + return get(opCode).ImplicitDefs; + } + // // Query instruction class flags according to the machine-independent // flags listed above. // - unsigned int getIClass(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass; - } bool isNop(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_NOP_FLAG; + return get(opCode).Flags & M_NOP_FLAG; } bool isBranch(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_BRANCH_FLAG; + return get(opCode).Flags & M_BRANCH_FLAG; } bool isCall(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_CALL_FLAG; + return get(opCode).Flags & M_CALL_FLAG; } bool isReturn(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_RET_FLAG; + return get(opCode).Flags & M_RET_FLAG; } bool isControlFlow(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_BRANCH_FLAG - || getDescriptor(opCode).iclass & M_CALL_FLAG - || getDescriptor(opCode).iclass & M_RET_FLAG; + return get(opCode).Flags & M_BRANCH_FLAG + || get(opCode).Flags & M_CALL_FLAG + || get(opCode).Flags & M_RET_FLAG; } bool isArith(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_RET_FLAG; + return get(opCode).Flags & M_ARITH_FLAG; } bool isCCInstr(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_CC_FLAG; + return get(opCode).Flags & M_CC_FLAG; } bool isLogical(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; + return get(opCode).Flags & M_LOGICAL_FLAG; } bool isIntInstr(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_INT_FLAG; + return get(opCode).Flags & M_INT_FLAG; } bool isFloatInstr(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_FLOAT_FLAG; + return get(opCode).Flags & M_FLOAT_FLAG; } - bool isConditional(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_CONDL_FLAG; + bool isConditional(MachineOpCode opCode) const { + return get(opCode).Flags & M_CONDL_FLAG; } bool isLoad(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_LOAD_FLAG; + return get(opCode).Flags & M_LOAD_FLAG; } bool isPrefetch(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; + return get(opCode).Flags & M_PREFETCH_FLAG; } bool isLoadOrPrefetch(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_LOAD_FLAG - || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; + return get(opCode).Flags & M_LOAD_FLAG + || get(opCode).Flags & M_PREFETCH_FLAG; } bool isStore(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_STORE_FLAG; + return get(opCode).Flags & M_STORE_FLAG; } bool isMemoryAccess(MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_LOAD_FLAG - || getDescriptor(opCode).iclass & M_PREFETCH_FLAG - || getDescriptor(opCode).iclass & M_STORE_FLAG; + return get(opCode).Flags & M_LOAD_FLAG + || get(opCode).Flags & M_PREFETCH_FLAG + || get(opCode).Flags & M_STORE_FLAG; } - bool isDummyPhiInstr(const MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; + bool isDummyPhiInstr(MachineOpCode opCode) const { + return get(opCode).Flags & M_DUMMY_PHI_FLAG; } - bool isPseudoInstr(const MachineOpCode opCode) const { - return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; + bool isPseudoInstr(MachineOpCode opCode) const { + return get(opCode).Flags & M_PSEUDO_FLAG; } - + bool isTwoAddrInstr(MachineOpCode opCode) const { + return get(opCode).Flags & M_2_ADDR_FLAG; + } + bool isTerminatorInstr(unsigned Opcode) const { + return get(Opcode).Flags & M_TERMINATOR_FLAG; + } + // Check if an instruction can be issued before its operands are ready, // or if a subsequent instruction that uses its result can be issued // before the results are ready. @@ -207,11 +229,11 @@ public: // Latencies for individual instructions and instruction pairs // virtual int minLatency(MachineOpCode opCode) const { - return getDescriptor(opCode).latency; + return get(opCode).latency; } virtual int maxLatency(MachineOpCode opCode) const { - return getDescriptor(opCode).latency; + return get(opCode).latency; } // @@ -235,28 +257,86 @@ public: // virtual uint64_t maxImmedConstant(MachineOpCode opCode, bool &isSignExtended) const { - isSignExtended = getDescriptor(opCode).immedIsSignExtended; - return getDescriptor(opCode).maxImmedConst; + isSignExtended = get(opCode).immedIsSignExtended; + return get(opCode).maxImmedConst; + } + + //------------------------------------------------------------------------- + // Queries about representation of LLVM quantities (e.g., constants) + //------------------------------------------------------------------------- + + /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded + /// from memory into a register, i.e., cannot be set bitwise in register and + /// cannot use immediate fields of instructions. Note that this only makes + /// sense for primitive types. + /// + virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; + + // Test if this constant may not fit in the immediate field of the + // machine instructions (probably) generated for this instruction. + // + virtual bool ConstantMayNotFitInImmedField(const Constant* CV, + const Instruction* I) const { + return true; // safe but very conservative } + + /// createNOPinstr - returns the target's implementation of NOP, which is + /// usually a pseudo-instruction, implemented by a degenerate version of + /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0 + /// + virtual MachineInstr* createNOPinstr() const = 0; + + /// isNOPinstr - not having a special NOP opcode, we need to know if a given + /// instruction is interpreted as an `official' NOP instr, i.e., there may be + /// more than one way to `do nothing' but only one canonical way to slack off. + /// + virtual bool isNOPinstr(const MachineInstr &MI) const = 0; + //------------------------------------------------------------------------- // Code generation support for creating individual machine instructions + // + // WARNING: These methods are Sparc specific + // //------------------------------------------------------------------------- - + + // Get certain common op codes for the current target. this and all the + // Create* methods below should be moved to a machine code generation class + // + virtual MachineOpCode getNOPOpCode() const { abort(); } + + // Get the value of an integral constant in the form that must + // be put into the machine register. The specified constant is interpreted + // as (i.e., converted if necessary to) the specified destination type. The + // result is always returned as an uint64_t, since the representation of + // int64_t and uint64_t are identical. The argument can be any known const. + // + // isValidConstant is set to true if a valid constant was found. + // + virtual uint64_t ConvertConstantToIntType(const TargetMachine &target, + const Value *V, + const Type *destType, + bool &isValidConstant) const { + abort(); + } + // Create an instruction sequence to put the constant `val' into // the virtual register `dest'. `val' may be a Constant or a // GlobalValue, viz., the constant address of a global variable or function. // The generated instructions are returned in `mvec'. // Any temp. registers (TmpInstruction) created are recorded in mcfi. - // Any stack space required is allocated via mcff. + // Symbolic constants or constants that must be accessed from memory + // are added to the constant pool via MachineFunction::get(F). // virtual void CreateCodeToLoadConst(const TargetMachine& target, Function* F, Value* val, Instruction* dest, std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; - + MachineCodeForInstruction& mcfi) const { + abort(); + } + // Create an instruction sequence to copy an integer value `val' // to a floating point value `dest' by copying to memory and back. // val must be an integral type. dest must be a Float or Double. @@ -264,12 +344,14 @@ public: // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // - virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, + Function* F, + Value* val, + Instruction* dest, + std::vector& mvec, + MachineCodeForInstruction& MI) const { + abort(); + } // Similarly, create an instruction sequence to copy an FP value // `val' to an integer value `dest' by copying to memory and back. @@ -277,12 +359,14 @@ public: // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // - virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, - Function* F, - Value* val, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, + Function* F, + Value* val, + Instruction* dest, + std::vector& mvec, + MachineCodeForInstruction& MI) const { + abort(); + } // Create instruction(s) to copy src to dest, for arbitrary types // The generated instructions are returned in `mvec'. @@ -290,23 +374,45 @@ public: // Any stack space required is allocated via mcff. // virtual void CreateCopyInstructionsByType(const TargetMachine& target, - Function* F, - Value* src, - Instruction* dest, - std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + Function* F, + Value* src, + Instruction* dest, + std::vector& mvec, + MachineCodeForInstruction& MI) const { + abort(); + } // Create instruction sequence to produce a sign-extended register value // from an arbitrary sized value (sized in bits, not bytes). + // The generated instructions are appended to `mvec'. + // Any temp. registers (TmpInstruction) created are recorded in mcfi. // Any stack space required is allocated via mcff. // virtual void CreateSignExtensionInstructions(const TargetMachine& target, Function* F, - Value* unsignedSrcVal, - unsigned int srcSizeInBits, - Value* dest, + Value* srcVal, + Value* destVal, + unsigned numLowBits, std::vector& mvec, - MachineCodeForInstruction& mcfi)const=0; + MachineCodeForInstruction& MI) const { + abort(); + } + + // Create instruction sequence to produce a zero-extended register value + // from an arbitrary sized value (sized in bits, not bytes). + // The generated instructions are appended to `mvec'. + // Any temp. registers (TmpInstruction) created are recorded in mcfi. + // Any stack space required is allocated via mcff. + // + virtual void CreateZeroExtensionInstructions(const TargetMachine& target, + Function* F, + Value* srcVal, + Value* destVal, + unsigned srcSizeInBits, + std::vector& mvec, + MachineCodeForInstruction& mcfi) const { + abort(); + } }; #endif