X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FTargetInstrInfo.h;h=2f2f4cd575e1f28188fa329f4b861685bfb538b5;hb=320c630c1b55e17fa00249d499f974cb1a4238f8;hp=7accaf5789f9b99e18e923936cddc644e8a5f51b;hpb=08d52071bae2f8cc2e9aa6a451118b83d043813b;p=oota-llvm.git

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 7accaf5789f..2f2f4cd575e 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -48,6 +48,7 @@ const unsigned M_BARRIER_FLAG          = 1 << 3;
 const unsigned M_DELAY_SLOT_FLAG       = 1 << 4;
 const unsigned M_LOAD_FLAG             = 1 << 5;
 const unsigned M_STORE_FLAG            = 1 << 6;
+const unsigned M_INDIRECT_FLAG         = 1 << 7;
 
 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
 // changed into a 3-address instruction if the first two operands cannot be
@@ -130,6 +131,7 @@ class TargetInstrDescriptor {
 public:
   MachineOpCode   Opcode;        // The opcode.
   unsigned short  numOperands;   // Num of args (may be more if variable_ops).
+  unsigned short  numDefs;       // Num of args that are definitions.
   const char *    Name;          // Assembly language mnemonic for the opcode.
   InstrSchedClass schedClass;    // enum  identifying instr sched class
   unsigned        Flags;         // flags identifying machine instr class
@@ -200,6 +202,10 @@ public:
     return get(Opcode).numOperands;
   }
 
+  int getNumDefs(MachineOpCode Opcode) const {
+    return get(Opcode).numDefs;
+  }
+
   InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
     return get(Opcode).schedClass;
   }
@@ -232,6 +238,10 @@ public:
     return get(Opcode).Flags & M_BRANCH_FLAG;
   }
   
+  bool isIndirectBranch(MachineOpCode Opcode) const {
+    return get(Opcode).Flags & M_INDIRECT_FLAG;
+  }
+  
   /// isBarrier - Returns true if the specified instruction stops control flow
   /// from executing the instruction immediately following it.  Examples include
   /// unconditional branches and return instructions.
@@ -278,24 +288,24 @@ public:
     return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
   }
 
-  /// isTriviallyReMaterializable - Return true if the instruction is trivially
+  /// hasNoSideEffects - Return true if the instruction is trivially
   /// rematerializable, meaning it has no side effects and requires no operands
   /// that aren't always available.
-  bool isTriviallyReMaterializable(MachineInstr *MI) const {
+  bool hasNoSideEffects(MachineInstr *MI) const {
     return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) &&
-           isReallyTriviallyReMaterializable(MI);
+           isTriviallyReMaterializable(MI);
   }
 
 protected:
-  /// isReallyTriviallyReMaterializable - For instructions with opcodes for
-  /// which the M_REMATERIALIZABLE flag is set, this function tests whether the
-  /// instruction itself is actually trivially rematerializable, considering
-  /// its operands.  This is used for targets that have instructions that are
-  /// only trivially rematerializable for specific uses.  This predicate must
-  /// return false if the instruction has any side effects other than
-  /// producing a value, or if it requres any address registers that are not
-  /// always available.
-  virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
+  /// isTriviallyReMaterializable - For instructions with opcodes for which the
+  /// M_REMATERIALIZABLE flag is set, this function tests whether the
+  /// instruction itself is actually trivially rematerializable, considering its
+  /// operands.  This is used for targets that have instructions that are only
+  /// trivially rematerializable for specific uses.  This predicate must return
+  /// false if the instruction has any side effects other than producing a
+  /// value, or if it requres any address registers that are not always
+  /// available.
+  virtual bool isTriviallyReMaterializable(MachineInstr *MI) const {
     return true;
   }