X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FTarget%2FMRegisterInfo.h;h=bc58080a5ece2dbac73f95af126953e7f819d68c;hb=ff110265753c19daf0468ee1facf357460497b7e;hp=0cac31bb36529747c96ba81b051e561bf89ff94e;hpb=c3580cace271b0f7d35a25eb285a1cc0d644c30c;p=oota-llvm.git diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h index 0cac31bb365..bc58080a5ec 100644 --- a/include/llvm/Target/MRegisterInfo.h +++ b/include/llvm/Target/MRegisterInfo.h @@ -23,22 +23,35 @@ namespace llvm { -class Type; +class BitVector; +class CalleeSavedInfo; class MachineFunction; class MachineInstr; class MachineLocation; class MachineMove; +class RegScavenger; class TargetRegisterClass; +class Type; /// TargetRegisterDesc - This record contains all of the information known about /// a particular register. The AliasSet field (if not null) contains a pointer /// to a Zero terminated array of registers that this register aliases. This is /// needed for architectures like X86 which have AL alias AX alias EAX. /// Registers that this does not apply to simply should set this to null. +/// The SubRegs field is a zero terminated array of registers that are +/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. +/// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate +/// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH, +/// AL which are immediate sub-registers of AX. The SuperRegs field is a zero +/// terminated array of registers that are super-registers of the specific +/// register, e.g. RAX, EAX, are super-registers of AX. /// struct TargetRegisterDesc { const char *Name; // Assembly language name for the register const unsigned *AliasSet; // Register Alias Set, described above + const unsigned *SubRegs; // Sub-register set, described above + const unsigned *ImmSubRegs; // Immediate sub-register set, described above + const unsigned *SuperRegs; // Super-register set, described above }; class TargetRegisterClass { @@ -47,31 +60,47 @@ public: typedef const unsigned* const_iterator; typedef const MVT::ValueType* vt_iterator; - typedef const TargetRegisterClass** sc_iterator; + typedef const TargetRegisterClass* const * sc_iterator; private: + unsigned ID; bool isSubClass; const vt_iterator VTs; const sc_iterator SubClasses; const sc_iterator SuperClasses; + const sc_iterator SubRegClasses; + const sc_iterator SuperRegClasses; const unsigned RegSize, Alignment; // Size & Alignment of register in bytes + const int CopyCost; const iterator RegsBegin, RegsEnd; public: - TargetRegisterClass(const MVT::ValueType *vts, - const TargetRegisterClass **subcs, - const TargetRegisterClass **supcs, - unsigned RS, unsigned Al, iterator RB, iterator RE) - : VTs(vts), SubClasses(subcs), SuperClasses(supcs), - RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {} + TargetRegisterClass(unsigned id, + const MVT::ValueType *vts, + const TargetRegisterClass * const *subcs, + const TargetRegisterClass * const *supcs, + const TargetRegisterClass * const *subregcs, + const TargetRegisterClass * const *superregcs, + unsigned RS, unsigned Al, int CC, + iterator RB, iterator RE) + : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), + SubRegClasses(subregcs), SuperRegClasses(superregcs), + RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} virtual ~TargetRegisterClass() {} // Allow subclasses - - // begin/end - Return all of the registers in this class. + + /// getID() - Return the register class ID number. + /// + unsigned getID() const { return ID; } + + /// begin/end - Return all of the registers in this class. + /// iterator begin() const { return RegsBegin; } iterator end() const { return RegsEnd; } - // getNumRegs - Return the number of registers in this class + /// getNumRegs - Return the number of registers in this class. + /// unsigned getNumRegs() const { return RegsEnd-RegsBegin; } - // getRegister - Return the specified register in the class + /// getRegister - Return the specified register in the class. + /// unsigned getRegister(unsigned i) const { assert(i < getNumRegs() && "Register number out of range!"); return RegsBegin[i]; @@ -106,9 +135,9 @@ public: return I; } - /// hasSubRegClass - return true if the specified TargetRegisterClass is a + /// hasSubClass - return true if the specified TargetRegisterClass is a /// sub-register class of this TargetRegisterClass. - bool hasSubRegClass(const TargetRegisterClass *cs) const { + bool hasSubClass(const TargetRegisterClass *cs) const { for (int i = 0; SubClasses[i] != NULL; ++i) if (SubClasses[i] == cs) return true; @@ -127,9 +156,9 @@ public: return I; } - /// hasSuperRegClass - return true if the specified TargetRegisterClass is a + /// hasSuperClass - return true if the specified TargetRegisterClass is a /// super-register class of this TargetRegisterClass. - bool hasSuperRegClass(const TargetRegisterClass *cs) const { + bool hasSuperClass(const TargetRegisterClass *cs) const { for (int i = 0; SuperClasses[i] != NULL; ++i) if (SuperClasses[i] == cs) return true; @@ -148,6 +177,60 @@ public: return I; } + /// hasSubRegClass - return true if the specified TargetRegisterClass is a + /// class of a sub-register class for this TargetRegisterClass. + bool hasSubRegClass(const TargetRegisterClass *cs) const { + for (int i = 0; SubRegClasses[i] != NULL; ++i) + if (SubRegClasses[i] == cs) + return true; + return false; + } + + /// hasClassForSubReg - return true if the specified TargetRegisterClass is a + /// class of a sub-register class for this TargetRegisterClass. + bool hasClassForSubReg(unsigned SubReg) const { + --SubReg; + for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) + if (i == SubReg) + return true; + return false; + } + + /// getClassForSubReg - return theTargetRegisterClass for the sub-register + /// at idx for this TargetRegisterClass. + sc_iterator getClassForSubReg(unsigned SubReg) const { + --SubReg; + for (unsigned i = 0; SubRegClasses[i] != NULL; ++i) + if (i == SubReg) + return &SubRegClasses[i]; + assert(0 && "Invalid subregister index for register class"); + return NULL; + } + + /// subregclasses_begin / subregclasses_end - Loop over all of + /// the subregister classes of this register class. + sc_iterator subregclasses_begin() const { + return SubRegClasses; + } + + sc_iterator subregclasses_end() const { + sc_iterator I = SubRegClasses; + while (*I != NULL) ++I; + return I; + } + + /// superregclasses_begin / superregclasses_end - Loop over all of + /// the superregister classes of this register class. + sc_iterator superregclasses_begin() const { + return SuperRegClasses; + } + + sc_iterator superregclasses_end() const { + sc_iterator I = SuperRegClasses; + while (*I != NULL) ++I; + return I; + } + /// allocation_order_begin/end - These methods define a range of registers /// which specify the registers in this class that are valid to register /// allocate, and the preferred order to allocate them in. For example, @@ -161,10 +244,10 @@ public: /// /// By default, these methods return all registers in the class. /// - virtual iterator allocation_order_begin(MachineFunction &MF) const { + virtual iterator allocation_order_begin(const MachineFunction &MF) const { return begin(); } - virtual iterator allocation_order_end(MachineFunction &MF) const { + virtual iterator allocation_order_end(const MachineFunction &MF) const { return end(); } @@ -177,6 +260,10 @@ public: /// getAlignment - Return the minimum required alignment for a register of /// this class. unsigned getAlignment() const { return Alignment; } + + /// getCopyCost - Return the cost of copying a value between two registers in + /// this class. + int getCopyCost() const { return CopyCost; } }; @@ -203,20 +290,14 @@ protected: public: enum { // Define some target independent constants - /// NoRegister - This 'hard' register is a 'noop' register for all backends. - /// This is used as the destination register for instructions that do not - /// produce a value. Some frontends may use this as an operand register to - /// mean special things, for example, the Sparc backend uses R0 to mean %g0 - /// which always PRODUCES the value 0. The X86 backend does not use this - /// value as an operand register, except for memory references. - /// + /// NoRegister - This physical register is not a real target register. It + /// is useful as a sentinal. NoRegister = 0, /// FirstVirtualRegister - This is the first register number that is /// considered to be a 'virtual' register, which is part of the SSA /// namespace. This must be the same for all targets, which means that each /// target is limited to 1024 registers. - /// FirstVirtualRegister = 1024 }; @@ -234,9 +315,16 @@ public: return Reg >= FirstVirtualRegister; } + /// getPhysicalRegisterRegClass - Returns the Register Class of a physical + /// register of the given type. + const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT, + unsigned Reg) const; + /// getAllocatableSet - Returns a bitset indexed by register number - /// indicating if a register is allocatable or not. - std::vector getAllocatableSet(MachineFunction &MF) const; + /// indicating if a register is allocatable or not. If a register class is + /// specified, returns the subset for the class. + BitVector getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC = NULL) const; const TargetRegisterDesc &operator[](unsigned RegNo) const { assert(RegNo < NumRegs && @@ -259,6 +347,41 @@ public: return get(RegNo).AliasSet; } + /// getSubRegisters - Return the set of registers that are sub-registers of + /// the specified register, or a null list of there are none. The list + /// returned is zero terminated. + /// + const unsigned *getSubRegisters(unsigned RegNo) const { + return get(RegNo).SubRegs; + } + + /// getImmediateSubRegisters - Return the set of registers that are immediate + /// sub-registers of the specified register, or a null list of there are none. + /// The list returned is zero terminated. + /// + const unsigned *getImmediateSubRegisters(unsigned RegNo) const { + return get(RegNo).ImmSubRegs; + } + + /// getSuperRegisters - Return the set of registers that are super-registers + /// of the specified register, or a null list of there are none. The list + /// returned is zero terminated. + /// + const unsigned *getSuperRegisters(unsigned RegNo) const { + return get(RegNo).SuperRegs; + } + + /// isSubRegOf - Predicate which returns true if RegA is a sub-register of + /// RegB. Returns false otherwise. + /// + bool isSubRegOf(unsigned RegA, unsigned RegB) const { + const TargetRegisterDesc &RD = (*this)[RegA]; + for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg) + if (*reg == RegB) + return true; + return false; + } + /// getName - Return the symbolic target specific name for the specified /// physical register. const char *getName(unsigned RegNo) const { @@ -279,14 +402,55 @@ public: return false; } - /// getCalleeSaveRegs - Return a null-terminated list of all of the - /// callee-save registers on this target. - virtual const unsigned* getCalleeSaveRegs() const = 0; + /// regsOverlap - Returns true if the two registers are equal or alias + /// each other. The registers may be virtual register. + bool regsOverlap(unsigned regA, unsigned regB) const { + if (regA == regB) + return true; + + if (isVirtualRegister(regA) || isVirtualRegister(regB)) + return false; + return areAliases(regA, regB); + } + + /// isSubRegister - Returns true if regB is a sub-register of regA. + /// + bool isSubRegister(unsigned regA, unsigned regB) const { + for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR) + if (*SR == regB) return true; + return false; + } - /// getCalleeSaveRegClasses - Return a null-terminated list of the preferred - /// register classes to spill each callee-saved register with. The order and + /// isSuperRegister - Returns true if regB is a super-register of regA. + /// + bool isSuperRegister(unsigned regA, unsigned regB) const { + for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR) + if (*SR == regB) return true; + return false; + } + + /// getCalleeSavedRegs - Return a null-terminated list of all of the + /// callee saved registers on this target. The register should be in the + /// order of desired callee-save stack frame offset. The first register is + /// closed to the incoming stack pointer if stack grows down, and vice versa. + virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) + const = 0; + + /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred + /// register classes to spill each callee saved register with. The order and /// length of this list match the getCalleeSaveRegs() list. - virtual const TargetRegisterClass* const *getCalleeSaveRegClasses() const = 0; + virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( + const MachineFunction *MF) const =0; + + /// getReservedRegs - Returns a bitset indexed by physical register number + /// indicating if a register is a special register that has particular uses and + /// should be considered unavailable at all times, e.g. SP, RA. This is used by + /// register scavenger to determine what registers are free. + virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; + + /// getSubReg - Returns the physical register number of sub-register "Index" + /// for physical register RegNo. + virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; //===--------------------------------------------------------------------===// // Register Class Information @@ -300,14 +464,40 @@ public: unsigned getNumRegClasses() const { return regclass_end()-regclass_begin(); } + + /// getRegClass - Returns the register class associated with the enumeration + /// value. See class TargetOperandInfo. + const TargetRegisterClass *getRegClass(unsigned i) const { + assert(i <= getNumRegClasses() && "Register Class ID out of range"); + return i ? RegClassBegin[i - 1] : NULL; + } //===--------------------------------------------------------------------===// // Interfaces used by the register allocator and stack frame // manipulation passes to move data around between registers, - // immediates and memory. The return value is the number of - // instructions added to (negative if removed from) the basic block. + // immediates and memory. FIXME: Move these to TargetInstrInfo.h. // + /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved + /// registers and returns true if it isn't possible / profitable to do so by + /// issuing a series of store instructions via storeRegToStackSlot(). Returns + /// false otherwise. + virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + return false; + } + + /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee + /// saved registers and returns true if it isn't possible / profitable to do + /// so by issuing a series of load instructions via loadRegToStackSlot(). + /// Returns false otherwise. + virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector &CSI) const { + return false; + } + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, int FrameIndex, @@ -321,7 +511,23 @@ public: virtual void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const = 0; + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const = 0; + + /// getCrossCopyRegClass - Returns a legal register class to copy a register + /// in the specified class to or from. Returns NULL if it is possible to copy + /// between a two registers of the specified class. + virtual const TargetRegisterClass * + getCrossCopyRegClass(const TargetRegisterClass *RC) const { + return NULL; + } + + /// reMaterialize - Re-issue the specified 'original' instruction at the + /// specific location targeting a new destination register. + virtual void reMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, + const MachineInstr *Orig) const = 0; /// foldMemoryOperand - Attempt to fold a load or store of the /// specified stack slot into the specified machine instruction for @@ -335,6 +541,41 @@ public: return 0; } + /// foldMemoryOperand - Same as the previous version except it allows folding + /// of any load and store from / to any address, not just from a specific + /// stack slot. + virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, + unsigned OpNum, + MachineInstr* LoadMI) const { + return 0; + } + + /// targetHandlesStackFrameRounding - Returns true if the target is responsible + /// for rounding up the stack frame (probably at emitPrologue time). + virtual bool targetHandlesStackFrameRounding() const { + return false; + } + + /// requiresRegisterScavenging - returns true if the target requires (and + /// can make use of) the register scavenger. + virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { + return false; + } + + /// hasFP - Return true if the specified function should have a dedicated frame + /// pointer register. For most targets this is true only if the function has + /// variable sized allocas or if frame pointer elimination is disabled. + virtual bool hasFP(const MachineFunction &MF) const = 0; + + // hasReservedCallFrame - Under normal circumstances, when a frame pointer is + // not required, we reserve argument space for call sites in the function + // immediately on entry to the current function. This eliminates the need for + // add/sub sp brackets around call sites. Returns true if the call frame is + // included as part of the stack frame. + virtual bool hasReservedCallFrame(MachineFunction &MF) const { + return !hasFP(MF); + } + /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the /// frame setup/destroy instructions if they exist (-1 otherwise). Some /// targets use pseudo instructions in order to abstract away the difference @@ -362,12 +603,18 @@ public: assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); } + /// processFunctionBeforeCalleeSavedScan - This method is called immediately + /// before PrologEpilogInserter scans the physical registers used to determine + /// what callee saved registers should be spilled. This method is optional. + virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS = NULL) const { + + } + /// processFunctionBeforeFrameFinalized - This method is called immediately /// before the specified functions frame layout (MF.getFrameInfo()) is /// finalized. Once the frame is finalized, MO_FrameIndex operands are - /// replaced with direct constants. This method is optional. The return value - /// is the number of instructions added to (negative if removed from) the - /// basic block + /// replaced with direct constants. This method is optional. /// virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { } @@ -377,10 +624,12 @@ public: /// referenced by the iterator contains an MO_FrameIndex operand which must be /// eliminated by this method. This method may modify or replace the /// specified instruction, as long as it keeps the iterator pointing the the - /// finished product. The return value is the number of instructions - /// added to (negative if removed from) the basic block. + /// finished product. SPAdj is the SP adjustment due to call frame setup + /// instruction. The return value is the number of instructions added to + /// (negative if removed from) the basic block. /// - virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI) const = 0; + virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, + int SPAdj, RegScavenger *RS=NULL) const = 0; /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. The return value is the number of instructions @@ -404,7 +653,7 @@ public: /// getRARegister - This method should return the register where the return /// address can be found. virtual unsigned getRARegister() const = 0; - + /// getLocation - This method should return the actual location of a frame /// variable given the frame index. The location is returned in ML. /// Subclasses should override this method for special handling of frame @@ -415,10 +664,10 @@ public: /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to all functions. Note that LabelID is ignored (assumed to be /// the beginning of the function.) - virtual void getInitialFrameState(std::vector &Moves) const; + virtual void getInitialFrameState(std::vector &Moves) const; }; -// This is useful when building DenseMaps keyed on virtual registers +// This is useful when building IndexedMaps keyed on virtual registers struct VirtReg2IndexFunctor : std::unary_function { unsigned operator()(unsigned Reg) const { return Reg - MRegisterInfo::FirstVirtualRegister;