X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=include%2Fllvm%2FMC%2FMCRegisterInfo.h;h=dc60be3b8ac2278f7cfbfce57e90150724560ce9;hb=b6632ba380cf624e60fe16b03d6e21b05dd07724;hp=7ed84f214d07a1696f608388a8456ab70a32cc69;hpb=8ca9a862038e8c4e9a2ca73b3b75e1be3425155f;p=oota-llvm.git diff --git a/include/llvm/MC/MCRegisterInfo.h b/include/llvm/MC/MCRegisterInfo.h index 7ed84f214d0..dc60be3b8ac 100644 --- a/include/llvm/MC/MCRegisterInfo.h +++ b/include/llvm/MC/MCRegisterInfo.h @@ -17,7 +17,7 @@ #define LLVM_MC_MCREGISTERINFO_H #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/DenseSet.h" +#include "llvm/Support/ErrorHandling.h" #include namespace llvm { @@ -25,30 +25,18 @@ namespace llvm { /// MCRegisterClass - Base class of TargetRegisterClass. class MCRegisterClass { public: - typedef const unsigned* iterator; - typedef const unsigned* const_iterator; -private: - unsigned ID; + typedef const uint16_t* iterator; + typedef const uint16_t* const_iterator; + + const unsigned ID; const char *Name; const unsigned RegSize, Alignment; // Size & Alignment of register in bytes const int CopyCost; const bool Allocatable; - const iterator RegsBegin, RegsEnd; - DenseSet RegSet; -public: - MCRegisterClass(unsigned id, const char *name, - unsigned RS, unsigned Al, int CC, bool Allocable, - iterator RB, iterator RE) - : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC), - Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE) {} - - /// initMCRegisterClass - Initialize initMCRegisterClass. *DO NOT USE*. - // FIXME: This could go away if RegSet would use a constant bit field. - void initMCRegisterClass() { - RegSet.resize(getNumRegs()); - for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) - RegSet.insert(*I); - } + const iterator RegsBegin; + const uint8_t *const RegSet; + const unsigned RegsSize; + const unsigned RegSetSize; /// getID() - Return the register class ID number. /// @@ -61,11 +49,11 @@ public: /// begin/end - Return all of the registers in this class. /// iterator begin() const { return RegsBegin; } - iterator end() const { return RegsEnd; } + iterator end() const { return RegsBegin + RegsSize; } /// getNumRegs - Return the number of registers in this class. /// - unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } + unsigned getNumRegs() const { return RegsSize; } /// getRegister - Return the specified register in the class. /// @@ -77,7 +65,11 @@ public: /// contains - Return true if the specified register is included in this /// register class. This does not include virtual registers. bool contains(unsigned Reg) const { - return RegSet.count(Reg); + unsigned InByte = Reg % 8; + unsigned Byte = Reg / 8; + if (Byte >= RegSetSize) + return false; + return (RegSet[Byte] & (1 << InByte)) != 0; } /// contains - Return true if both registers are in this class. @@ -114,10 +106,10 @@ public: /// of AX. /// struct MCRegisterDesc { - const char *Name; // Printable name for the reg (for debugging) - const unsigned *Overlaps; // Overlapping registers, described above - const unsigned *SubRegs; // Sub-register set, described above - const unsigned *SuperRegs; // Super-register set, described above + const char *Name; // Printable name for the reg (for debugging) + unsigned Overlaps; // Overlapping registers, described above + unsigned SubRegs; // Sub-register set, described above + unsigned SuperRegs; // Super-register set, described above }; /// MCRegisterInfo base class - We assume that the target defines a static @@ -141,6 +133,12 @@ private: unsigned RAReg; // Return address register const MCRegisterClass *Classes; // Pointer to the regclass array unsigned NumClasses; // Number of entries in the array + const unsigned *Overlaps; // Pointer to the overlaps array + const unsigned *SubRegs; // Pointer to the subregs array + const unsigned *SuperRegs; // Pointer to the superregs array + const uint16_t *SubRegIndices; // Pointer to the subreg lookup + // array. + unsigned NumSubRegIndices; // Number of subreg indices. DenseMap L2DwarfRegs; // LLVM to Dwarf regs mapping DenseMap EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH DenseMap Dwarf2LRegs; // Dwarf to LLVM regs mapping @@ -151,15 +149,21 @@ public: /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen /// auto-generated routines. *DO NOT USE*. void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, - MCRegisterClass *C, unsigned NC) { + const MCRegisterClass *C, unsigned NC, + const unsigned *O, const unsigned *Sub, + const unsigned *Super, + const uint16_t *SubIndices, + unsigned NumIndices) { Desc = D; NumRegs = NR; RAReg = RA; Classes = C; + Overlaps = O; + SubRegs = Sub; + SuperRegs = Super; NumClasses = NC; - // FIXME: This should go away. - for (unsigned i = 0; i != NC; ++i) - C[i].initMCRegisterClass(); + SubRegIndices = SubIndices; + NumSubRegIndices = NumIndices; } /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf @@ -171,7 +175,7 @@ public: else L2DwarfRegs[LLVMReg] = DwarfReg; } - + /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM /// register number mapping. Called by TableGen auto-generated routines. /// *DO NOT USE*. @@ -181,7 +185,7 @@ public: else Dwarf2LRegs[DwarfReg] = LLVMReg; } - + /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register /// number mapping. By default the SEH register number is just the same /// as the LLVM register number. @@ -216,7 +220,7 @@ public: /// const unsigned *getAliasSet(unsigned RegNo) const { // The Overlaps set always begins with Reg itself. - return get(RegNo).Overlaps + 1; + return Overlaps + get(RegNo).Overlaps + 1; } /// getOverlaps - Return a list of registers that overlap Reg, including @@ -225,7 +229,7 @@ public: /// These are exactly the registers in { x | regsOverlap(x, Reg) }. /// const unsigned *getOverlaps(unsigned RegNo) const { - return get(RegNo).Overlaps; + return Overlaps + get(RegNo).Overlaps; } /// getSubRegisters - Return the list of registers that are sub-registers of @@ -234,7 +238,24 @@ public: /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. /// const unsigned *getSubRegisters(unsigned RegNo) const { - return get(RegNo).SubRegs; + return SubRegs + get(RegNo).SubRegs; + } + + /// getSubReg - Returns the physical register number of sub-register "Index" + /// for physical register RegNo. Return zero if the sub-register does not + /// exist. + unsigned getSubReg(unsigned Reg, unsigned Idx) const { + return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); + } + + /// getSubRegIndex - For a given register pair, return the sub-register index + /// if the second register is a sub-register of the first. Return zero + /// otherwise. + unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const { + for (unsigned I = 1; I <= NumSubRegIndices; ++I) + if (getSubReg(RegNo, I) == SubRegNo) + return I; + return 0; } /// getSuperRegisters - Return the list of registers that are super-registers @@ -243,7 +264,7 @@ public: /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. /// const unsigned *getSuperRegisters(unsigned RegNo) const { - return get(RegNo).SuperRegs; + return SuperRegs + get(RegNo).SuperRegs; } /// getName - Return the human-readable symbolic target-specific name for the @@ -275,8 +296,7 @@ public: const DenseMap &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs; const DenseMap::const_iterator I = M.find(RegNum); if (I == M.end()) { - assert(0 && "Invalid RegNum"); - return -1; + llvm_unreachable("Invalid RegNum"); } return I->second; } @@ -303,7 +323,7 @@ public: return Classes[i]; } }; - + } // End llvm namespace #endif