X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=folly%2FCpuId.h;h=bbd36c219a40099210a8daacbc166ad9354335b8;hb=c32f067bded198c6e907ee31ed76d83baa856a8e;hp=24d4d97ee979d52f8048a80c991eb53c47245059;hpb=ed8c80a0e0988e4ce687f51ca832a00e4a6b7930;p=folly.git

diff --git a/folly/CpuId.h b/folly/CpuId.h
index 24d4d97e..bbd36c21 100644
--- a/folly/CpuId.h
+++ b/folly/CpuId.h
@@ -33,7 +33,7 @@ namespace folly {
 class CpuId {
  public:
   // Always inline in order for this to be usable from a __ifunc__.
-  // In shared library mde, a __ifunc__ runs at relocation time, while the
+  // In shared library mode, a __ifunc__ runs at relocation time, while the
   // PLT hasn't been fully populated yet; thus, ifuncs cannot use symbols
   // with potentially external linkage. (This issue is less likely in opt
   // mode since inlining happens more likely, and it doesn't happen for
@@ -56,7 +56,7 @@ class CpuId {
 #elif defined(__i386__) && defined(__PIC__) && !defined(__clang__) && \
     defined(__GNUC__)
     // The following block like the normal cpuid branch below, but gcc
-    // reserves ebx for use of it's pic register so we must specially
+    // reserves ebx for use of its pic register so we must specially
     // handle the save and restore to avoid clobbering the register
     uint32_t n;
     __asm__(
@@ -65,13 +65,14 @@ class CpuId {
         "popl %%ebx\n\t"
         : "=a"(n)
         : "a"(0)
-        : "edx", "ecx");
+        : "ecx", "edx");
     if (n >= 1) {
+      uint32_t f1a;
       __asm__(
           "pushl %%ebx\n\t"
           "cpuid\n\t"
           "popl %%ebx\n\t"
-          : "=c"(f1c_), "=d"(f1d_)
+          : "=a"(f1a), "=c"(f1c_), "=d"(f1d_)
           : "a"(1)
           :);
     }
@@ -87,19 +88,24 @@ class CpuId {
     }
 #elif FOLLY_X64 || defined(__i386__)
     uint32_t n;
-    __asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "edx", "ecx");
+    __asm__("cpuid" : "=a"(n) : "a"(0) : "ebx", "ecx", "edx");
     if (n >= 1) {
-      __asm__("cpuid" : "=c"(f1c_), "=d"(f1d_) : "a"(1) : "ebx");
+      uint32_t f1a;
+      __asm__("cpuid" : "=a"(f1a), "=c"(f1c_), "=d"(f1d_) : "a"(1) : "ebx");
     }
     if (n >= 7) {
-      __asm__("cpuid" : "=b"(f7b_), "=c"(f7c_) : "a"(7), "c"(0) : "edx");
+      uint32_t f7a;
+      __asm__("cpuid"
+              : "=a"(f7a), "=b"(f7b_), "=c"(f7c_)
+              : "a"(7), "c"(0)
+              : "edx");
     }
 #endif
   }
 
 #define X(name, r, bit)                   \
   FOLLY_ALWAYS_INLINE bool name() const { \
-    return (r) & (1U << bit);             \
+    return ((r) & (1U << bit)) != 0;      \
   }
 
 // cpuid(1): Processor Info and Feature Bits.