X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=drivers%2Fusb%2Fdwc3%2Fcore.h;h=a3a196bd7d2c07acdf1978a0dda401aa1a49212c;hb=d72b2a3f3cb467a6645bd35e4ee2849068263593;hp=6ddf8e9462a2be5a5e2ddb4709eddb36fd7371f0;hpb=26ecf99bd66fe915083fb69c7c20b9b9b67d38f0;p=firefly-linux-kernel-4.4.55.git diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 6ddf8e9462a2..a3a196bd7d2c 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -30,10 +30,6 @@ #include #include #include -#include -#include -#include -#include #include #include @@ -183,15 +179,9 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) -#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) -#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) -#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) -#define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 -#define USBTRDTIM_UTMI_8_BIT 9 -#define USBTRDTIM_UTMI_16_BIT 5 /* Global USB2 PHY Vendor Control Register */ #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) @@ -204,6 +194,7 @@ /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) +#define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28) #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24) #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19) #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7) @@ -223,10 +214,6 @@ #define DWC3_GEVNTSIZ_INTMASK (1 << 31) #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff) -/* Global HWPARAMS0 Register */ -#define DWC3_GHWPARAMS0_USB3_MODE(n) ((n) & 7) -#define DWC3_GHWPARAMS0_USB3_DRD 2 - /* Global HWPARAMS1 Register */ #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24) #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0 @@ -450,18 +437,18 @@ struct dwc3_event_buffer { #define DWC3_EP_DIRECTION_TX true #define DWC3_EP_DIRECTION_RX false -#define DWC3_TRB_NUM 32 +#define DWC3_TRB_NUM 256 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1) /** * struct dwc3_ep - device side endpoint representation * @endpoint: usb endpoint - * @request_list: list of requests for this endpoint - * @req_queued: list of requests on this ep which have TRBs setup + * @pending_list: list of pending requests for this endpoint + * @started_list: list of started requests on this endpoint * @trb_pool: array of transaction buffers * @trb_pool_dma: dma address of @trb_pool - * @free_slot: next slot which is going to be used - * @busy_slot: first slot which is owned by HW + * @trb_enqueue: enqueue 'pointer' into TRB array + * @trb_dequeue: dequeue 'pointer' into TRB array * @desc: usb_endpoint_descriptor pointer * @dwc: pointer to DWC controller * @saved_state: ep state saved during hibernation @@ -476,13 +463,13 @@ struct dwc3_event_buffer { */ struct dwc3_ep { struct usb_ep endpoint; - struct list_head request_list; - struct list_head req_queued; + struct list_head pending_list; + struct list_head started_list; struct dwc3_trb *trb_pool; dma_addr_t trb_pool_dma; - u32 free_slot; - u32 busy_slot; + u32 trb_enqueue; + u32 trb_dequeue; const struct usb_ss_ep_comp_descriptor *comp_desc; struct dwc3 *dwc; @@ -635,11 +622,24 @@ struct dwc3_hwparams { /* HWPARAMS7 */ #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff) +/** + * struct dwc3_request - representation of a transfer request + * @request: struct usb_request to be transferred + * @list: a list_head used for request queueing + * @dep: struct dwc3_ep owning this request + * @first_trb_index: index to first trb used by this request + * @epnum: endpoint number to which this request refers + * @trb: pointer to struct dwc3_trb + * @trb_dma: DMA address of @trb + * @direction: IN or OUT direction flag + * @mapped: true when request has been dma-mapped + * @queued: true when request has been queued to HW + */ struct dwc3_request { struct usb_request request; struct list_head list; struct dwc3_ep *dep; - u32 start_slot; + u32 first_trb_index; u8 epnum; struct dwc3_trb *trb; @@ -647,7 +647,7 @@ struct dwc3_request { unsigned direction:1; unsigned mapped:1; - unsigned queued:1; + unsigned started:1; }; /* @@ -679,7 +679,6 @@ struct dwc3_scratchpad_array { * @regs: base address for our registers * @regs_size: address space size * @nr_scratch: number of scratch buffers - * @num_event_buffers: calculated number of event buffers * @u1u2: only used on revisions <1.83a for workaround * @maximum_speed: maximum speed requested (mainly for testing purposes) * @revision: revision register contents @@ -706,7 +705,6 @@ struct dwc3_scratchpad_array { * @hwparams: copy of hwparams registers * @root: debugfs root folder pointer * @regset: debugfs pointer to regdump file - * @cable: extcon cable for otg device/host mode notifier * @test_mode: true when we're entering a USB test mode * @test_mode_nr: test feature selector * @lpm_nyet_threshold: LPM NYET response threshold @@ -722,14 +720,11 @@ struct dwc3_scratchpad_array { * 0 - utmi_sleep_n * 1 - utmi_l1_suspend_n * @is_fpga: true when we are using the FPGA board - * @enabled: true when gadget driver is ready * @pullups_connected: true when Run/Stop bit is set * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround * @start_config_issued: true when StartConfig command has been issued * @three_stage_setup: set if we perform a three phase setup * @usb3_lpm_capable: set if hadrware supports Link Power Management - * @phyif_utmi_16_bits: set if configure the core to support UTMI+ PHY - * with an 16-bit interface * @disable_scramble_quirk: set if we enable the disable scramble quirk * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk @@ -742,14 +737,6 @@ struct dwc3_scratchpad_array { * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG, * disabling the suspend signal to the PHY. - * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists - * in GUSB2PHYCFG, specify that USB2 PHY doesn't - * provide a free-running PHY clock. - * @dis_del_phy_power_chg_quirk: set if we disable delay phy power - * change quirk. - * @xhci_slow_suspend_quirk: set if need an extraordinary delay to wait - * for xHC enter the Halted state after the Run/Stop - * (R/S) bit is cleared to '0'. * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk * @tx_de_emphasis: Tx de-emphasis value * 0 - -6dB de-emphasis @@ -778,7 +765,7 @@ struct dwc3 { struct platform_device *xhci; struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM]; - struct dwc3_event_buffer **ev_buffs; + struct dwc3_event_buffer *ev_buf; struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; struct usb_gadget gadget; @@ -802,7 +789,6 @@ struct dwc3 { u32 gctl; u32 nr_scratch; - u32 num_event_buffers; u32 u1u2; u32 maximum_speed; @@ -863,14 +849,6 @@ struct dwc3 { struct dentry *root; struct debugfs_regset32 *regset; - struct { - struct extcon_dev *edev; - bool connected; - struct notifier_block device_nb; - struct notifier_block host_nb; - struct delayed_work otg_work; - } cable; - u8 test_mode; u8 test_mode_nr; u8 lpm_nyet_threshold; @@ -885,12 +863,10 @@ struct dwc3 { unsigned has_lpm_erratum:1; unsigned is_utmi_l1_suspend:1; unsigned is_fpga:1; - unsigned enabled:1; unsigned pullups_connected:1; unsigned setup_packet_pending:1; unsigned three_stage_setup:1; unsigned usb3_lpm_capable:1; - unsigned phyif_utmi_16_bits:1; unsigned disable_scramble_quirk:1; unsigned u2exit_lfps_quirk:1; @@ -903,9 +879,7 @@ struct dwc3 { unsigned dis_u3_susphy_quirk:1; unsigned dis_u2_susphy_quirk:1; unsigned dis_enblslpm_quirk:1; - unsigned dis_u2_freeclk_exists_quirk:1; - unsigned dis_del_phy_power_chg_quirk:1; - unsigned xhci_slow_suspend_quirk:1; + unsigned dis_rxdet_inp3_quirk:1; unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; @@ -1058,10 +1032,12 @@ struct dwc3_gadget_ep_cmd_params { /* prototypes */ void dwc3_set_mode(struct dwc3 *dwc, u32 mode); -int dwc3_soft_reset(struct dwc3 *dwc); -int dwc3_event_buffers_setup(struct dwc3 *dwc); -void dwc3_event_buffers_cleanup(struct dwc3 *dwc); -bool dwc3_force_mode(struct dwc3 *dwc, u32 mode); + +/* check whether we are on the DWC_usb31 core */ +static inline bool dwc3_is_usb31(struct dwc3 *dwc) +{ + return !!(dwc->revision & DWC3_REVISION_IS_DWC31); +} #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_host_init(struct dwc3 *dwc); @@ -1082,7 +1058,6 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state); int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, unsigned cmd, struct dwc3_gadget_ep_cmd_params *params); int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param); -int dwc3_gadget_restart(struct dwc3 *dwc, bool start); #else static inline int dwc3_gadget_init(struct dwc3 *dwc) { return 0; } @@ -1102,8 +1077,6 @@ static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) { return 0; } -static inline int dwc3_gadget_restart(struct dwc3 *dwc, bool start) -{ return 0; } #endif /* power management interface */