The LLVM type system is one of the most important features of the
intermediate representation. Being typed enables a number of
-optimizations to be performed on the IR directly, without having to do
+optimizations to be performed on the intermediate representation directly,
+without having to do
extra analyses on the side before the transformation. A strong type
system makes it easier to read the generated code and enables novel
analyses and transformations that are not feasible to perform on normal
@@ -1055,7 +1178,6 @@ classifications:
- | < { float, i32 (i32)* } > |
+
+< { float, i32 (i32)* } > |
A pair, where the first element is a float and the
second element is a pointer to a
function that takes an i32, returning
@@ -1679,7 +1803,8 @@ following is the syntax for constant expressions:
was stored to memory and read back as TYPE. In other words, no bits change
with this operator, just the type. This can be used for conversion of
vector types to any other type, as long as they have the same bit width. For
- pointers it is only valid to cast to another pointer type.
+ pointers it is only valid to cast to another pointer type. It is not valid
+ to bitcast to or from an aggregate type.
getelementptr ( CSTPTR, IDX0, IDX1, ... )
@@ -1709,7 +1834,7 @@ following is the syntax for constant expressions:
extractelement ( VAL, IDX )
Perform the extractelement
- operation on constants.
+ operation on constants.
insertelement ( VAL, ELT, IDX )
@@ -1783,7 +1908,8 @@ call void asm sideeffect "eieio", ""()
TODO: The format of the asm and constraints string still need to be
documented here. Constraints on what can be done (e.g. duplication, moving, etc
-need to be documented).
+need to be documented). This is probably best done by reference to another
+document that covers inline asm from a holistic perspective.
@@ -1829,27 +1955,30 @@ the 'invoke' instruction, the '
Syntax:
- ret <type> <value> ; Return a value from a non-void function
+
+ ret <type> <value> ; Return a value from a non-void function
ret void ; Return from void function
- ret <type> <value>, <type> <value> ; Return two values from a non-void function
Overview:
-The 'ret' instruction is used to return control flow (and a
-value) from a function back to the caller.
+The 'ret' instruction is used to return control flow (and
+optionally a value) from a function back to the caller.
There are two forms of the 'ret' instruction: one that
-returns value(s) and then causes control flow, and one that just causes
+returns a value and then causes control flow, and one that just causes
control flow to occur.
Arguments:
-The 'ret' instruction may return zero, one or multiple values.
-The type of each return value must be a 'first
-class' type. Note that a function is not well
-formed if there exists a 'ret' instruction inside of the
-function that returns values that do not match the return type of the
-function.
+The 'ret' instruction optionally accepts a single argument,
+the return value. The type of the return value must be a
+'first class' type.
+
+A function is not well formed if
+it it has a non-void return type and contains a 'ret'
+instruction with no return value or a return value with a type that
+does not match its type, or if it has a void return type and contains
+a 'ret' instruction with a return value.
Semantics:
@@ -1860,16 +1989,14 @@ the instruction after the call. If the caller was an "invoke" instruction, execution continues
at the beginning of the "normal" destination block. If the instruction
returns a value, that value shall set the call or invoke instruction's
-return value. If the instruction returns multiple values then these
-values can only be accessed through a 'getresult
-' instruction.
+return value.
Example:
ret i32 5 ; Return an integer value of 5
ret void ; Return from a void function
- ret i32 4, i8 2 ; Return two values 4 and 2
+ ret { i32, i8 } { i32 4, i8 2 } ; Return an aggregate of values 4 and 2
@@ -1966,7 +2093,7 @@ branches or with a lookup table.
Syntax:
- <result> = invoke [cconv] <ptr to function ty> <function ptr val>(<function args>)
+ <result> = invoke [cconv] [ret attrs] <ptr to function ty> <function ptr val>(<function args>) [fn attrs]
to label <normal label> unwind label <exception label>
@@ -1979,9 +2106,7 @@ function, with the possibility of control flow transfer to either the
"ret" instruction, control flow will return to the
"normal" label. If the callee (or any indirect callees) returns with the "unwind" instruction, control is interrupted and
-continued at the dynamically nearest "exception" label. If the callee function
-returns multiple values then individual return values are only accessible through
-a 'getresult' instruction.
+continued at the dynamically nearest "exception" label.
Arguments:
@@ -1993,6 +2118,11 @@ a 'getresult' instruction.
convention the call should use. If none is specified, the call defaults
to using C calling conventions.
+
+ The optional Parameter Attributes list for
+ return values. Only 'zeroext', 'signext',
+ and 'inreg' attributes are valid here.
+
'ptr to function ty': shall be the signature of the pointer to
function value being invoked. In most cases, this is a direct function
invocation, but indirect invokes are just as possible, branching off
@@ -2013,6 +2143,9 @@ a 'getresult' instruction.
'exception label': the label reached when a callee returns with
the unwind instruction.
+ The optional function attributes list. Only
+ 'noreturn', 'nounwind', 'readonly' and
+ 'readnone' attributes are valid here.
Semantics:
@@ -2112,7 +2245,7 @@ The result value has the same type as its operands.
Syntax:
- <result> = add <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = add <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2154,7 +2287,7 @@ instruction is appropriate for both signed and unsigned integers.
Syntax:
- <result> = sub <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = sub <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2200,7 +2333,7 @@ instruction is appropriate for both signed and unsigned integers.
Syntax:
- <result> = mul <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = mul <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'mul' instruction returns the product of its two
@@ -2237,7 +2370,7 @@ width of the full product.
Syntax:
- <result> = udiv <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = udiv <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'udiv' instruction returns the quotient of its two
@@ -2265,7 +2398,7 @@ operations; for signed integer division, use 'sdiv'.
Syntax:
- <result> = sdiv <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = sdiv <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2296,7 +2429,7 @@ Instruction
Syntax:
- <result> = fdiv <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = fdiv <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2325,7 +2458,7 @@ of floating point values. Both arguments must have identical types.
Syntax:
- <result> = urem <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = urem <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'urem' instruction returns the remainder from the
@@ -2355,7 +2488,7 @@ distinct operations; for signed integer remainder, use 'srem'.
Syntax:
- <result> = srem <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = srem <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2374,8 +2507,8 @@ values. Both arguments must have identical types.
Semantics:
This instruction returns the remainder of a division (where the result
-has the same sign as the dividend, var1), not the modulo
-operator (where the result has the same sign as the divisor, var2) of
+has the same sign as the dividend, op1), not the modulo
+operator (where the result has the same sign as the divisor, op2) of
a value. For more information about the difference, see The
Math Forum. For a table of how this is implemented in various languages,
@@ -2401,7 +2534,7 @@ and the remainder.)
Syntax:
- <result> = frem <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = frem <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'frem' instruction returns the remainder from the
@@ -2439,7 +2572,7 @@ and produce a single value. The resulting value is the same type as its operand
Instruction
Syntax:
- <result> = shl <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = shl <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2450,21 +2583,23 @@ the left a specified number of bits.
Arguments:
Both arguments to the 'shl' instruction must be the same integer type. 'var2' is treated as an
-unsigned value. This instruction does not support
-vector operands.
+ href="#t_integer">integer or vector of integer
+type. 'op2' is treated as an unsigned value.
Semantics:
-The value produced is var1 * 2var2 mod 2n,
-where n is the width of the result. If var2 is (statically or dynamically) negative or
-equal to or larger than the number of bits in var1, the result is undefined.
+The value produced is op1 * 2op2 mod 2n,
+where n is the width of the result. If op2 is (statically or dynamically) negative or
+equal to or larger than the number of bits in op1, the result is undefined.
+If the arguments are vectors, each vector element of op1 is shifted by the
+corresponding shift amount in op2.
Example:
<result> = shl i32 4, %var ; yields {i32}: 4 << %var
<result> = shl i32 4, 2 ; yields {i32}: 16
<result> = shl i32 1, 10 ; yields {i32}: 1024
<result> = shl i32 1, 32 ; undefined
+ <result> = shl <2 x i32> < i32 1, i32 1>, < i32 1, i32 2> ; yields: result=<2 x i32> < i32 2, i32 4>
@@ -2472,7 +2607,7 @@ equal to or larger than the number of bits in var1, the result is undef
Instruction
Syntax:
- <result> = lshr <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = lshr <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2481,16 +2616,17 @@ operand shifted to the right a specified number of bits with zero fill.
Arguments:
Both arguments to the 'lshr' instruction must be the same
-integer type. 'var2' is treated as an
-unsigned value. This instruction does not support
-vector operands.
+integer or vector of integer
+type. 'op2' is treated as an unsigned value.
Semantics:
This instruction always performs a logical shift right operation. The most
significant bits of the result will be filled with zero bits after the
-shift. If var2 is (statically or dynamically) equal to or larger than
-the number of bits in var1, the result is undefined.
+shift. If op2 is (statically or dynamically) equal to or larger than
+the number of bits in op1, the result is undefined. If the arguments are
+vectors, each vector element of op1 is shifted by the corresponding shift
+amount in op2.
Example:
@@ -2499,6 +2635,7 @@ the number of bits in var1, the result is undefined.
<result> = lshr i8 4, 3 ; yields {i8}:result = 0
<result> = lshr i8 -2, 1 ; yields {i8}:result = 0x7FFFFFFF
<result> = lshr i32 1, 32 ; undefined
+ <result> = lshr <2 x i32> < i32 -2, i32 4>, < i32 1, i32 2> ; yields: result=<2 x i32> < i32 0x7FFFFFFF, i32 1>
@@ -2508,7 +2645,7 @@ Instruction
Syntax:
- <result> = ashr <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = ashr <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2517,16 +2654,16 @@ operand shifted to the right a specified number of bits with sign extension.
Arguments:
Both arguments to the 'ashr' instruction must be the same
-integer type. 'var2' is treated as an
-unsigned value. This instruction does not support
-vector operands.
+integer or vector of integer
+type. 'op2' is treated as an unsigned value.
Semantics:
This instruction always performs an arithmetic shift right operation,
The most significant bits of the result will be filled with the sign bit
-of var1. If var2 is (statically or dynamically) equal to or
-larger than the number of bits in var1, the result is undefined.
-
+of op1. If op2 is (statically or dynamically) equal to or
+larger than the number of bits in op1, the result is undefined. If the
+arguments are vectors, each vector element of op1 is shifted by the
+corresponding shift amount in op2.
Example:
@@ -2535,6 +2672,7 @@ larger than the number of bits in var1, the result is undefined.
<result> = ashr i8 4, 3 ; yields {i8}:result = 0
<result> = ashr i8 -2, 1 ; yields {i8}:result = -1
<result> = ashr i32 1, 32 ; undefined
+ <result> = ashr <2 x i32> < i32 -2, i32 4>, < i32 1, i32 3> ; yields: result=<2 x i32> < i32 -1, i32 0>
@@ -2547,7 +2685,7 @@ Instruction
Syntax:
- <result> = and <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = and <ty> <op1>, <op2> ; yields {ty}:result
Overview:
@@ -2564,7 +2702,7 @@ values. Both arguments must have identical types.
Semantics:
The truth table used for the 'and' instruction is:
-
+
@@ -2606,7 +2744,7 @@ values. Both arguments must have identical types.
Syntax:
- <result> = or <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = or <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'or' instruction returns the bitwise logical inclusive
@@ -2619,7 +2757,7 @@ values. Both arguments must have identical types.
Semantics:
The truth table used for the 'or' instruction is:
-
+
@@ -2661,7 +2799,7 @@ values. Both arguments must have identical types.
Instruction
Syntax:
- <result> = xor <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = xor <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'xor' instruction returns the bitwise logical exclusive
@@ -2676,7 +2814,7 @@ values. Both arguments must have identical types.
The truth table used for the 'xor' instruction is:
-
+
@@ -2834,23 +2972,25 @@ exceeds the length of val, the results are undefined.
Syntax:
- <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <n x i32> <mask> ; yields <n x <ty>>
+ <result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <m x i32> <mask> ; yields <m x <ty>>
Overview:
The 'shufflevector' instruction constructs a permutation of elements
-from two input vectors, returning a vector of the same type.
+from two input vectors, returning a vector with the same element type as
+the input and length that is the same as the shuffle mask.
Arguments:
-The first two operands of a 'shufflevector' instruction are vectors
-with types that match each other and types that match the result of the
-instruction. The third argument is a shuffle mask, which has the same number
-of elements as the other vector type, but whose element type is always 'i32'.
+The first two operands of a 'shufflevector' instruction are vectors
+with types that match each other. The third argument is a shuffle mask whose
+element type is always 'i32'. The result of the instruction is a vector whose
+length is the same as the shuffle mask and whose element type is the same as
+the element type of the first two operands.
@@ -2863,7 +3003,7 @@ constant integer or undef values.
The elements of the two input vectors are numbered from left to right across
both of the vectors. The shuffle mask operand specifies, for each element of
-the result vector, which element of the two input registers the result element
+the result vector, which element of the two input vectors the result element
gets. The element selector may be undef (meaning "don't care") and the second
operand may be undef if performing a shuffle from only one vector.
@@ -2875,6 +3015,10 @@ operand may be undef if performing a shuffle from only one vector.
<4 x i32> <i32 0, i32 4, i32 1, i32 5> ; yields <4 x i32>
%result = shufflevector <4 x i32> %v1, <4 x i32> undef,
<4 x i32> <i32 0, i32 1, i32 2, i32 3> ; yields <4 x i32> - Identity shuffle.
+ %result = shufflevector <8 x i32> %v1, <8 x i32> undef,
+ <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; yields <4 x i32>
+ %result = shufflevector <4 x i32> %v1, <4 x i32> %v2,
+ <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 > ; yields <8 x i32>
@@ -2970,6 +3114,7 @@ indices in a
'getelementptr' instruction.
The value to insert must have the same type as the value identified
by the indices.
+
Semantics:
@@ -2982,7 +3127,7 @@ specified by the indices is that of elt.
Example:
- %result = insertvalue {i32, float} %agg, 1, 0 ; yields {i32, float}
+ %result = insertvalue {i32, float} %agg, i32 1, 0 ; yields {i32, float}
@@ -3036,7 +3181,7 @@ choose to align the allocation on any convenient boundary.
Semantics:
Memory is allocated using the system "malloc" function, and
-a pointer is returned. The result of a zero byte allocattion is undefined. The
+a pointer is returned. The result of a zero byte allocation is undefined. The
result is null if there is insufficient memory available.
Example:
@@ -3225,25 +3370,34 @@ at the location specified by the '<pointer>' operand.
Syntax:
- <result> = getelementptr <ty>* <ptrval>{, <ty> <idx>}*
+ <result> = getelementptr <pty>* <ptrval>{, <ty> <idx>}*
Overview:
The 'getelementptr' instruction is used to get the address of a
-subelement of an aggregate data structure.
+subelement of an aggregate data structure. It performs address calculation only
+and does not access memory.
Arguments:
- This instruction takes a list of integer operands that indicate what
-elements of the aggregate object to index to. The actual types of the arguments
-provided depend on the type of the first pointer argument. The
-'getelementptr' instruction is used to index down through the type
-levels of a structure or to a specific index in an array. When indexing into a
-structure, only i32 integer constants are allowed. When indexing
-into an array or pointer, only integers of 32 or 64 bits are allowed; 32-bit
-values will be sign extended to 64-bits if required.
+ The first argument is always a pointer, and forms the basis of the
+calculation. The remaining arguments are indices, that indicate which of the
+elements of the aggregate object are indexed. The interpretation of each index
+is dependent on the type being indexed into. The first index always indexes the
+pointer value given as the first argument, the second index indexes a value of
+the type pointed to (not necessarily the value directly pointed to, since the
+first index can be non-zero), etc. The first type indexed into must be a pointer
+value, subsequent types can be arrays, vectors and structs. Note that subsequent
+types being indexed into can never be pointers, since that would require loading
+the pointer before continuing calculation.
+
+ The type of each index argument depends on the type it is indexing into.
+When indexing into a (packed) structure, only i32 integer
+constants are allowed. When indexing into an array, pointer or vector,
+only integers of 32 or 64 bits are allowed (also non-constants). 32-bit values
+will be sign extended to 64-bits if required.
For example, let's consider a C code fragment and how it gets
compiled to LLVM:
@@ -3284,13 +3438,6 @@ entry:
Semantics:
- The index types specified for the 'getelementptr' instruction depend
-on the pointer type that is being indexed into. Pointer
-and array types can use a 32-bit or 64-bit
-integer type but the value will always be sign extended
-to 64-bits. Structure and packed
-structure types require i32 constants.
-
In the example above, the first index is indexing into the '%ST*'
type, which is a pointer, yielding a '%ST' = '{ i32, double, %RT
}' type, a structure. The second index indexes into the third element of
@@ -3330,7 +3477,11 @@ FAQ.
; yields [12 x i8]*:aptr
- %aptr = getelementptr {i32, [12 x i8]}* %sptr, i64 0, i32 1
+ %aptr = getelementptr {i32, [12 x i8]}* %saptr, i64 0, i32 1
+ ; yields i8*:vptr
+ %vptr = getelementptr {i32, <2 x i8>}* %svptr, i64 0, i32 1, i32 1
+ ; yields i8*:eptr
+ %eptr = getelementptr [12 x i8]* %aptr, i64 0, i32 1
@@ -3632,7 +3783,7 @@ the value cannot fit in the floating point value, the results are undefined.
Example:
%X = uitofp i32 257 to float ; yields float:257.0
- %Y = uitofp i8 -1 to double ; yields double:255.0
+ %Y = uitofp i8 -1 to double ; yields double:255.0
@@ -3666,7 +3817,7 @@ the value cannot fit in the floating point value, the results are undefined.
Example:
%X = sitofp i32 257 to float ; yields float:257.0
- %Y = sitofp i8 -1 to double ; yields double:-1.0
+ %Y = sitofp i8 -1 to double ; yields double:-1.0
@@ -3688,7 +3839,7 @@ the integer type ty2.
Arguments:
The 'ptrtoint' instruction takes a value to cast, which
must be a pointer value, and a type to cast it to
-ty2, which must be an integer type.
+ty2, which must be an integer type.
Semantics:
The 'ptrtoint' instruction converts value to integer type
@@ -3724,7 +3875,7 @@ a pointer type, ty2.
Arguments:
The 'inttoptr' instruction takes an integer
value to cast, and a type to cast it to, which must be a
-pointer type.
+pointer type.
Semantics:
The 'inttoptr' instruction converts value to type
@@ -3761,8 +3912,9 @@ nothing is done (no-op cast).
Arguments:
The 'bitcast' instruction takes a value to cast, which must be
-a first class value, and a type to cast it to, which must also be a first class type. The bit sizes of value
+a non-aggregate first class value, and a type to cast it to, which must also be
+a non-aggregate first class type. The bit sizes of
+value
and the destination type, ty2, must be identical. If the source
type is a pointer, the destination type must also be a pointer. This
instruction supports bitwise conversion of vectors to integers and to vectors
@@ -3781,7 +3933,7 @@ other types, use the inttoptr or
%X = bitcast i8 255 to i8 ; yields i8 :-1
%Y = bitcast i32* %x to sint* ; yields sint*:%x
- %Z = bitcast <2xint> %V to i64; ; yields i64: %V
+ %Z = bitcast <2 x int> %V to i64; ; yields i64: %V
@@ -3797,15 +3949,17 @@ instructions, which defy better classification.
Syntax:
- <result> = icmp <cond> <ty> <var1>, <var2> ; yields {i1}:result
+ <result> = icmp <cond> <ty> <op1>, <op2> ; yields {i1} or {<N x i1>}:result
Overview:
-The 'icmp' instruction returns a boolean value based on comparison
-of its two integer or pointer operands.
+The 'icmp' instruction returns a boolean value or
+a vector of boolean values based on comparison
+of its two integer, integer vector, or pointer operands.
Arguments:
The 'icmp' instruction takes three operands. The first operand is
the condition code indicating the kind of comparison to perform. It is not
a value, just a keyword. The possible condition code are:
+
- eq: equal
- ne: not equal
@@ -3819,36 +3973,44 @@ a value, just a keyword. The possible condition code are:
- sle: signed less or equal
The remaining two arguments must be integer or
-pointer typed. They must also be identical types.
+pointer
+or integer vector typed.
+They must also be identical types.
Semantics:
-The 'icmp' compares var1 and var2 according to
+ The 'icmp' compares op1 and op2 according to
the condition code given as cond. The comparison performed always
-yields a i1 result, as follows:
+yields either an i1 or vector of i1 result, as follows:
+
- eq: yields true if the operands are equal,
false otherwise. No sign interpretation is necessary or performed.
- ne: yields true if the operands are unequal,
- false otherwise. No sign interpretation is necessary or performed.
+ false otherwise. No sign interpretation is necessary or performed.
- ugt: interprets the operands as unsigned values and yields
- true if var1 is greater than var2.
+ true if op1 is greater than op2.
- uge: interprets the operands as unsigned values and yields
- true if var1 is greater than or equal to var2.
+ true if op1 is greater than or equal to op2.
- ult: interprets the operands as unsigned values and yields
- true if var1 is less than var2.
+ true if op1 is less than op2.
- ule: interprets the operands as unsigned values and yields
- true if var1 is less than or equal to var2.
+ true if op1 is less than or equal to op2.
- sgt: interprets the operands as signed values and yields
- true if var1 is greater than var2.
+ true if op1 is greater than op2.
- sge: interprets the operands as signed values and yields
- true if var1 is greater than or equal to var2.
+ true if op1 is greater than or equal to op2.
- slt: interprets the operands as signed values and yields
- true if var1 is less than var2.
+ true if op1 is less than op2.
- sle: interprets the operands as signed values and yields
- true if var1 is less than or equal to var2.
+ true if op1 is less than or equal to op2.
If the operands are pointer typed, the pointer
values are compared as if they were integers.
+If the operands are integer vectors, then they are compared
+element by element. The result is an i1 vector with
+the same number of elements as the values being compared.
+Otherwise, the result is an i1.
+
Example:
<result> = icmp eq i32 4, 5 ; yields: result=false
@@ -3865,15 +4027,23 @@ values are compared as if they were integers.
Syntax:
- <result> = fcmp <cond> <ty> <var1>, <var2> ; yields {i1}:result
+ <result> = fcmp <cond> <ty> <op1>, <op2> ; yields {i1} or {<N x i1>}:result
Overview:
-The 'fcmp' instruction returns a boolean value based on comparison
-of its floating point operands.
+The 'fcmp' instruction returns a boolean value
+or vector of boolean values based on comparison
+of its operands.
+
+If the operands are floating point scalars, then the result
+type is a boolean (i1).
+
+If the operands are floating point vectors, then the result type
+is a vector of boolean with the same number of elements as the
+operands being compared.
Arguments:
The 'fcmp' instruction takes three operands. The first operand is
the condition code indicating the kind of comparison to perform. It is not
-a value, just a keyword. The possible condition code are:
+a value, just a keyword. The possible condition code are:
- false: no comparison, always returns false
- oeq: ordered and equal
@@ -3894,49 +4064,53 @@ a value, just a keyword. The possible condition code are:
Ordered means that neither operand is a QNAN while
unordered means that either operand may be a QNAN.
-The val1 and val2 arguments must be
-floating point typed. They must have identical
-types.
+Each of val1 and val2 arguments must be
+either a floating point type
+or a vector of floating point type.
+They must have identical types.
Semantics:
-The 'fcmp' instruction compares var1 and var2
-according to the condition code given as cond. The comparison performed
-always yields a i1 result, as follows:
+ The 'fcmp' instruction compares op1 and op2
+according to the condition code given as cond.
+If the operands are vectors, then the vectors are compared
+element by element.
+Each comparison performed
+always yields an i1 result, as follows:
- false: always yields false, regardless of operands.
- oeq: yields true if both operands are not a QNAN and
- var1 is equal to var2.
+ op1 is equal to op2.
- ogt: yields true if both operands are not a QNAN and
- var1 is greather than var2.
+ op1 is greather than op2.
- oge: yields true if both operands are not a QNAN and
- var1 is greater than or equal to var2.
+ op1 is greater than or equal to op2.
- olt: yields true if both operands are not a QNAN and
- var1 is less than var2.
+ op1 is less than op2.
- ole: yields true if both operands are not a QNAN and
- var1 is less than or equal to var2.
+ op1 is less than or equal to op2.
- one: yields true if both operands are not a QNAN and
- var1 is not equal to var2.
+ op1 is not equal to op2.
- ord: yields true if both operands are not a QNAN.
- ueq: yields true if either operand is a QNAN or
- var1 is equal to var2.
+ op1 is equal to op2.
- ugt: yields true if either operand is a QNAN or
- var1 is greater than var2.
+ op1 is greater than op2.
- uge: yields true if either operand is a QNAN or
- var1 is greater than or equal to var2.
+ op1 is greater than or equal to op2.
- ult: yields true if either operand is a QNAN or
- var1 is less than var2.
+ op1 is less than op2.
- ule: yields true if either operand is a QNAN or
- var1 is less than or equal to var2.
+ op1 is less than or equal to op2.
- une: yields true if either operand is a QNAN or
- var1 is not equal to var2.
+ op1 is not equal to op2.
- uno: yields true if either operand is a QNAN.
- true: always yields true, regardless of operands.
Example:
<result> = fcmp oeq float 4.0, 5.0 ; yields: result=false
- <result> = icmp one float 4.0, 5.0 ; yields: result=true
- <result> = icmp olt float 4.0, 5.0 ; yields: result=true
- <result> = icmp ueq double 1.0, 2.0 ; yields: result=false
+ <result> = fcmp one float 4.0, 5.0 ; yields: result=true
+ <result> = fcmp olt float 4.0, 5.0 ; yields: result=true
+ <result> = fcmp ueq double 1.0, 2.0 ; yields: result=false
@@ -3946,7 +4120,7 @@ always yields a i1 result, as follows:
Syntax:
- <result> = vicmp <cond> <ty> <var1>, <var2> ; yields {ty}:result
+ <result> = vicmp <cond> <ty> <op1>, <op2> ; yields {ty}:result
Overview:
The 'vicmp' instruction returns an integer vector value based on
@@ -3954,7 +4128,7 @@ element-wise comparison of its two integer vector operands.
Arguments:
The 'vicmp' instruction takes three operands. The first operand is
the condition code indicating the kind of comparison to perform. It is not
-a value, just a keyword. The possible condition code are:
+a value, just a keyword. The possible condition code are:
- eq: equal
- ne: not equal
@@ -3967,17 +4141,17 @@ a value, just a keyword. The possible condition code are:
- slt: signed less than
- sle: signed less or equal
-The remaining two arguments must be vector of
+ The remaining two arguments must be vector or
integer typed. They must also be identical types.
Semantics:
-The 'vicmp' instruction compares var1 and var2
+ The 'vicmp' instruction compares op1 and op2
according to the condition code given as cond. The comparison yields a
vector of integer result, of
identical type as the values being compared. The most significant bit in each
element is 1 if the element-wise comparison evaluates to true, and is 0
otherwise. All other bits of the result are undefined. The condition codes
are evaluated identically to the 'icmp'
-instruction.
+instruction.
Example:
@@ -3992,7 +4166,7 @@ instruction.
Syntax:
- <result> = vfcmp <cond> <ty> <var1>, <var2>
+ <result> = vfcmp <cond> <ty> <op1>, <op2>
Overview:
The 'vfcmp' instruction returns an integer vector value based on
element-wise comparison of its two floating point vector operands. The output
@@ -4000,7 +4174,7 @@ elements have the same width as the input elements.
Arguments:
The 'vfcmp' instruction takes three operands. The first operand is
the condition code indicating the kind of comparison to perform. It is not
-a value, just a keyword. The possible condition code are:
+a value, just a keyword. The possible condition code are:
- false: no comparison, always returns false
- oeq: ordered and equal
@@ -4023,7 +4197,7 @@ a value, just a keyword. The possible condition code are:
floating point typed. They must also be identical
types.
Semantics:
-The 'vfcmp' instruction compares var1 and var2
+ The 'vfcmp' instruction compares op1 and op2
according to the condition code given as cond. The comparison yields a
vector of integer result, with
an identical number of elements as the values being compared, and each element
@@ -4031,12 +4205,15 @@ having identical with to the width of the floating point elements. The most
significant bit in each element is 1 if the element-wise comparison evaluates to
true, and is 0 otherwise. All other bits of the result are undefined. The
condition codes are evaluated identically to the
-'fcmp' instruction.
+'fcmp' instruction.
Example:
- <result> = vfcmp oeq <2 x float> < float 4, float 0 >, < float 5, float 0 > ; yields: result=<2 x i32> < i32 0, i32 -1 >
- <result> = vfcmp ult <2 x double> < double 1, double 2 >, < double 2, double 2> ; yields: result=<2 x i64> < i64 -1, i64 0 >
+ ; yields: result=<2 x i32> < i32 0, i32 -1 >
+ <result> = vfcmp oeq <2 x float> < float 4, float 0 >, < float 5, float 0 >
+
+ ; yields: result=<2 x i64> < i64 -1, i64 0 >
+ <result> = vfcmp ult <2 x double> < double 1, double 2 >, < double 2, double 2>
@@ -4091,7 +4268,9 @@ Loop: ; Infinite loop that counts from 0 on up...
Syntax:
- <result> = select i1 <cond>, <ty> <val1>, <ty> <val2> ; yields ty
+ <result> = select selty <cond>, <ty> <val1>, <ty> <val2> ; yields ty
+
+ selty is either i1 or {<N x i1>}
Overview:
@@ -4105,18 +4284,25 @@ condition, without branching.
Arguments:
-The 'select' instruction requires an 'i1' value indicating the
+The 'select' instruction requires an 'i1' value or
+a vector of 'i1' values indicating the
condition, and two values of the same first class
-type. If the val1/val2 are vectors, the entire vectors are selected, not
+type. If the val1/val2 are vectors and
+the condition is a scalar, then entire vectors are selected, not
individual elements.
Semantics:
-If the i1 condition evaluates is 1, the instruction returns the first
+If the condition is an i1 and it evaluates to 1, the instruction returns the first
value argument; otherwise, it returns the second value argument.
+
+If the condition is a vector of i1, then the value arguments must
+be vectors of the same size, and the selection is done element
+by element.
+
Example:
@@ -4135,7 +4321,7 @@ value argument; otherwise, it returns the second value argument.
Syntax:
- <result> = [tail] call [cconv] <ty> [<fnty>*] <fnptrval>(<param list>)
+ <result> = [tail] call [cconv] [ret attrs] <ty> [<fnty>*] <fnptrval>(<function args>) [fn attrs]
Overview:
@@ -4152,13 +4338,20 @@ value argument; otherwise, it returns the second value argument.
any allocas or varargs in the caller. If the "tail" marker is present, the
function call is eligible for tail call optimization. Note that calls may
be marked "tail" even if they do not occur before a ret instruction.
+ href="#i_ret">ret instruction.
The optional "cconv" marker indicates which calling
convention the call should use. If none is specified, the call defaults
- to using C calling conventions.
+ to using C calling conventions.
+
+
+ The optional Parameter Attributes list for
+ return values. Only 'zeroext', 'signext',
+ and 'inreg' attributes are valid here.
+
+
'ty': the type of the call instruction itself which is also
the type of the return value. Functions that return no value are marked
@@ -4183,6 +4376,11 @@ value argument; otherwise, it returns the second value argument.
indicates the function accepts a variable number of arguments, the extra
arguments can be specified.
+
+ The optional function attributes list. Only
+ 'noreturn', 'nounwind', 'readonly' and
+ 'readnone' attributes are valid here.
+
Semantics:
@@ -4192,9 +4390,7 @@ transfer to a specified function, with its incoming arguments bound to
the specified values. Upon a 'ret'
instruction in the called function, control flow continues with the
instruction after the function call, and the return value of the
-function is bound to the result argument. If the callee returns multiple
-values then the return values of the function are only accessible through
-the 'getresult' instruction.
+function is bound to the result argument.
Example:
@@ -4206,9 +4402,11 @@ the 'getresult' instruction.
call void %foo(i8 97 signext)
%struct.A = type { i32, i8 }
- %r = call %struct.A @foo() ; yields { 32, i8 }
- %gr = getresult %struct.A %r, 0 ; yields i32
- %gr1 = getresult %struct.A %r, 1 ; yields i8
+ %r = call %struct.A @foo() ; yields { 32, i8 }
+ %gr = extractvalue %struct.A %r, 0 ; yields i32
+ %gr1 = extractvalue %struct.A %r, 1 ; yields i8
+ %Z = call void @foo() noreturn ; indicates that %foo never returns normally
+ %ZZ = call zeroext i32 @bar() ; Return value is %zero extended
@@ -4261,52 +4459,6 @@ argument.
-
-
-
-
-
- Syntax:
-
- <resultval> = getresult <type> <retval>, <index>
-
-
- Overview:
-
- The 'getresult' instruction is used to extract individual values
-from a 'call'
-or 'invoke' instruction that returns multiple
-results.
-
- Arguments:
-
- The 'getresult' instruction takes a call or invoke value as its
-first argument, or an undef value. The value must have structure type. The second argument is a constant
-unsigned index value which must be in range for the number of values returned
-by the call.
-
- Semantics:
-
- The 'getresult' instruction extracts the element identified by
-'index' from the aggregate value.
-
- Example:
-
-
- %struct.A = type { i32, i8 }
-
- %r = call %struct.A @foo()
- %gr = getresult %struct.A %r, 0 ; yields i32:%gr
- %gr1 = getresult %struct.A %r, 1 ; yields i8:%gr1
- add i32 %gr, 42
- add i8 %gr1, 41
-
-
- Syntax:
declare void %llvm.va_start(i8* <arglist>)
Overview:
-The 'llvm.va_start' intrinsic initializes
+ The 'llvm.va_start' intrinsic initializes
*<arglist> for subsequent use by va_arg.
Arguments:
-The argument is a pointer to a va_list element to initialize.
+The argument is a pointer to a va_list element to initialize.
Semantics:
-The 'llvm.va_start' intrinsic works just like the va_start
+ The 'llvm.va_start' intrinsic works just like the va_start
macro available in C. In a target-dependent way, it initializes the
va_list element to which the argument points, so that the next call to
va_arg will produce the first variable argument passed to the function.
@@ -4510,7 +4662,8 @@ example, memory allocation.
LLVM support for Accurate Garbage
-Collection requires the implementation and generation of these intrinsics.
+Collection (GC) requires the implementation and generation of these
+intrinsics.
These intrinsics allow identification of GC roots on the
stack, as well as garbage collector implementations that require read and write barriers.
@@ -4862,11 +5015,12 @@ performance.
The 'llvm.pcmarker' intrinsic is a method to export a Program Counter
-(PC) in a region of
-code to simulators and other tools. The method is target specific, but it is
-expected that the marker will use exported symbols to transmit the PC of the marker.
-The marker makes no guarantees that it will remain with any specific instruction
-after optimizations. It is possible that the presence of a marker will inhibit
+(PC) in a region of
+code to simulators and other tools. The method is target specific, but it is
+expected that the marker will use exported symbols to transmit the PC of the
+marker.
+The marker makes no guarantees that it will remain with any specific instruction
+after optimizations. It is possible that the presence of a marker will inhibit
optimizations. The intended use is to be inserted after optimizations to allow
correlations of simulation runs.
@@ -4942,7 +5096,13 @@ for more efficient code generation.
Syntax:
+ This is an overloaded intrinsic. You can use llvm.memcpy on any integer bit
+width. Not all targets support all bit widths however.
+ declare void @llvm.memcpy.i8(i8 * <dest>, i8 * <src>,
+ i8 <len>, i32 <align>)
+ declare void @llvm.memcpy.i16(i8 * <dest>, i8 * <src>,
+ i16 <len>, i32 <align>)
declare void @llvm.memcpy.i32(i8 * <dest>, i8 * <src>,
i32 <len>, i32 <align>)
declare void @llvm.memcpy.i64(i8 * <dest>, i8 * <src>,
@@ -4996,7 +5156,13 @@ be set to 0 or 1.
Syntax:
+ This is an overloaded intrinsic. You can use llvm.memmove on any integer bit
+width. Not all targets support all bit widths however.
+ declare void @llvm.memmove.i8(i8 * <dest>, i8 * <src>,
+ i8 <len>, i32 <align>)
+ declare void @llvm.memmove.i16(i8 * <dest>, i8 * <src>,
+ i16 <len>, i32 <align>)
declare void @llvm.memmove.i32(i8 * <dest>, i8 * <src>,
i32 <len>, i32 <align>)
declare void @llvm.memmove.i64(i8 * <dest>, i8 * <src>,
@@ -5051,7 +5217,13 @@ be set to 0 or 1.
Syntax:
+ This is an overloaded intrinsic. You can use llvm.memset on any integer bit
+width. Not all targets support all bit widths however.
+ declare void @llvm.memset.i8(i8 * <dest>, i8 <val>,
+ i8 <len>, i32 <align>)
+ declare void @llvm.memset.i16(i8 * <dest>, i8 <val>,
+ i16 <len>, i32 <align>)
declare void @llvm.memset.i32(i8 * <dest>, i8 <val>,
i32 <len>, i32 <align>)
declare void @llvm.memset.i64(i8 * <dest>, i8 <val>,
@@ -5106,7 +5278,7 @@ this can be specified as the fourth argument, otherwise it should be set to 0 or
Syntax:
This is an overloaded intrinsic. You can use llvm.sqrt on any
floating point or vector of floating point type. Not all targets support all
-types however.
+types however.
declare float @llvm.sqrt.f32(float %Val)
declare double @llvm.sqrt.f64(double %Val)
@@ -5150,7 +5322,7 @@ floating point number.
Syntax:
This is an overloaded intrinsic. You can use llvm.powi on any
floating point or vector of floating point type. Not all targets support all
-types however.
+types however.
declare float @llvm.powi.f32(float %Val, i32 %power)
declare double @llvm.powi.f64(double %Val, i32 %power)
@@ -5192,7 +5364,7 @@ unspecified sequence of rounding operations.
Syntax:
This is an overloaded intrinsic. You can use llvm.sin on any
floating point or vector of floating point type. Not all targets support all
-types however.
+types however.
declare float @llvm.sin.f32(float %Val)
declare double @llvm.sin.f64(double %Val)
@@ -5231,7 +5403,7 @@ conditions in the same way.
Syntax:
This is an overloaded intrinsic. You can use llvm.cos on any
floating point or vector of floating point type. Not all targets support all
-types however.
+types however.
declare float @llvm.cos.f32(float %Val)
declare double @llvm.cos.f64(double %Val)
@@ -5270,7 +5442,7 @@ conditions in the same way.
Syntax:
This is an overloaded intrinsic. You can use llvm.pow on any
floating point or vector of floating point type. Not all targets support all
-types however.
+types however.
declare float @llvm.pow.f32(float %Val, float %Power)
declare double @llvm.pow.f64(double %Val, double %Power)
@@ -5325,7 +5497,7 @@ These allow efficient code generation for some algorithms.
Syntax:
This is an overloaded intrinsic function. You can use bswap on any integer
-type that is an even number of bytes (i.e. BitWidth % 16 == 0).
+type that is an even number of bytes (i.e. BitWidth % 16 == 0).
declare i16 @llvm.bswap.i16(i16 <id>)
declare i32 @llvm.bswap.i32(i32 <id>)
@@ -5364,7 +5536,7 @@ additional even-byte lengths (6 bytes, 8 bytes and more, respectively).
Syntax:
This is an overloaded intrinsic. You can use llvm.ctpop on any integer bit
-width. Not all targets support all bit widths however.
+width. Not all targets support all bit widths however.
declare i8 @llvm.ctpop.i8 (i8 <src>)
declare i16 @llvm.ctpop.i16(i16 <src>)
@@ -5403,7 +5575,7 @@ The 'llvm.ctpop' intrinsic counts the 1's in a variable.
Syntax:
This is an overloaded intrinsic. You can use llvm.ctlz on any
-integer bit width. Not all targets support all bit widths however.
+integer bit width. Not all targets support all bit widths however.
declare i8 @llvm.ctlz.i8 (i8 <src>)
declare i16 @llvm.ctlz.i16(i16 <src>)
@@ -5446,7 +5618,7 @@ of src. For example, llvm.ctlz(i32 2) = 30.
Syntax:
This is an overloaded intrinsic. You can use llvm.cttz on any
-integer bit width. Not all targets support all bit widths however.
+integer bit width. Not all targets support all bit widths however.
declare i8 @llvm.cttz.i8 (i8 <src>)
declare i16 @llvm.cttz.i16(i16 <src>)
@@ -5487,7 +5659,7 @@ of src. For example, llvm.cttz(2) = 1.
Syntax:
This is an overloaded intrinsic. You can use llvm.part.select
-on any integer bit width.
+on any integer bit width.
declare i17 @llvm.part.select.i17 (i17 %val, i32 %loBit, i32 %hiBit)
declare i29 @llvm.part.select.i29 (i29 %val, i32 %loBit, i32 %hiBit)
@@ -5517,7 +5689,7 @@ only the %hiBit - %loBit bits set, as follows:
The %loBits value is subtracted from the %hiBits value
to determine the number of bits to retain.
A mask of the retained bits is created by shifting a -1 value.
- The mask is ANDed with %val to produce the result.
+ The mask is ANDed with %val to produce the result.
In reverse mode, a similar computation is made except that the bits are
returned in the reverse order. So, for example, if X has the value
@@ -5534,7 +5706,7 @@ returned in the reverse order. So, for example, if X has the value
Syntax:
This is an overloaded intrinsic. You can use llvm.part.set
-on any integer bit width.
+on any integer bit width.
declare i17 @llvm.part.set.i17.i9 (i17 %val, i9 %repl, i32 %lo, i32 %hi)
declare i29 @llvm.part.set.i29.i9 (i29 %val, i9 %repl, i32 %lo, i32 %hi)
@@ -5563,10 +5735,10 @@ up to that size.
In forward mode, the bits between %lo and %hi (inclusive)
are replaced with corresponding bits from %repl. That is the 0th bit
in %repl replaces the %loth bit in %val and etc. up
-to the %hith bit.
+to the %hith bit.
In reverse mode, a similar computation is made except that the bits are
reversed. That is, the 0th bit in %repl replaces the
-%hi bit in %val and etc. down to the %loth bit.
+%hi bit in %val and etc. down to the %loth bit.
Examples:
llvm.part.set(0xFFFF, 0, 4, 7) -> 0xFF0F
@@ -5686,7 +5858,8 @@ declare i8* @llvm.init.trampoline(i8* <tramp>, i8* <func>, i8* <n
These intrinsic functions expand the "universal IR" of LLVM to represent
hardware constructs for atomic operations and memory synchronization. This
provides an interface to the hardware, not an interface to the programmer. It
- is aimed at a low enough level to allow any programming models or APIs which
+ is aimed at a low enough level to allow any programming models or APIs
+ (Application Programming Interfaces) which
need atomic behaviors to map cleanly onto it. It is also modeled primarily on
hardware behavior. Just as hardware provides a "universal IR" for source
languages, it also provides a starting point for developing a "universal"
@@ -5732,7 +5905,7 @@ i1 <device> )
ls: load-store barrier
sl: store-load barrier
ss: store-store barrier
- device: barrier applies to device and uncached memory also.
+ device: barrier applies to device and uncached memory also.
Semantics:
@@ -5778,19 +5951,20 @@ i1 <device> )
Syntax:
- This is an overloaded intrinsic. You can use llvm.atomic.lcs on any
- integer bit width. Not all targets support all bit widths however.
+ This is an overloaded intrinsic. You can use llvm.atomic.cmp.swap on
+ any integer bit width and for different address spaces. Not all targets
+ support all bit widths however.
-declare i8 @llvm.atomic.lcs.i8( i8* <ptr>, i8 <cmp>, i8 <val> )
-declare i16 @llvm.atomic.lcs.i16( i16* <ptr>, i16 <cmp>, i16 <val> )
-declare i32 @llvm.atomic.lcs.i32( i32* <ptr>, i32 <cmp>, i32 <val> )
-declare i64 @llvm.atomic.lcs.i64( i64* <ptr>, i64 <cmp>, i64 <val> )
+declare i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* <ptr>, i8 <cmp>, i8 <val> )
+declare i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* <ptr>, i16 <cmp>, i16 <val> )
+declare i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* <ptr>, i32 <cmp>, i32 <val> )
+declare i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* <ptr>, i64 <cmp>, i64 <val> )
Overview:
@@ -5800,7 +5974,7 @@ declare i64 @llvm.atomic.lcs.i64( i64* <ptr>, i64 <cmp>, i64 <val
Arguments:
- The llvm.atomic.lcs intrinsic takes three arguments. The result as
+ The llvm.atomic.cmp.swap intrinsic takes three arguments. The result as
well as both cmp and val must be integer values with the
same bit width. The ptr argument must be a pointer to a value of
this integer type. While any bit width integer may be used, targets may only
@@ -5822,13 +5996,13 @@ declare i64 @llvm.atomic.lcs.i64( i64* <ptr>, i64 <cmp>, i64 <val
store i32 4, %ptr
%val1 = add i32 4, 4
-%result1 = call i32 @llvm.atomic.lcs.i32( i32* %ptr, i32 4, %val1 )
+%result1 = call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %ptr, i32 4, %val1 )
; yields {i32}:result1 = 4
%stored1 = icmp eq i32 %result1, 4 ; yields {i1}:stored1 = true
%memval1 = load i32* %ptr ; yields {i32}:memval1 = 8
%val2 = add i32 1, 1
-%result2 = call i32 @llvm.atomic.lcs.i32( i32* %ptr, i32 5, %val2 )
+%result2 = call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %ptr, i32 5, %val2 )
; yields {i32}:result2 = 8
%stored2 = icmp eq i32 %result2, 5 ; yields {i1}:stored2 = false
@@ -5847,10 +6021,10 @@ declare i64 @llvm.atomic.lcs.i64( i64* <ptr>, i64 <cmp>, i64 <val
This is an overloaded intrinsic. You can use llvm.atomic.swap on any
integer bit width. Not all targets support all bit widths however.
-declare i8 @llvm.atomic.swap.i8( i8* <ptr>, i8 <val> )
-declare i16 @llvm.atomic.swap.i16( i16* <ptr>, i16 <val> )
-declare i32 @llvm.atomic.swap.i32( i32* <ptr>, i32 <val> )
-declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
+declare i8 @llvm.atomic.swap.i8.p0i8( i8* <ptr>, i8 <val> )
+declare i16 @llvm.atomic.swap.i16.p0i16( i16* <ptr>, i16 <val> )
+declare i32 @llvm.atomic.swap.i32.p0i32( i32* <ptr>, i32 <val> )
+declare i64 @llvm.atomic.swap.i64.p0i64( i64* <ptr>, i64 <val> )
Overview:
@@ -5862,7 +6036,7 @@ declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
Arguments:
- The llvm.atomic.ls intrinsic takes two arguments. Both the
+ The llvm.atomic.swap intrinsic takes two arguments. Both the
val argument and the result must be integers of the same bit width.
The first argument, ptr, must be a pointer to a value of this
integer type. The targets may only lower integer representations they
@@ -5881,13 +6055,13 @@ declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
store i32 4, %ptr
%val1 = add i32 4, 4
-%result1 = call i32 @llvm.atomic.swap.i32( i32* %ptr, i32 %val1 )
+%result1 = call i32 @llvm.atomic.swap.i32.p0i32( i32* %ptr, i32 %val1 )
; yields {i32}:result1 = 4
%stored1 = icmp eq i32 %result1, 4 ; yields {i1}:stored1 = true
%memval1 = load i32* %ptr ; yields {i32}:memval1 = 8
%val2 = add i32 1, 1
-%result2 = call i32 @llvm.atomic.swap.i32( i32* %ptr, i32 %val2 )
+%result2 = call i32 @llvm.atomic.swap.i32.p0i32( i32* %ptr, i32 %val2 )
; yields {i32}:result2 = 8
%stored2 = icmp eq i32 %result2, 8 ; yields {i1}:stored2 = true
@@ -5897,19 +6071,19 @@ declare i64 @llvm.atomic.swap.i64( i64* <ptr>, i64 <val> )
Syntax:
- This is an overloaded intrinsic. You can use llvm.atomic.las on any
+ This is an overloaded intrinsic. You can use llvm.atomic.load.add on any
integer bit width. Not all targets support all bit widths however.
-declare i8 @llvm.atomic.las.i8.( i8* <ptr>, i8 <delta> )
-declare i16 @llvm.atomic.las.i16.( i16* <ptr>, i16 <delta> )
-declare i32 @llvm.atomic.las.i32.( i32* <ptr>, i32 <delta> )
-declare i64 @llvm.atomic.las.i64.( i64* <ptr>, i64 <delta> )
+declare i8 @llvm.atomic.load.add.i8..p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.add.i16..p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.add.i32..p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.add.i64..p0i64( i64* <ptr>, i64 <delta> )
Overview:
@@ -5936,17 +6110,238 @@ declare i64 @llvm.atomic.las.i64.( i64* <ptr>, i64 <delta> )
%ptr = malloc i32
store i32 4, %ptr
-%result1 = call i32 @llvm.atomic.las.i32( i32* %ptr, i32 4 )
+%result1 = call i32 @llvm.atomic.load.add.i32.p0i32( i32* %ptr, i32 4 )
; yields {i32}:result1 = 4
-%result2 = call i32 @llvm.atomic.las.i32( i32* %ptr, i32 2 )
+%result2 = call i32 @llvm.atomic.load.add.i32.p0i32( i32* %ptr, i32 2 )
; yields {i32}:result2 = 8
-%result3 = call i32 @llvm.atomic.las.i32( i32* %ptr, i32 5 )
+%result3 = call i32 @llvm.atomic.load.add.i32.p0i32( i32* %ptr, i32 5 )
; yields {i32}:result3 = 10
-%memval = load i32* %ptr ; yields {i32}:memval1 = 15
+%memval1 = load i32* %ptr ; yields {i32}:memval1 = 15
+
+
+
+
+
+
+ Syntax:
+
+ This is an overloaded intrinsic. You can use llvm.atomic.load.sub on
+ any integer bit width and for different address spaces. Not all targets
+ support all bit widths however.
+
+declare i8 @llvm.atomic.load.sub.i8.p0i32( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.sub.i16.p0i32( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.sub.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.sub.i64.p0i32( i64* <ptr>, i64 <delta> )
+
+
+ Overview:
+
+ This intrinsic subtracts delta to the value stored in memory at
+ ptr. It yields the original value at ptr.
+
+ Arguments:
+
+
+ The intrinsic takes two arguments, the first a pointer to an integer value
+ and the second an integer value. The result is also an integer value. These
+ integer types can have any bit width, but they must all have the same bit
+ width. The targets may only lower integer representations they support.
+
+ Semantics:
+
+ This intrinsic does a series of operations atomically. It first loads the
+ value stored at ptr. It then subtracts delta, stores the
+ result to ptr. It yields the original value stored at ptr.
+
+
+ Examples:
+
+%ptr = malloc i32
+ store i32 8, %ptr
+%result1 = call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %ptr, i32 4 )
+ ; yields {i32}:result1 = 8
+%result2 = call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %ptr, i32 2 )
+ ; yields {i32}:result2 = 4
+%result3 = call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %ptr, i32 5 )
+ ; yields {i32}:result3 = 2
+%memval1 = load i32* %ptr ; yields {i32}:memval1 = -3
+
+
+
+
+
+
+ Syntax:
+
+ These are overloaded intrinsics. You can use llvm.atomic.load_and,
+ llvm.atomic.load_nand, llvm.atomic.load_or, and
+ llvm.atomic.load_xor on any integer bit width and for different
+ address spaces. Not all targets support all bit widths however.
+
+declare i8 @llvm.atomic.load.and.i8.p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.and.i16.p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.and.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.and.i64.p0i64( i64* <ptr>, i64 <delta> )
+
+
+
+
+declare i8 @llvm.atomic.load.or.i8.p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.or.i16.p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.or.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.or.i64.p0i64( i64* <ptr>, i64 <delta> )
+
+
+
+
+declare i8 @llvm.atomic.load.nand.i8.p0i32( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.nand.i16.p0i32( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.nand.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.nand.i64.p0i32( i64* <ptr>, i64 <delta> )
+
+
+
+
+declare i8 @llvm.atomic.load.xor.i8.p0i32( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.xor.i16.p0i32( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.xor.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.xor.i64.p0i32( i64* <ptr>, i64 <delta> )
+
+
+ Overview:
+
+ These intrinsics bitwise the operation (and, nand, or, xor) delta to
+ the value stored in memory at ptr. It yields the original value
+ at ptr.
+
+ Arguments:
+
+
+ These intrinsics take two arguments, the first a pointer to an integer value
+ and the second an integer value. The result is also an integer value. These
+ integer types can have any bit width, but they must all have the same bit
+ width. The targets may only lower integer representations they support.
+
+ Semantics:
+
+ These intrinsics does a series of operations atomically. They first load the
+ value stored at ptr. They then do the bitwise operation
+ delta, store the result to ptr. They yield the original
+ value stored at ptr.
+
+
+ Examples:
+
+%ptr = malloc i32
+ store i32 0x0F0F, %ptr
+%result0 = call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %ptr, i32 0xFF )
+ ; yields {i32}:result0 = 0x0F0F
+%result1 = call i32 @llvm.atomic.load.and.i32.p0i32( i32* %ptr, i32 0xFF )
+ ; yields {i32}:result1 = 0xFFFFFFF0
+%result2 = call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ptr, i32 0F )
+ ; yields {i32}:result2 = 0xF0
+%result3 = call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %ptr, i32 0F )
+ ; yields {i32}:result3 = FF
+%memval1 = load i32* %ptr ; yields {i32}:memval1 = F0
+
+
+
+ Syntax:
+
+ These are overloaded intrinsics. You can use llvm.atomic.load_max,
+ llvm.atomic.load_min, llvm.atomic.load_umax, and
+ llvm.atomic.load_umin on any integer bit width and for different
+ address spaces. Not all targets
+ support all bit widths however.
+
+declare i8 @llvm.atomic.load.max.i8.p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.max.i16.p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.max.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.max.i64.p0i64( i64* <ptr>, i64 <delta> )
+
+
+
+
+declare i8 @llvm.atomic.load.min.i8.p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.min.i16.p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.min.i32..p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.min.i64..p0i64( i64* <ptr>, i64 <delta> )
+
+
+
+
+declare i8 @llvm.atomic.load.umax.i8.p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.umax.i16.p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.umax.i32.p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.umax.i64.p0i64( i64* <ptr>, i64 <delta> )
+
+
+
+
+declare i8 @llvm.atomic.load.umin.i8..p0i8( i8* <ptr>, i8 <delta> )
+declare i16 @llvm.atomic.load.umin.i16.p0i16( i16* <ptr>, i16 <delta> )
+declare i32 @llvm.atomic.load.umin.i32..p0i32( i32* <ptr>, i32 <delta> )
+declare i64 @llvm.atomic.load.umin.i64..p0i64( i64* <ptr>, i64 <delta> )
+
+
+ Overview:
+
+ These intrinsics takes the signed or unsigned minimum or maximum of
+ delta and the value stored in memory at ptr. It yields the
+ original value at ptr.
+
+ Arguments:
+
+
+ These intrinsics take two arguments, the first a pointer to an integer value
+ and the second an integer value. The result is also an integer value. These
+ integer types can have any bit width, but they must all have the same bit
+ width. The targets may only lower integer representations they support.
+
+ Semantics:
+
+ These intrinsics does a series of operations atomically. They first load the
+ value stored at ptr. They then do the signed or unsigned min or max
+ delta and the value, store the result to ptr. They yield
+ the original value stored at ptr.
+
+
+ Examples:
+
+%ptr = malloc i32
+ store i32 7, %ptr
+%result0 = call i32 @llvm.atomic.load.min.i32.p0i32( i32* %ptr, i32 -2 )
+ ; yields {i32}:result0 = 7
+%result1 = call i32 @llvm.atomic.load.max.i32.p0i32( i32* %ptr, i32 8 )
+ ; yields {i32}:result1 = -2
+%result2 = call i32 @llvm.atomic.load.umin.i32.p0i32( i32* %ptr, i32 10 )
+ ; yields {i32}:result2 = 8
+%result3 = call i32 @llvm.atomic.load.umax.i32.p0i32( i32* %ptr, i32 30 )
+ ; yields {i32}:result3 = 8
+%memval1 = load i32* %ptr ; yields {i32}:memval1 = 30
+
+
+
General Intrinsics
@@ -6034,6 +6429,7 @@ This intrinsic allows annotations to be put on arbitrary expressions
with arbitrary strings. This can be useful for special purpose optimizations
that want to look for these annotations. These have no other defined use, they
are ignored by code generation and optimization.
+
@@ -6069,13 +6465,47 @@ call of the abort() function.
+
+
+
+ Syntax:
+
+declare void @llvm.stackprotector( i8* <guard>, i8** <slot> )
+
+
+ Overview:
+
+ The llvm.stackprotector intrinsic takes the guard and stores
+ it onto the stack at slot. The stack slot is adjusted to ensure that
+ it is placed on the stack before local variables.
+
+ Arguments:
+
+ The llvm.stackprotector intrinsic requires two pointer arguments. The
+ first argument is the value loaded from the stack guard
+ @__stack_chk_guard. The second variable is an alloca that
+ has enough space to hold the value of the guard.
+
+ Semantics:
+
+ This intrinsic causes the prologue/epilogue inserter to force the position of
+ the AllocaInst stack slot to be before local variables on the
+ stack. This is to ensure that if a local variable on the stack is overwritten,
+ it will destroy the value of the guard. When the function exits, the guard on
+ the stack is checked against the original guard. If they're different, then
+ the program aborts by calling the __stack_chk_fail() function.
+
+
+
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Chris Lattner
The LLVM Compiler Infrastructure
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