X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=docs%2FCodeGenerator.rst;h=75d40db958c09b89e1ec31c4c3c2a88d690b9020;hb=1758082f64077aeaa33b397a561e0483a2e02d37;hp=1f2dc6ca7f7f40035aa8a0873aa8e1341a3b3d3e;hpb=6fccaafd8be0eb7619b5a210387b0d1254ef4174;p=oota-llvm.git diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index 1f2dc6ca7f7..75d40db958c 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -70,7 +70,7 @@ different pieces of this will be useful to you. In any case, you should be familiar with the `target description`_ and `machine code representation`_ classes. If you want to add a backend for a new target, you will need to `implement the target description`_ classes for your new target and understand -the `LLVM code representation `_. If you are interested in +the :doc:`LLVM code representation `. If you are interested in implementing a new `code generation algorithm`_, it should only depend on the target-description and machine code representation classes, ensuring that it is portable. @@ -172,7 +172,7 @@ architecture. These target descriptions often have a large amount of common information (e.g., an ``add`` instruction is almost identical to a ``sub`` instruction). In order to allow the maximum amount of commonality to be factored out, the LLVM code generator uses the -:doc:`TableGen ` tool to describe big chunks of the +:doc:`TableGen/index` tool to describe big chunks of the target machine, which allows the use of domain-specific and target-specific abstractions to reduce the amount of repetition. @@ -277,7 +277,7 @@ an associated register class. When the register allocator runs, it replaces virtual registers with a physical register in the set. The target-specific implementations of these classes is auto-generated from a -`TableGen `_ description of the register file. +:doc:`TableGen/index` description of the register file. .. _TargetInstrInfo: @@ -290,10 +290,10 @@ the opcode, the number of operands, the list of implicit register uses and defs, whether the instruction has certain target-independent properties (accesses memory, is commutable, etc), and holds any target-specific flags. -The ``TargetFrameInfo`` class ------------------------------ +The ``TargetFrameLowering`` class +--------------------------------- -The ``TargetFrameInfo`` class is used to provide information about the stack +The ``TargetFrameLowering`` class is used to provide information about the stack frame layout of the target. It holds the direction of stack growth, the known stack alignment on entry to each function, and the offset to the local area. The offset to the local area is the offset from the stack pointer on function @@ -434,12 +434,12 @@ For example, consider this simple LLVM example: .. code-block:: llvm define i32 @test(i32 %X, i32 %Y) { - %Z = udiv i32 %X, %Y + %Z = sdiv i32 %X, %Y ret i32 %Z } -The X86 instruction selector produces this machine code for the ``div`` and -``ret`` (use "``llc X.bc -march=x86 -print-machineinstrs``" to get this): +The X86 instruction selector might produce this machine code for the ``div`` and +``ret``: .. code-block:: llvm @@ -454,8 +454,8 @@ The X86 instruction selector produces this machine code for the ``div`` and %EAX = mov %reg1026 ;; 32-bit return value goes in EAX ret -By the end of code generation, the register allocator has coalesced the -registers and deleted the resultant identity moves producing the following +By the end of code generation, the register allocator would coalesce the +registers and delete the resultant identity moves producing the following code: .. code-block:: llvm @@ -464,7 +464,7 @@ code: mov %EAX, %EDX sar %EDX, 31 idiv %ECX - ret + ret This approach is extremely general (if it can handle the X86 architecture, it can handle anything!) and allows all of the target specific knowledge about the @@ -636,6 +636,18 @@ file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation that prints out a directive for each method (e.g. ``EmitValue -> .byte``), but MCObjectStreamer implements a full assembler. +For target specific directives, the MCStreamer has a MCTargetStreamer instance. +Each target that needs it defines a class that inherits from it and is a lot +like MCStreamer itself: It has one method per directive and two classes that +inherit from it, a target object streamer and a target asm streamer. The target +asm streamer just prints it (``emitFnStart -> .fnstrart``), and the object +streamer implement the assembler logic for it. + +To make llvm use these classes, the target initialization must call +TargetRegistry::RegisterAsmStreamer and TargetRegistry::RegisterMCObjectStreamer +passing callbacks that allocate the corresponding target streamer and pass it +to createAsmStreamer or to the appropriate object streamer constructor. + The ``MCContext`` class ----------------------- @@ -757,7 +769,9 @@ provide an ordering between nodes that have side effects (such as loads, stores, calls, returns, etc). All nodes that have side effects should take a token chain as input and produce a new one as output. By convention, token chain inputs are always operand #0, and chain results are always the last value -produced by an operation. +produced by an operation. However, after instruction selection, the +machine nodes have their chain after the instruction's operands, and +may be followed by glue nodes. A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is always a marker node with an Opcode of ``ISD::EntryToken``. The Root node is @@ -834,6 +848,10 @@ is based on the final SelectionDAG, with nodes that must be scheduled together bundled into a single scheduling-unit node, and with immediate operands and other nodes that aren't relevant for scheduling omitted. +The option ``-filter-view-dags`` allows to select the name of the basic block +that you are interested to visualize and filters all the previous +``view-*-dags`` options. + .. _Build initial DAG: Initial SelectionDAG Construction @@ -1216,7 +1234,7 @@ used. Each virtual register can only be mapped to physical registers of a particular class. For instance, in the X86 architecture, some virtuals can only be allocated to 8 bit registers. A register class is described by ``TargetRegisterClass`` objects. To discover if a virtual register is -compatible with a given physical, this code can be used:

+compatible with a given physical, this code can be used: .. code-block:: c++ @@ -1322,7 +1340,7 @@ found before being stored or after being reloaded. If the indirect strategy is used, after all the virtual registers have been mapped to physical registers or stack slots, it is necessary to use a spiller object to place load and store instructions in the code. Every virtual that has -been mapped to a stack slot will be stored to memory after been defined and will +been mapped to a stack slot will be stored to memory after being defined and will be loaded before being used. The implementation of the spiller tries to recycle load/store instructions, avoiding unnecessary instructions. For an example of how to invoke the spiller, see ``RegAllocLinearScan::runOnMachineFunction`` in @@ -1335,7 +1353,7 @@ With very rare exceptions (e.g., function calls), the LLVM machine code instructions are three address instructions. That is, each instruction is expected to define at most one register, and to use at most two registers. However, some architectures use two address instructions. In this case, the -defined register is also one of the used register. For instance, an instruction +defined register is also one of the used registers. For instance, an instruction such as ``ADD %EAX, %EBX``, in X86 is actually equivalent to ``%EAX = %EAX + %EBX``. @@ -1560,7 +1578,7 @@ three important things that you have to implement for your target: correspond to. The MCInsts that are generated by this are fed into the instruction printer or the encoder. -Finally, at your choosing, you can also implement an subclass of MCCodeEmitter +Finally, at your choosing, you can also implement a subclass of MCCodeEmitter which lowers MCInst's into machine code bytes and relocations. This is important if you want to support direct .o file emission, or would like to implement an assembler for your target. @@ -1614,7 +1632,7 @@ Implementing a Native Assembler =============================== Though you're probably reading this because you want to write or maintain a -compiler backend, LLVM also fully supports building a native assemblers too. +compiler backend, LLVM also fully supports building a native assembler. We've tried hard to automate the generation of the assembler from the .td files (in particular the instruction syntax and encodings), which means that a large part of the manual and repetitive data entry can be factored and shared with the @@ -1671,7 +1689,7 @@ ones supported by the matcher), through a Requires clause: def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; -In this example, the mnemonic gets mapped into different a new one depending on +In this example, the mnemonic gets mapped into a different one depending on the current instruction set. Instruction Aliases @@ -1981,7 +1999,7 @@ Tail Calls This box indicates whether the target supports guaranteed tail calls. These are calls marked "`tail `_" and use the fastcc calling -convention. Please see the `tail call section more more details`_. +convention. Please see the `tail call section`_ for more details. .. _feat_segstacks: @@ -1999,7 +2017,7 @@ Basic support exists on the X86 backend. Currently vararg doesn't work and the object files are not marked the way the gold linker expects, but simple Go programs can be built by dragonegg. -.. _tail call section more more details: +.. _tail call section: Tail call optimization ---------------------- @@ -2015,7 +2033,7 @@ supported on x86/x86-64 and PowerPC. It is performed if: * Option ``-tailcallopt`` is enabled. -* Platform specific constraints are met. +* Platform-specific constraints are met. x86/x86-64 constraints: