X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3399-android.dtsi;h=720a902c10060ee9a76caf1e1d1f331ceecb480f;hb=3f7948b47646b9438d202a7c16f90ca2f98d9dea;hp=49edcbbf9c96f017d65b990a84fa0eb5a260b704;hpb=a8b948f89f888b82ddc1b83105b2cc582c7dced7;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi index 49edcbbf9c96..720a902c1006 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi @@ -45,12 +45,17 @@ / { compatible = "rockchip,android", "rockchip,rk3399"; + aliases { + lcdc0 = &vopb_rk_fb; + lcdc1 = &vopl_rk_fb; + }; + chosen { - bootargs = "console=uart,mmio32,0xff1a0000"; + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1"; }; ramoops_mem: ramoops_mem { - reg = <0x0 0x100000 0x0 0x100000>; + reg = <0x0 0x110000 0x0 0xf0000>; reg-names = "ramoops_mem"; }; @@ -58,11 +63,22 @@ compatible = "ramoops"; record-size = <0x0 0x20000>; console-size = <0x0 0x80000>; - ftrace-size = <0x0 0x10000>; + ftrace-size = <0x0 0x00000>; pmsg-size = <0x0 0x50000>; memory-region = <&ramoops_mem>; }; + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <182>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -75,6 +91,11 @@ size = <0x0 0x8000000>; linux,cma-default; }; + /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */ + rockchip_logo: rockchip-logo@00000000 { + compatible = "rockchip,fb-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; }; ion { @@ -140,27 +161,72 @@ }; }; + cdn_dp_fb: dp-fb@fec00000 { + status = "disabled"; + compatible = "rockchip,rk3399-cdn-dp-fb"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3399_PD_HDCP>; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>; + reset-names = "spdif", "dptx", "apb"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + cdn_dp_sound: cdn-dp-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,cdn-dp-fb"; + simple-audio-card,widgets = "Headphone", "Out Jack", + "Line", "In Jack"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + mclk-fs = <256>; + + cpu { + sound-dai = <&i2s2>; + }; + + codec { + sound-dai = <&cdn_dp_fb 0>; + }; + }; + }; + vpu: vpu_service@ff650000 { compatible = "rockchip,vpu_service"; rockchip,grf = <&grf>; iommu_enabled = <1>; reg = <0x0 0xff650000 0x0 0x800>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "irq_dec", "irq_enc"; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; clock-names = "aclk_vcodec", "hclk_vcodec"; resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; reset-names = "video_h", "video_a"; + power-domains = <&power RK3399_PD_VCODEC>; name = "vpu_service"; dev_mode = <0>; + /* 0 means ion, 1 means drm */ + allocator = <0>; }; vpu_mmu: vpu_mmu { dbgname = "vpu"; compatible = "rockchip,vpu_mmu"; reg = <0x0 0xff650800 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "vpu_mmu"; }; @@ -169,14 +235,17 @@ rockchip,grf = <&grf>; iommu_enabled = <1>; reg = <0x0 0xff660000 0x0 0x400>; - interrupts = ; + interrupts = ; interrupt-names = "irq_dec"; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>; clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core"; resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>; reset-names = "video_h", "video_a"; + power-domains = <&power RK3399_PD_VDU>; dev_mode = <2>; name = "rkvdec"; + /* 0 means ion, 1 means drm */ + allocator = <0>; }; vdec_mmu: vdec_mmu { @@ -184,7 +253,7 @@ compatible = "rockchip,vdec_mmu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "vdec_mmu"; }; @@ -192,9 +261,10 @@ compatible = "rockchip,iep"; iommu_enabled = <1>; reg = <0x0 0xff670000 0x0 0x800>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3399_PD_IEP>; version = <2>; }; @@ -202,7 +272,7 @@ dbgname = "iep"; compatible = "rockchip,iep_mmu"; reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; + interrupts = ; interrupt-names = "iep_mmu"; }; @@ -210,26 +280,32 @@ compatible = "rockchip,rga2"; dev_mode = <1>; reg = <0x0 0xff680000 0x0 0x1000>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3399_PD_RGA>; + status = "okay"; }; fb: fb { + status = "okay"; compatible = "rockchip,rk-fb"; rockchip,disp-mode = ; + rockchip,uboot-logo-on = <1>; + memory-region = <&rockchip_logo>; }; rk_screen: screen { + status = "okay"; compatible = "rockchip,screen"; - #include }; vopb_rk_fb: vop-rk-fb@ff900000 { + status = "disabled"; compatible = "rockchip,rk3399-lcdc"; rockchip,prop = ; reg = <0x0 0xff900000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; @@ -237,42 +313,25 @@ rockchip,grf = <&grf>; rockchip,pwr18 = <0>; rockchip,iommu-enabled = <1>; - power_ctr: power_ctr { - /*rockchip,debug = <0>; - lcd_en: lcd-en { - rockchip,power_type = ; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;//GPIO_C6 = 22 - rockchip,delay = <10>; - }; - */ - - /*lcd_cs: lcd-cs { - rockchip,power_type = ; - gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;//GPIO_C5 = 21 - rockchip,delay = <10>; - };*/ - - /*lcd_rst: lcd-rst { - rockchip,power_type = ; - gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>; - rockchip,delay = <5>; - };*/ - }; + power-domains = <&power RK3399_PD_VOPB>; + devfreq = <&dmc>; }; vopb_mmu_rk_fb: vopb-mmu { + status = "okay"; dbgname = "vop"; compatible = "rockchip,vopb_mmu"; reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopb_mmu"; }; vopl_rk_fb: vop-rk-fb@ff8f0000 { + status = "disabled"; compatible = "rockchip,rk3399-lcdc"; rockchip,prop = ; reg = <0x0 0xff8f0000 0x0 0x3efc>; - interrupts = ; + interrupts = ; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc"; resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; @@ -280,20 +339,161 @@ rockchip,grf = <&grf>; rockchip,pwr18 = <0>; rockchip,iommu-enabled = <1>; + power-domains = <&power RK3399_PD_VOPL>; + devfreq = <&dmc>; }; vopl_mmu_rk_fb: vopl-mmu { + status = "okay"; dbgname = "vop"; compatible = "rockchip,vopl_mmu"; reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; + interrupts = ; interrupt-names = "vopl_mmu"; }; + cif_isp0: cif_isp@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + rockchip,grf = <&grf>; + reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>; + reg-names = "register", "dsihost-register"; + clocks = + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>, + <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>, + <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>; + clock-names = + "clk_cif_out", "clk_cif_pll", + "pclk_dphytxrx", "pclk_dphy_ref", + "aclk_isp0_noc", "aclk_isp0_wrapper", + "hclk_isp0_noc", "hclk_isp0_wrapper", + "clk_isp0", "pclk_dphyrx"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + power-domains = <&power RK3399_PD_ISP0>; + status = "disabled"; + }; + + isp0: isp@ff910000 { + compatible = "rockchip,rk3399-isp", "rockchip,isp"; + reg = <0x0 0xff910000 0x0 0x10000>; + interrupts = ; + clocks = + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>, + <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>, + <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>; + clock-names = + "clk_cif_out", "clk_cif_pll", + "pclk_dphytxrx", "pclk_dphy_ref", + "aclk_isp0_noc", "aclk_isp0_wrapper", + "hclk_isp0_noc", "hclk_isp0_wrapper", + "clk_isp0", "pclk_dphyrx"; + pinctrl-names = + "cif_clkout","isp_dvp8bit0", "isp_mipi_fl", + "isp_mipi_fl_prefl", "isp_flash_as_gpio", + "isp_flash_as_trigger_out"; + pinctrl-0 = <&cif_clkout>; + pinctrl-1 = <&isp_dvp_d0d7>; + pinctrl-2 = <&cif_clkout>; + pinctrl-3 = <&isp_prelight>; + pinctrl-4 = <&isp_flash_trigger_as_gpio>; + pinctrl-5 = <&isp_flash_trigger>; + rockchip,isp,mipiphy = <2>; + rockchip,isp,cifphy = <1>; + rockchip,isp,dsiphy,reg = <0xff968000 0x8000>; + rockchip,grf = <&grf>; + rockchip,cru = <&cru>; + rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + rockchip,isp,iommu-enable = <1>; + power-domains = <&power RK3399_PD_ISP0>; + status = "disabled"; + }; + + isp0_mmu { + dbgname = "isp0"; + compatible = "rockchip,isp0_mmu"; + reg = <0x0 0xff914000 0x0 0x100>, + <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp0_mmu"; + }; + + isp1: isp@ff920000 { + compatible = "rockchip,rk3399-isp", "rockchip,isp"; + reg = <0x0 0xff920000 0x0 0x10000>; + interrupts = ; + clocks = + <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>, + <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>, + <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>, + <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_MIPIDPHY_CFG>; + clock-names = + "aclk_isp1_noc", "aclk_isp1_wrapper", + "hclk_isp1_noc", "hclk_isp1_wrapper", + "clk_isp1", "clk_cif_out", + "clk_cif_pll", "pclk_dphytxrx", + "pclk_dphy_ref", "pclk_isp1", + "pclk_dphyrx", "pclk_mipi_dsi", + "mipi_dphy_cfg"; + pinctrl-names = + "cif_clkout","isp_dvp8bit0", "isp_mipi_fl", + "isp_mipi_fl_prefl", "isp_flash_as_gpio", + "isp_flash_as_trigger_out"; + pinctrl-0 = <&cif_clkout>; + pinctrl-1 = <&isp_dvp_d0d7>; + pinctrl-2 = <&cif_clkout>; + pinctrl-3 = <&isp_prelight>; + pinctrl-4 = <&isp_flash_trigger_as_gpio>; + pinctrl-5 = <&isp_flash_trigger>; + rockchip,isp,mipiphy = <2>; + rockchip,isp,cifphy = <1>; + rockchip,isp,dsiphy,reg = <0xff968000 0x8000>; + rockchip,grf = <&grf>; + rockchip,cru = <&cru>; + rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + rockchip,isp,iommu-enable = <1>; + power-domains = <&power RK3399_PD_ISP1>; + status = "disabled"; + }; + + isp1_mmu { + dbgname = "isp1"; + compatible = "rockchip,isp1_mmu"; + reg = <0x0 0xff924000 0x0 0x100>, + <0x0 0xff925000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp1_mmu"; + }; + hdmi_rk_fb: hdmi-rk-fb@ff940000 { + status = "disabled"; compatible = "rockchip,rk3399-hdmi"; reg = <0x0 0xff940000 0x0 0x20000>; - status = "disabled"; + interrupts = , + ; + clocks = <&cru PCLK_HDMI_CTRL>, + <&cru HCLK_HDCP>, + <&cru SCLK_HDMI_CEC>, + <&cru PLL_VPLL>, + <&cru SCLK_HDMI_SFR>; + clock-names = "pclk_hdmi", + "hdcp_clk_hdmi", + "cec_clk_hdmi", + "dclk_hdmi_phy", + "sclk_hdmi_sfr"; + resets = <&cru SRST_HDMI_CTRL>; + reset-names = "hdmi"; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>; + pinctrl-1 = <&i2c3_gpio>; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_HDCP>; }; mipi0_rk_fb: mipi-rk-fb@ff960000 { @@ -301,17 +501,105 @@ rockchip,prop = <0>; rockchip,grf = <&grf>; reg = <0x0 0xff960000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>; clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg"; + power-domains = <&power RK3399_PD_VIO>; + status = "disabled"; }; mipi1_rk_fb: mipi-rk-fb@ff968000 { compatible = "rockchip,rk3399-dsi"; rockchip,prop = <1>; + rockchip,grf = <&grf>; reg = <0x0 0xff968000 0x0 0x8000>; - interrupts = ; + interrupts = ; clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>; clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg"; + power-domains = <&power RK3399_PD_VIO>; + status = "disabled"; + }; + + edp_rk_fb: edp-rk-fb@ff970000 { + compatible = "rockchip,rk3399-edp-fb"; + reg = <0x0 0xff970000 0x0 0x8000>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; + clock-names = "clk_edp", "pclk_edp", "clk_grf"; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "edp_apb"; + status = "disabled"; + power-domains = <&power RK3399_PD_EDP>; + }; +}; + +&pinctrl { + isp { + cif_clkout: cif-clkout { + rockchip,pins = + /*cif_clkout*/ + <2 11 RK_FUNC_3 &pcfg_pull_none>; + }; + + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + /*cif_data0*/ + <2 0 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data1*/ + <2 1 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data2*/ + <2 2 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data3*/ + <2 3 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data4*/ + <2 4 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data5*/ + <2 5 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data6*/ + <2 6 RK_FUNC_3 &pcfg_pull_none>, + /*cif_data7*/ + <2 7 RK_FUNC_3 &pcfg_pull_none>, + /*cif_sync*/ + <2 8 RK_FUNC_3 &pcfg_pull_none>, + /*cif_href*/ + <2 9 RK_FUNC_3 &pcfg_pull_none>, + /*cif_clkin*/ + <2 10 RK_FUNC_3 &pcfg_pull_none>; + }; + + isp_shutter: isp-shutter { + rockchip,pins = + /*SHUTTEREN*/ + <1 1 RK_FUNC_1 &pcfg_pull_none>, + /*SHUTTERTRIG*/ + <1 0 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_flash_trigger: isp-flash-trigger { + /*ISP_FLASHTRIGOU*/ + rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_prelight: isp-prelight { + /*ISP_PRELIGHTTRIG*/ + rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio { + /*ISP_FLASHTRIGOU*/ + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam_pins { + cam0_default_pins: cam0-default-pins { + rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>, + <2 11 RK_FUNC_3 &pcfg_pull_none>; + }; + cam0_sleep_pins: cam0-sleep-pins { + rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>, + <2 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; };