X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3368.dtsi;h=b931379811ac223f443df9ce5328ed21d29ebfa8;hb=c2b3e8740d8dcadbf90f8e9d947841cd2b7baa4a;hp=cc093a482aa461f9bd62914e28fc94b1d693d8b6;hpb=c34e6e0bd5d729948119d4b3e15b075ec0b80d6f;p=firefly-linux-kernel-4.4.55.git diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index cc093a482aa4..b931379811ac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -45,6 +45,9 @@ #include #include #include +#include +#include +#include / { compatible = "rockchip,rk3368"; @@ -53,6 +56,7 @@ #size-cells = <2>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -123,6 +127,10 @@ reg = <0x0 0x0>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster1_opp>; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_l1: cpu@1 { @@ -131,6 +139,8 @@ reg = <0x0 0x1>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster1_opp>; }; cpu_l2: cpu@2 { @@ -139,6 +149,8 @@ reg = <0x0 0x2>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster1_opp>; }; cpu_l3: cpu@3 { @@ -147,6 +159,8 @@ reg = <0x0 0x3>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKL>; + operating-points-v2 = <&cluster1_opp>; }; cpu_b0: cpu@100 { @@ -155,6 +169,10 @@ reg = <0x0 0x100>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + operating-points-v2 = <&cluster0_opp>; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b1: cpu@101 { @@ -163,6 +181,8 @@ reg = <0x0 0x101>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + operating-points-v2 = <&cluster0_opp>; }; cpu_b2: cpu@102 { @@ -171,6 +191,8 @@ reg = <0x0 0x102>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + operating-points-v2 = <&cluster0_opp>; }; cpu_b3: cpu@103 { @@ -179,6 +201,60 @@ reg = <0x0 0x103>; cpu-idle-states = <&cpu_sleep>; enable-method = "psci"; + clocks = <&cru ARMCLKB>; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1200000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1200000>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000>; + }; + opp@816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1200000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000>; }; }; @@ -197,6 +273,37 @@ <&cpu_b2>, <&cpu_b3>; }; + amba { + compatible = "arm,amba-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC_PERI>; + clock-names = "apb_pclk"; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; + }; + + dmac_bus: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC_BUS>; + clock-names = "apb_pclk"; + arm,pl330-broken-no-flushp; + peripherals-req-type-burst; + }; + }; + psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -221,12 +328,13 @@ #clock-cells = <0>; }; - sdmmc: dwmmc@ff0c0000 { + sdmmc: rksdmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; status = "disabled"; @@ -244,12 +352,13 @@ status = "disabled"; }; - emmc: dwmmc@ff0f0000 { + emmc: rksdmmc@ff0f0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0f0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = ; status = "disabled"; @@ -262,6 +371,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -304,16 +415,29 @@ status = "disabled"; }; - i2c1: i2c@ff140000 { + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + clocks = <&cru PCLK_I2C0>; + clock-names = "i2c"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff140000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff140000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; + clocks = <&cru PCLK_I2C2>; pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; + pinctrl-0 = <&i2c2_xfer>; status = "disabled"; }; @@ -404,6 +528,91 @@ status = "disabled"; }; + thermal-zones { + cpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <115000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3368-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + gmac: ethernet@ff290000 { compatible = "rockchip,rk3368-gmac"; reg = <0x0 0xff290000 0x0 0x10000>; @@ -421,6 +630,16 @@ status = "disabled"; }; + nandc0: nandc@ff400000 { + compatible = "rockchip,rk-nandc"; + reg = <0x0 0xff400000 0x0 0x4000>; + interrupts = ; + nandc_id = <0>; + clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>; + clock-names = "clk_nandc", "hclk_nandc"; + status = "disabled"; + }; + usb_host0_ehci: usb@ff500000 { compatible = "generic-ehci"; reg = <0x0 0xff500000 0x0 0x100>; @@ -445,29 +664,63 @@ status = "disabled"; }; - i2c0: i2c@ff650000 { - compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; - reg = <0x0 0xff650000 0x0 0x1000>; - clocks = <&cru PCLK_I2C0>; - clock-names = "i2c"; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + ddrpctl: syscon@ff610000 { + compatible = "rockchip,rk3368-ddrpctl", "syscon"; + reg = <0x0 0xff610000 0x0 0x400>; }; - i2c2: i2c@ff660000 { + i2c1: i2c@ff660000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff660000 0x0 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; + clocks = <&cru PCLK_I2C1>; pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; status = "disabled"; }; @@ -484,9 +737,127 @@ status = "disabled"; }; + mbox: mbox@ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0x0 0xff6b0000 0x0 0x1000>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + }; + + pmu: power-management@ff730000 { + compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff730000 0x0 0x1000>; + + power: power-controller { + status = "disabled"; + compatible = "rockchip,rk3368-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Note: Although SCLK_* are the working clocks + * of device without including on the NOC, needed for + * synchronous reset. + * + * The clocks on the which NOC: + * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. + * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. + * ACLK_RGA is on ACLK_RGA_NIU. + * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. + * + * Which clock are device clocks: + * clocks devices + * *_IEP IEP:Image Enhancement Processor + * *_ISP ISP:Image Signal Processing + * *_VIP VIP:Video Input Processor + * *_VOP* VOP:Visual Output Processor + * *_RGA RGA + * *_EDP* EDP + * *_DPHY* LVDS + * *_HDMI HDMI + * *_MIPI_* MIPI + */ + pd_vio { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_VIP>, + <&cru ACLK_RGA>, + <&cru ACLK_VOP>, + <&cru ACLK_VOP_IEP>, + <&cru DCLK_VOP>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP>, + <&cru HCLK_VIO_HDCPMMU>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_HDCP>, + <&cru PCLK_ISP>, + <&cru PCLK_VIP>, + <&cru PCLK_DPHYRX>, + <&cru PCLK_DPHYTX0>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_VOP0_PWM>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_HDCP>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>, + <&cru SCLK_HDMI_CEC>, + <&cru SCLK_HDMI_HDCP>; + }; + /* + * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC + * (video endecoder & decoder) clocks that on the + * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). + */ + pd_video { + reg = ; + clocks = <&cru ACLK_VIDEO>, + <&cru HCLK_VIDEO>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>; + }; + /* + * Note: ACLK_GPU is the GPU clock, + * and on the ACLK_GPU_NIU (NOC). + */ + pd_gpu_1 { + reg = ; + clocks = <&cru ACLK_GPU_CFG>, + <&cru ACLK_GPU_MEM>, + <&cru SCLK_GPU_CORE>; + }; + }; + }; + pmugrf: syscon@ff738000 { - compatible = "rockchip,rk3368-pmugrf", "syscon"; + compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xff738000 0x0 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3368-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; cru: clock-controller@ff760000 { @@ -495,11 +866,28 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_BUS>, <&cru ACLK_PERI>, + <&cru HCLK_BUS>, <&cru HCLK_PERI>, + <&cru PCLK_BUS>, <&cru PCLK_PERI>; + assigned-clock-rates = + <576000000>, <400000000>, + <1188000000>, + <300000000>, <300000000>, + <150000000>, <150000000>, + <75000000>, <75000000>; }; grf: syscon@ff770000 { - compatible = "rockchip,rk3368-grf", "syscon"; + compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x1000>; + + io_domains: io-domains { + compatible = "rockchip,rk3368-io-voltage-domain"; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { @@ -510,6 +898,36 @@ status = "disabled"; }; + timer@ff810000 { + compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; + }; + + i2s_2ch: i2s-2ch@ff890000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac_bus 6>, <&dmac_bus 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; + status = "disabled"; + }; + + i2s_8ch: i2s-8ch@ff898000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff898000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_bus>; + status = "disabled"; + }; + gic: interrupt-controller@ffb71000 { compatible = "arm,gic-400"; interrupt-controller; @@ -517,13 +935,35 @@ #address-cells = <0>; reg = <0x0 0xffb71000 0x0 0x1000>, - <0x0 0xffb72000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x2000>, <0x0 0xffb74000 0x0 0x2000>, <0x0 0xffb76000 0x0 0x2000>; interrupts = ; }; + gpu: rogue-g6110@ffa30000 { + compatible = "arm,rogue-G6110", "arm,rk3368-gpu"; + reg = <0x0 0xffa30000 0x0 0x10000>; + clocks = + <&cru SCLK_GPU_CORE>, + <&cru ACLK_GPU_MEM>, + <&cru ACLK_GPU_CFG>; + clock-names = + "sclk_gpu_core", + "aclk_gpu_mem", + "aclk_gpu_cfg"; + operating-points = < + /* KHz uV */ + 200000 1100000 + 288000 1100000 + 400000 1150000 + 576000 1200000 + >; + interrupts = ; + interrupt-names = "rogue-g6110-irq"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3368-pinctrl"; rockchip,grf = <&grf>; @@ -712,6 +1152,42 @@ }; }; + i2s { + i2s_8ch_bus: i2s-8ch-bus { + rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>, + <2 13 RK_FUNC_1 &pcfg_pull_none>, + <2 14 RK_FUNC_1 &pcfg_pull_none>, + <2 15 RK_FUNC_1 &pcfg_pull_none>, + <2 16 RK_FUNC_1 &pcfg_pull_none>, + <2 17 RK_FUNC_1 &pcfg_pull_none>, + <2 18 RK_FUNC_1 &pcfg_pull_none>, + <2 19 RK_FUNC_1 &pcfg_pull_none>, + <2 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>; + }; + + vop_pwm_pin: vop-pwm { + rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + sdio0 { sdio0_bus1: sdio0-bus1 { rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>; @@ -762,7 +1238,7 @@ rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>; }; - sdmmc_cd: sdmcc-cd { + sdmmc_cd: sdmmc-cd { rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>; }; @@ -829,6 +1305,16 @@ }; }; + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,