X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3368-tb-sheep.dts;h=e1a17f0a4a8da3c1791758c87a5ec679ca640fc5;hb=166ce57b57dd71e86bc70c7135dd8ef870dae126;hp=b45d2c540f0713882d12b92bfe217771ec1d50a5;hpb=cc754b8c11f42e70f593e9f755c9eadad734ce8b;p=firefly-linux-kernel-4.4.55.git

diff --git a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
index b45d2c540f07..e1a17f0a4a8d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-tb-sheep.dts
@@ -46,6 +46,40 @@
 / {
 	model = "Rockchip Sheep board";
 	compatible = "rockchip,sheep", "rockchip,rk3368";
+
+	dwc_control_usb: dwc-control-usb {
+		compatible = "rockchip,rk3368-dwc-control-usb";
+		rockchip,grf = <&grf>;
+		grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "otg_id", "otg_bvalid",
+				  "otg_linestate", "host0_linestate";
+		clocks = <&cru HCLK_USB_PERI>, <&cru SCLK_USBPHY480M>;
+		clock-names = "hclk_usb_peri", "usbphy_480m";
+
+		usb_bc {
+			compatible = "inno,phy";
+			regbase = &dwc_control_usb;
+			rk_usb,bvalid     = <0x4bc 23 1>;
+			rk_usb,iddig      = <0x4bc 26 1>;
+			rk_usb,vdmsrcen   = <0x718 12 1>;
+			rk_usb,vdpsrcen   = <0x718 11 1>;
+			rk_usb,rdmpden    = <0x718 10 1>;
+			rk_usb,idpsrcen   = <0x718  9 1>;
+			rk_usb,idmsinken  = <0x718  8 1>;
+			rk_usb,idpsinken  = <0x718  7 1>;
+			rk_usb,dpattach   = <0x4b8 31 1>;
+			rk_usb,cpdet      = <0x4b8 30 1>;
+			rk_usb,dcpattach  = <0x4b8 29 1>;
+		};
+	};
+};
+
+&rt5640 {
+	status = "okay";
 };
 
 &gt9xx {
@@ -68,3 +102,63 @@
 &rk_key {
 	status = "okay";
 };
+
+&rk818 {
+	status = "okay";
+};
+
+&cpu_l0 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_l1 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_l2 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_l3 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_b0 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_b1 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_b2 {
+	cpu-supply = <&syr827>;
+};
+
+&cpu_b3 {
+	cpu-supply = <&syr827>;
+};
+
+&gpu {
+	logic-supply = <&vdd_logic>;
+};
+
+&dwc_control_usb {
+	host_drv_gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
+	otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
+
+	rockchip,remote_wakeup;
+	rockchip,usb_irq_wakeup;
+};
+
+&usb_otg {
+	clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
+	clock-names = "sclk_otgphy0", "otg";
+	resets = <&cru SRST_USBOTG_AHB>,
+		 <&cru SRST_USBOTG_PHY>,
+		 <&cru SRST_USBOTG_CON>;
+	reset-names = "otg_ahb", "otg_phy", "otg_controller";
+	/* 0 - Normal, 1 - Force Host, 2 - Force Device */
+	rockchip,usb-mode = <0>;
+	status = "okay";
+};