X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;f=arch%2Farm64%2Fboot%2Fdts%2Frockchip%2Frk3366.dtsi;h=acabb1de45385bc8a88d8f8c4afcac402ebebed7;hb=927b5a2bd7e0ca06412cd3536e48b2a89bff0dfc;hp=a315e104f5ed317016b3174ab97006540fe75ec5;hpb=debb2d340f7a5a5502bc5d1a5da23545be3d912d;p=firefly-linux-kernel-4.4.55.git

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index a315e104f5ed..acabb1de4538 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -45,6 +45,9 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/display/rk_fb.h>
+#include <dt-bindings/power/rk3366-power.h>
+#include <dt-bindings/soc/rockchip_boot-mode.h>
 
 / {
 	compatible = "rockchip,rk3366";
@@ -75,6 +78,8 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			clocks = <&cru ARMCLK>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu1: cpu@1 {
@@ -82,6 +87,7 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x1>;
 			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu2: cpu@2 {
@@ -89,6 +95,7 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x2>;
 			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu3: cpu@3 {
@@ -96,6 +103,39 @@
 			compatible = "arm,cortex-a53","arm,armv8";
 			reg = <0x0 0x3>;
 			enable-method = "psci";
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <950000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1000000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1075000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1175000>;
+		};
+		opp05 {
+			opp-hz = /bits/ 64 <1296000000>;
+			opp-microvolt = <1250000>;
 		};
 	};
 
@@ -106,16 +146,22 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <
-				GIC_PPI 13
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-				<GIC_PPI 14
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-				<GIC_PPI 11
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
-				<GIC_PPI 10
-			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		clock-frequency = <24000000>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
 	};
 
 	xin24m: xin24m {
@@ -185,6 +231,74 @@
 		status = "disabled";
 	};
 
+	scr: rkscr@ff1d0000 {
+		compatible = "rockchip-scr";
+		reg = <0x0 0xff1d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
+		clocks = <&cru PCLK_SIM>;
+		clock-names = "g_pclk_sim_card";
+		status = "disabled";
+	};
+
+	sdmmc: rksdmmc@ff400000 {
+		compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
+		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0xff400000 0x0 0x4000>;
+		status = "disabled";
+	};
+
+	sdio: rksdmmc@ff410000 {
+		compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
+		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
+			 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0xff410000 0x0 0x4000>;
+		status = "disabled";
+	};
+
+	emmc: rksdmmc@ff420000 {
+		compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
+		clock-freq-min-max = <400000 150000000>;
+		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0xff420000 0x0 0x4000>;
+		status = "disabled";
+	};
+
+	gmac: eth@ff440000 {
+		compatible = "rockchip,rk3366-gmac";
+		reg = <0x0 0xff440000 0x0 0x10000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "macirq";
+		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+			 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
+			 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
+			 <&cru PCLK_GMAC>;
+		clock-names = "stmmaceth", "mac_clk_rx",
+			      "mac_clk_tx", "clk_mac_ref",
+			      "clk_mac_refout", "aclk_mac",
+			      "pclk_mac";
+		resets = <&cru SRST_MAC>;
+		reset-names = "stmmaceth";
+		status = "disabled";
+	};
+
 	i2c0: i2c@ff650000 {
 		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 		reg = <0x0 0xff728000 0x0 0x1000>;
@@ -278,6 +392,60 @@
 		status = "disabled";
 	};
 
+	usbphy: phy {
+		compatible = "rockchip,rk336x-usb-phy";
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		usbphy0: usb-phy0 {
+			#phy-cells = <0>;
+			#clock-cells = <0>;
+			reg = <0x700>;
+		};
+
+		usbphy1: usb-phy1 {
+			#phy-cells = <0>;
+			#clock-cells = <0>;
+			reg = <0x728>;
+		};
+	};
+
+	usb_host0_echi: usb@ff480000 {
+		compatible = "generic-ehci";
+		reg = <0x0 0xff480000 0x0 0x20000>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+		clock-names = "sclk_otgphy0", "hclk_host0";
+		phys = <&usbphy1>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@ff4a0000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xff4a0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
+		clock-names = "sclk_otgphy0", "hclk_host0";
+		status = "disabled";
+	};
+
+	usb_otg: usb@ff4c0000 {
+		compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
+			     "snps,dwc2";
+		reg = <0x0 0xff4c0000 0x0 0x40000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_OTG>;
+		clock-names = "otg";
+		dr_mode = "otg";
+		g-np-tx-fifo-size = <16>;
+		g-rx-fifo-size = <275>;
+		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-use-dma;
+		status = "disabled";
+	};
+
 	i2c1: i2c@ff660000 {
 		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 		reg = <0x0 0xff660000 0x0 0x1000>;
@@ -346,9 +514,122 @@
 		status = "disabled";
 	};
 
+	pmu: power-management@ff730000 {
+		compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
+		reg = <0x0 0xff730000 0x0 0x1000>;
+
+		power: power-controller {
+			status = "disabled";
+			compatible = "rockchip,rk3366-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/*
+			 * Note: Although SCLK_* are the working clocks
+			 * of device without including on the NOC, needed for
+			 * synchronous reset.
+			 *
+			 * The clocks on the which NOC:
+			 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
+			 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
+			 * ACLK_ISP is on ACLK_ISP_NIU.
+			 * ACLK_HDCP is on ACLK_HDCP_NIU.
+			 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+			 *
+			 * Which clock are device clocks:
+			 *	clocks		devices
+			 *	*_IEP		IEP:Image Enhancement Processor
+			 *	*_ISP		ISP:Image Signal Processing
+			 *	*_VOP*		VOP:Visual Output Processor
+			 *	*_RGA		RGA
+			 *	*_DPHY*		LVDS
+			 *	*_HDMI		HDMI
+			 *	*_MIPI_*	MIPI
+			 */
+			pd_vio {
+				reg = <RK3366_PD_VIO>;
+				clocks = <&cru ACLK_IEP>,
+					 <&cru ACLK_ISP>,
+					 <&cru ACLK_RGA>,
+					 <&cru ACLK_HDCP>,
+					 <&cru ACLK_VOP_FULL>,
+					 <&cru ACLK_VOP_LITE>,
+					 <&cru ACLK_VOP_IEP>,
+					 <&cru DCLK_VOP_FULL>,
+					 <&cru DCLK_VOP_LITE>,
+					 <&cru HCLK_IEP>,
+					 <&cru HCLK_ISP>,
+					 <&cru HCLK_RGA>,
+					 <&cru HCLK_VOP_FULL>,
+					 <&cru HCLK_VOP_LITE>,
+					 <&cru HCLK_VIO_HDCPMMU>,
+					 <&cru PCLK_HDMI_CTRL>,
+					 <&cru PCLK_HDCP>,
+					 <&cru PCLK_MIPI_DSI0>,
+					 <&cru SCLK_VOP_FULL_PWM>,
+					 <&cru SCLK_HDCP>,
+					 <&cru SCLK_ISP>,
+					 <&cru SCLK_RGA>,
+					 <&cru SCLK_HDMI_CEC>,
+					 <&cru SCLK_HDMI_HDCP>;
+			};
+
+			/*
+			 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
+			 * (video endecoder & decoder) clocks that on the
+			 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+			 */
+			pd_vpu {
+				reg = <RK3366_PD_VPU>;
+				clocks = <&cru ACLK_VIDEO>,
+					 <&cru HCLK_VIDEO>;
+			};
+
+			/*
+			 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
+			 * (video decoder) clocks that on the
+			 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
+			 */
+			pd_rkvdec {
+				reg = <RK3366_PD_RKVDEC>;
+				clocks = <&cru ACLK_RKVDEC>,
+					 <&cru HCLK_RKVDEC>;
+			};
+
+			pd_video {
+				reg = <RK3366_PD_VIDEO>;
+				clocks = <&cru ACLK_VIDEO>,
+					 <&cru ACLK_RKVDEC>,
+					 <&cru HCLK_VIDEO>,
+					 <&cru HCLK_RKVDEC>,
+					 <&cru SCLK_HEVC_CABAC>,
+					 <&cru SCLK_HEVC_CORE>;
+			};
+
+			/*
+			 * Note: ACLK_GPU is the GPU clock,
+			 * and on the ACLK_GPU_NIU (NOC).
+			 */
+			pd_gpu {
+				reg = <RK3366_PD_GPU>;
+				clocks = <&cru ACLK_GPU>;
+			};
+		};
+	};
+
 	pmugrf: syscon@ff738000 {
-		compatible = "rockchip,rk3366-pmugrf", "syscon";
+		compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 		reg = <0x0 0xff738000 0x0 0x1000>;
+
+		reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x200>;
+			mode-normal = <BOOT_NORMAL>;
+			mode-recovery = <BOOT_RECOVERY>;
+			mode-fastboot = <BOOT_FASTBOOT>;
+			mode-loader = <BOOT_LOADER>;
+		};
 	};
 
 	amba {
@@ -384,6 +665,29 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+		assigned-clocks =
+			<&cru SCLK_32K>,
+			<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
+			<&cru PLL_CPLL>, <&cru PLL_GPLL>,
+			<&cru PLL_NPLL>, <&cru PLL_MPLL>,
+			<&cru PLL_WPLL>, <&cru PLL_BPLL>,
+			<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
+			<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
+			<&cru ACLK_BUS>, <&cru ACLK_PERI0>,
+			<&cru ACLK_PERI1>;
+		assigned-clock-rates =
+			<0>,
+			<0>, <0>,
+			<750000000>, <576000000>,
+			<594000000>, <594000000>,
+			<960000000>, <520000000>,
+			<375000000>, <288000000>,
+			<100000000>, <100000000>,
+			<288000000>, <288000000>,
+			<144000000>;
+		assigned-clock-parents =
+			<&cru SCLK_32K_INTR>,
+			<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
 	};
 
 	grf: syscon@ff770000 {
@@ -391,8 +695,160 @@
 		reg = <0x0 0xff770000 0x0 0x1000>;
 	};
 
+	wdt: watchdog@ff800000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x0 0xff800000 0x0 0x100>;
+		clocks = <&cru PCLK_WDT>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	spdif: spdif@ff880000 {
+		compatible = "rockchip,rk3366-spdif";
+		reg = <0x0 0xff880000 0x0 0x1000>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 3>;
+		dma-names = "tx";
+		clock-names = "hclk", "mclk";
+		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spdif_bus>;
+		status = "disabled";
+	};
+
+	i2s_2ch: i2s-2ch@ff890000 {
+		compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff890000 0x0 0x1000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_hclk", "i2s_clk";
+		clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
+		status = "disabled";
+	};
+
+	i2s_8ch: i2s-8ch@ff898000 {
+		compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
+		reg = <0x0 0xff898000 0x0 0x1000>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+		dma-names = "tx", "rx";
+		clock-names = "i2s_hclk", "i2s_clk";
+		clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s_8ch_bus>;
+		status = "disabled";
+	};
+
+	fb: fb {
+		compatible = "rockchip,rk-fb";
+		rockchip,disp-mode = <DUAL>;
+		status = "disabled";
+	};
+
+	rk_screen: screen {
+		compatible = "rockchip,screen";
+		status = "disabled";
+	};
+
+	vop_lite: vop@ff8f0000 {
+		compatible = "rockchip,rk3366-lcdc-lite";
+		rockchip,grf = <&grf>;
+		rockchip,pwr18 = <0>;
+		rockchip,iommu-enabled = <1>;
+		reg = <0x0 0xff8f0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
+		clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+		resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
+		reset-names = "axi", "ahb", "dclk";
+		status = "disabled";
+	};
+
+	vopl_mmu: vopl-mmu {
+		dbgname = "vop";
+		compatible = "rockchip,vopl_mmu";
+		reg = <0x0 0xff8f0f00 0x0 0x100>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vopl_mmu";
+		status = "disabled";
+	};
+
+	iep: iep@ff900000 {
+		compatible = "rockchip,iep";
+		iommu_enabled = <1>;
+		reg = <0x0 0xff900000 0x0 0x800>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+		clock-names = "aclk_iep", "hclk_iep";
+		version = <2>;
+		status = "disabled";
+	};
+
+	rga: rga@ff920000 {
+		compatible = "rockchip,rga2";
+		dev_mode = <1>;
+		reg = <0x0 0xff920000 0x0 0x1000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
+		status = "disabled";
+	};
+
+	vop_big: vop@ff930000 {
+		compatible = "rockchip,rk3366-lcdc-big";
+		rockchip,grf = <&grf>;
+		rockchip,prop = <PRMRY>;
+		rockchip,pwr18 = <0>;
+		rockchip,iommu-enabled = <1>;
+		reg = <0x0 0xff930000 0x0 0x23f0>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
+		clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+		resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
+		reset-names = "axi", "ahb", "dclk";
+		status = "disabled";
+	};
+
+	vopb_mmu: vopb-mmu {
+		dbgname = "vop";
+		compatible = "rockchip,vopb_mmu";
+		reg = <0x0 0xff932400 0x0 0x100>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vop_mmu";
+		status = "disabled";
+	};
+
+	iep_mmu: iep-mmu {
+		dbgname = "iep";
+		compatible = "rockchip,iep_mmu";
+		reg = <0x0 0xff900800 0x0 0x100>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "iep_mmu";
+		status = "disabled";
+	};
+
+	vpu_mmu: vpu_mmu {
+		dbgname = "vpu";
+		compatible = "rockchip,vpu_mmu";
+		reg = <0x0 0xff9a0800 0x0 0x100>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vpu_mmu";
+		status = "disabled";
+	};
+
+	vdec_mmu: vdec_mmu {
+		dbgname = "vdec";
+		compatible = "rockchip,vdec_mmu";
+		reg = <0x0 0xff9b0480 0x0 0x40>,
+		      <0x0 0xff9b04c0 0x0 0x40>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vdec_mmu";
+		status = "disabled";
+	};
+
 	dsihost0: mipi@ff960000 {
-		compatible = "rockchip,rk3368-dsi";
+		compatible = "rockchip,rk3366-dsi";
 		rockchip,prop = <0>;
 		reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 		reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
@@ -402,6 +858,70 @@
 		status = "disabled";
 	};
 
+	lvds: lvds@ff968000 {
+		compatible = "rockchip,rk3366-lvds";
+		rockchip,grf = <&grf>;
+		reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
+		reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
+		clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
+		clock-names = "pclk_lvds", "pclk_lvds_ctl";
+		status = "disabled";
+	};
+
+	hdmi: hdmi@ff980000 {
+		compatible = "rockchip,rk3366-hdmi";
+		reg = <0x0 0xff980000 0x0 0x20000>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_HDMI_CTRL>,
+			 <&cru SCLK_HDMI_HDCP>,
+			 <&cru SCLK_HDMI_CEC>,
+			 <&cru DCLK_HDMIPHY>;
+		clock-names = "pclk_hdmi",
+			      "hdcp_clk_hdmi",
+			      "cec_clk_hdmi",
+			      "dclk_hdmi_phy";
+		resets = <&cru SRST_HDMI>;
+		reset-names = "hdmi";
+		pinctrl-names = "default", "gpio";
+		pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
+		pinctrl-1 = <&i2c5_gpio>;
+		status = "disabled";
+	};
+
+	vpu: vpu_service@ff9a0000 {
+		compatible = "rockchip,vpu_service";
+		rockchip,grf = <&grf>;
+		iommu_enabled = <1>;
+		reg = <0x0 0xff9a0000 0x0 0x800>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec", "irq_enc";
+		clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+		clock-names = "aclk_vcodec", "hclk_vcodec";
+		resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
+		reset-names = "video_h", "video_a";
+		name = "vpu_service";
+		dev_mode = <0>;
+		status = "disabled";
+	};
+
+	rkvdec: rkvdec@ff9b0000 {
+		compatible = "rockchip,rkvdec";
+		rockchip,grf = <&grf>;
+		iommu_enabled = <1>;
+		reg = <0x0 0xff9b0000 0x0 0x400>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec";
+		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
+		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+		resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
+		reset-names = "video_h", "video_a";
+		dev_mode = <2>;
+		name = "rkvdec";
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3366-pinctrl";
 		rockchip,grf = <&grf>;
@@ -547,6 +1067,83 @@
 			};
 		};
 
+		sdmmc {
+			sdmmc_cd: sdmmc-cd {
+				rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_bus1: sdmmc-bus1 {
+				rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_bus4: sdmmc-bus4 {
+				rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
+						<5 1 RK_FUNC_1 &pcfg_pull_up>,
+						<5 2 RK_FUNC_1 &pcfg_pull_up>,
+						<5 3 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdmmc_clk: sdmmc-clk {
+				rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			sdmmc_cmd: sdmmc-cmd {
+				rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
+			};
+		};
+
+		sdio {
+			sdio_bus1: sdio-bus1 {
+				rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio_bus4: sdio-bus4 {
+				rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
+						<3 13 RK_FUNC_1 &pcfg_pull_up>,
+						<3 14 RK_FUNC_1 &pcfg_pull_up>,
+						<3 15 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio_cmd: sdio-cmd {
+				rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio_clk: sdio-clk {
+				rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			sdio_cd: sdio-cd {
+				rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio_wp: sdio-wp {
+				rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio_int: sdio-int {
+				rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
+			};
+
+			sdio_pwr: sdio-pwr {
+				rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
+			};
+		};
+
+		hdmi_i2c {
+			hdmii2c_xfer: hdmii2c-xfer {
+				rockchip,pins =
+					<5 13 RK_FUNC_2 &pcfg_pull_none>,
+					<5 14 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+
+		hdmi_pin {
+			hdmi_cec: hdmi-cec {
+				rockchip,pins =
+					<5 12 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		i2c0 {
 			i2c0_xfer: i2c0-xfer {
 				rockchip,pins =
@@ -558,8 +1155,8 @@
 		i2c1 {
 			i2c1_xfer: i2c1-xfer {
 				rockchip,pins =
-					<4 19 RK_FUNC_1 &pcfg_pull_none>,
-					<4 20 RK_FUNC_1 &pcfg_pull_none>;
+					<4 25 RK_FUNC_1 &pcfg_pull_none>,
+					<4 26 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
 
@@ -569,6 +1166,12 @@
 					<5 15 RK_FUNC_2 &pcfg_pull_none>,
 					<5 16 RK_FUNC_2 &pcfg_pull_none>;
 			};
+
+			i2c2_gpio: i2c2-gpio {
+				rockchip,pins =
+					<5 15 RK_FUNC_GPIO &pcfg_pull_none>,
+					<5 16 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 		i2c3 {
@@ -585,6 +1188,12 @@
 					<5 8 RK_FUNC_1 &pcfg_pull_none>,
 					<5 9 RK_FUNC_1 &pcfg_pull_none>;
 			};
+
+			i2c4_gpio: i2c4-gpio {
+				rockchip,pins =
+					<5 8 RK_FUNC_GPIO &pcfg_pull_none>,
+					<5 9 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 		i2c5 {
@@ -593,6 +1202,11 @@
 					<5 13 RK_FUNC_1 &pcfg_pull_none>,
 					<5 14 RK_FUNC_1 &pcfg_pull_none>;
 			};
+			i2c5_gpio: i2c5-gpio {
+				rockchip,pins =
+					<5 13 RK_FUNC_GPIO &pcfg_pull_none>,
+					<5 14 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
 		};
 
 		i2s {
@@ -610,6 +1224,13 @@
 			};
 		};
 
+		spdif {
+			spdif_bus: spdif-bus {
+				rockchip,pins =
+					<5 19 RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
 		spi0 {
 			spi0_clk: spi0-clk {
 				rockchip,pins =
@@ -636,19 +1257,41 @@
 		spi1 {
 			spi1_clk: spi1-clk {
 				rockchip,pins =
-					<2 4 RK_FUNC_2 &pcfg_pull_up>;
+					<2 4 RK_FUNC_3 &pcfg_pull_up>;
 			};
 			spi1_cs0: spi1-cs0 {
 				rockchip,pins =
-					<2 5 RK_FUNC_2 &pcfg_pull_up>;
+					<2 5 RK_FUNC_3 &pcfg_pull_up>;
+			};
+			spi1_tx: spi1-tx {
+				rockchip,pins =
+					<2 6 RK_FUNC_3 &pcfg_pull_up>;
 			};
 			spi1_rx: spi1-rx {
 				rockchip,pins =
-					<2 6 RK_FUNC_2 &pcfg_pull_up>;
+					<2 7 RK_FUNC_3 &pcfg_pull_up>;
 			};
-			spi1_tx: spi1-tx {
+		};
+
+		scr {
+			scr_clk: scr-clk {
 				rockchip,pins =
-					<2 7 RK_FUNC_2 &pcfg_pull_up>;
+					<5 8 RK_FUNC_2 &pcfg_pull_none>;
+			};
+
+			scr_io: scr-io {
+				rockchip,pins =
+					<5 9 RK_FUNC_2 &pcfg_pull_up>;
+			};
+
+			scr_rst: scr-rst {
+				rockchip,pins =
+					<5 10 RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			scr_detect: scr-detect {
+				rockchip,pins =
+					<5 11 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
 
@@ -763,5 +1406,171 @@
 					<5 18 RK_FUNC_2 &pcfg_pull_none>;
 			};
 		};
+
+		lcdc {
+			lcdc_lcdc: lcdc-lcdc {
+				rockchip,pins =
+					<0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
+					<0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
+					<0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
+					<0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
+					<0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
+					<0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
+					<0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
+					<0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
+					<1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
+					<1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
+					<1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
+					<1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
+					<1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
+					<1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
+					<1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
+					<1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
+					<1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
+					<1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
+			};
+
+			lcdc_gpio: lcdc-gpio {
+				rockchip,pins =
+					<0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
+					<0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
+					<0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
+					<0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
+					<0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
+					<0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
+					<0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
+					<0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
+					<1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
+					<1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
+					<1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
+					<1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
+					<1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
+					<1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
+					<1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
+					<1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
+					<1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
+					<1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
+			};
+		};
+
+		gmac {
+			rgmii_pins: rgmii-pins {
+				rockchip,pins =
+					/* mac_rxd3 */
+					<2 7  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxd2 */
+					<2 6  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txd3 */
+					<2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
+					/* mac_txd2 */
+					<2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
+					/* mac_rxd1 */
+					<2 3  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxd0 */
+					<2 2  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txd1 */
+					<2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
+					/* mac_txd0 */
+					<2 0  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txclkout */
+					<2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
+					/* mac_crs */
+					/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
+					/* mac_rxclkin */
+					<2 14 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_mdio */
+					<2 13 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txen */
+					<2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
+					/* mac_clk */
+					<2 11 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxer */
+					/* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
+					/* mac_rxdv */
+					<2 9  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_mdc */
+					<2 8  RK_FUNC_1 &pcfg_pull_none>;
+			};
+
+			rmii_pins: rmii-pins {
+				rockchip,pins =
+					/* mac_rxd1 */
+					<2 3  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxd0 */
+					<2 2  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txd1 */
+					<2 1  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txd0 */
+					<2 0  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_crs */
+					/* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
+					/* mac_rxclkin */
+					<2 14 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_mdio */
+					<2 13 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_txen */
+					<2 12 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_clk */
+					<2 11 RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_rxer */
+					/* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
+					/* mac_rxdv */
+					<2 9  RK_FUNC_1 &pcfg_pull_none>,
+					/* mac_mdc */
+					<2 8  RK_FUNC_1 &pcfg_pull_none>;
+			};
+		};
+
+		eth_phy {
+			eth_phy_pwr: eth-phy-pwr {
+				rockchip,pins =
+					<0 25 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+		};
+	};
+
+	gpu: gpu@ffa30000 {
+		compatible = "arm,malit764",
+			     "arm,malit76x",
+			     "arm,malit7xx",
+			     "arm,mali-midgard";
+
+		reg = <0x0 0xffa30000 0 0x10000>;
+
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "GPU", "MMU", "JOB";
+
+		clocks = <&cru ACLK_GPU>;
+		clock-names = "clk_mali";
+		operating-points-v2 = <&gpu_opp_table>;
+		status = "disabled";
+	};
+
+	gpu_opp_table: gpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp00 {
+			opp-hz = /bits/ 64 <96000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <192000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp02 {
+			opp-hz = /bits/ 64 <288000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp03 {
+			opp-hz = /bits/ 64 <375000000>;
+			opp-microvolt = <1125000>;
+		};
+		opp04 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <1200000>;
+		};
 	};
 };