X-Git-Url: http://plrg.eecs.uci.edu/git/?a=blobdiff_plain;ds=sidebyside;f=lib%2FTarget%2FX86%2FX86InstrFormats.td;h=ded1d9033704131b5be03d22084fcc1b2f07e3a4;hb=93f81d9b33bf5f01c113b1558962a5112b987092;hp=dc92cb53cea8764a51a4ef2278f5a93aac93f7b8;hpb=a86bcfb565bdea5bd45634fd2139ac17172a3500;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index dc92cb53cea..ded1d903370 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -1,10 +1,10 @@ -//===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===// -// +//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// @@ -21,34 +21,48 @@ class Format val> { def Pseudo : Format<0>; def RawFrm : Format<1>; def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; -def MRMSrcMem : Format<6>; +def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>; +def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>; +def RawFrmDstSrc: Format<10>; def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; def MRM6r : Format<22>; def MRM7r : Format<23>; def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; def MRM6m : Format<30>; def MRM7m : Format<31>; -def MRMInitReg : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>; def MRM_C9 : Format<38>; -def MRM_E8 : Format<39>; -def MRM_F0 : Format<40>; -def MRM_F8 : Format<41>; -def MRM_F9 : Format<42>; +def MRM_CA : Format<39>; +def MRM_CB : Format<40>; +def MRM_E8 : Format<41>; +def MRM_F0 : Format<42>; def RawFrmImm8 : Format<43>; def RawFrmImm16 : Format<44>; -def MRM_D0 : Format<45>; -def MRM_D1 : Format<46>; +def MRM_F8 : Format<45>; +def MRM_F9 : Format<46>; +def MRM_D0 : Format<47>; +def MRM_D1 : Format<48>; +def MRM_D4 : Format<49>; +def MRM_D5 : Format<50>; +def MRM_D6 : Format<51>; +def MRM_D8 : Format<52>; +def MRM_D9 : Format<53>; +def MRM_DA : Format<54>; +def MRM_DB : Format<55>; +def MRM_DC : Format<56>; +def MRM_DD : Format<57>; +def MRM_DE : Format<58>; +def MRM_DF : Format<59>; // ImmType - This specifies the immediate type used by an instruction. This is // part of the ad-hoc solution used to emit machine instruction encodings by our // machine code emitter. -class ImmType val> { - bits<3> Value = val; +class ImmType val> { + bits<4> Value = val; } def NoImm : ImmType<0>; def Imm8 : ImmType<1>; @@ -57,7 +71,8 @@ def Imm16 : ImmType<3>; def Imm16PCRel : ImmType<4>; def Imm32 : ImmType<5>; def Imm32PCRel : ImmType<6>; -def Imm64 : ImmType<7>; +def Imm32S : ImmType<7>; +def Imm64 : ImmType<8>; // FPFormat - This specifies what form this FP instruction has. This is used by // the Floating-Point stackifier pass. @@ -83,14 +98,27 @@ def SSEPackedSingle : Domain<1>; def SSEPackedDouble : Domain<2>; def SSEPackedInt : Domain<3>; +// Class specifying the vector form of the decompressed +// displacement of 8-bit. +class CD8VForm val> { + bits<3> Value = val; +} +def CD8VF : CD8VForm<0>; // v := VL +def CD8VH : CD8VForm<1>; // v := VL/2 +def CD8VQ : CD8VForm<2>; // v := VL/4 +def CD8VO : CD8VForm<3>; // v := VL/8 +def CD8VT1 : CD8VForm<4>; // v := 1 +def CD8VT2 : CD8VForm<5>; // v := 2 +def CD8VT4 : CD8VForm<6>; // v := 4 +def CD8VT8 : CD8VForm<7>; // v := 8 + // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize { bit hasOpSizePrefix = 1; } +class OpSize16 { bit hasOpSize16Prefix = 1; } class AdSize { bit hasAdSizePrefix = 1; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } -class SegFS { bits<2> SegOvrBits = 1; } -class SegGS { bits<2> SegOvrBits = 2; } class TB { bits<5> Prefix = 1; } class REP { bits<5> Prefix = 2; } class D8 { bits<5> Prefix = 3; } @@ -112,6 +140,10 @@ class T8XS { bits<5> Prefix = 18; } class TAXD { bits<5> Prefix = 19; } class XOP8 { bits<5> Prefix = 20; } class XOP9 { bits<5> Prefix = 21; } +class XOPA { bits<5> Prefix = 22; } +class PD { bits<5> Prefix = 23; } +class T8PD { bits<5> Prefix = 24; } +class TAPD { bits<5> Prefix = 25; } class VEX { bit hasVEXPrefix = 1; } class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } @@ -119,11 +151,27 @@ class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; } class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; } class VEX_L { bit hasVEX_L = 1; } class VEX_LIG { bit ignoresVEX_L = 1; } +class EVEX : VEX { bit hasEVEXPrefix = 1; } +class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; } +class EVEX_K { bit hasEVEX_K = 1; } +class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } +class EVEX_B { bit hasEVEX_B = 1; } +class EVEX_RC { bit hasEVEX_RC = 1; } +class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } +class EVEX_CD8 { + bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00, + !if(!eq(esize, 16), 0b01, + !if(!eq(esize, 32), 0b10, + !if(!eq(esize, 64), 0b11, ?)))); + bits<3> EVEX_CD8V = form.Value; +} class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; } class MemOp4 { bit hasMemOp4Prefix = 1; } class XOP { bit hasXOP_Prefix = 1; } class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, - string AsmStr, Domain d = GenericDomain> + string AsmStr, + InstrItinClass itin, + Domain d = GenericDomain> : Instruction { let Namespace = "X86"; @@ -139,17 +187,23 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, // If this is a pseudo instruction, mark it isCodeGenOnly. let isCodeGenOnly = !eq(!cast(f), "Pseudo"); + let Itinerary = itin; + // // Attributes specific to X86 instructions... // + bit ForceDisassemble = 0; // Force instruction to disassemble even though it's + // isCodeGenonly. Needed to hide an ambiguous + // AsmString from the parser, but still disassemble. + bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? + bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode? bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? bits<5> Prefix = 0; // Which prefix byte does this inst have? bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix? FPFormat FPForm = NotFP; // What flavor of FP instruction is this? bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? - bits<2> SegOvrBits = 0; // Segment override prefix. Domain ExeDomain = d; bit hasVEXPrefix = 0; // Does this inst require a VEX prefix? bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field? @@ -160,20 +214,28 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, // to be encoded in a immediate field? bit hasVEX_L = 0; // Does this inst use large (256-bit) registers? bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit + bit hasEVEXPrefix = 0; // Does this inst require EVEX form? + bit hasEVEX_K = 0; // Does this inst require masking? + bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field? + bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field? + bit hasEVEX_B = 0; // Does this inst set the EVEX_B field? + bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size. + bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width. bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding? bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix? + bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction. // TSFlags layout should be kept in sync with X86InstrInfo.h. let TSFlags{5-0} = FormBits; let TSFlags{6} = hasOpSizePrefix; - let TSFlags{7} = hasAdSizePrefix; - let TSFlags{12-8} = Prefix; - let TSFlags{13} = hasREX_WPrefix; - let TSFlags{16-14} = ImmT.Value; - let TSFlags{19-17} = FPForm.Value; - let TSFlags{20} = hasLockPrefix; - let TSFlags{22-21} = SegOvrBits; + let TSFlags{7} = hasOpSize16Prefix; + let TSFlags{8} = hasAdSizePrefix; + let TSFlags{13-9} = Prefix; + let TSFlags{14} = hasREX_WPrefix; + let TSFlags{18-15} = ImmT.Value; + let TSFlags{21-19} = FPForm.Value; + let TSFlags{22} = hasLockPrefix; let TSFlags{24-23} = ExeDomain.Value; let TSFlags{32-25} = Opcode; let TSFlags{33} = hasVEXPrefix; @@ -183,69 +245,87 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, let TSFlags{37} = hasVEX_i8ImmReg; let TSFlags{38} = hasVEX_L; let TSFlags{39} = ignoresVEX_L; - let TSFlags{40} = has3DNow0F0FOpcode; - let TSFlags{41} = hasMemOp4Prefix; - let TSFlags{42} = hasXOP_Prefix; + let TSFlags{40} = hasEVEXPrefix; + let TSFlags{41} = hasEVEX_K; + let TSFlags{42} = hasEVEX_Z; + let TSFlags{43} = hasEVEX_L2; + let TSFlags{44} = hasEVEX_B; + let TSFlags{46-45} = EVEX_CD8E; + let TSFlags{49-47} = EVEX_CD8V; + let TSFlags{50} = has3DNow0F0FOpcode; + let TSFlags{51} = hasMemOp4Prefix; + let TSFlags{52} = hasXOP_Prefix; + let TSFlags{53} = hasEVEX_RC; } class PseudoI pattern> - : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { + : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> { let Pattern = pattern; } class I o, Format f, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary, + Domain d = GenericDomain> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii8 o, Format f, dag outs, dag ins, string asm, - list pattern, Domain d = GenericDomain> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary, + Domain d = GenericDomain> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii8PCRel o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii16 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii32 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { + let Pattern = pattern; + let CodeSize = 3; +} +class Ii32S o, Format f, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii16PCRel o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii32PCRel o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } // FPStack Instruction Templates: // FPI - Floating Point Instruction template. -class FPI o, Format F, dag outs, dag ins, string asm> - : I {} +class FPI o, Format F, dag outs, dag ins, string asm, + InstrItinClass itin = NoItinerary> + : I {} // FpI_ - Floating Point Pseudo Instruction template. Not Predicated. -class FpI_ pattern> - : X86Inst<0, Pseudo, NoImm, outs, ins, ""> { +class FpI_ pattern, + InstrItinClass itin = NoItinerary> + : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> { let FPForm = fp; let Pattern = pattern; } @@ -257,22 +337,32 @@ class FpI_ pattern> // Iseg32 - 16-bit segment selector, 32-bit offset class Iseg16 o, Format f, dag outs, dag ins, string asm, - list pattern> : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Iseg32 o, Format f, dag outs, dag ins, string asm, - list pattern> : X86Inst { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } +def __xs : XS; +def __xd : XD; +def __pd : PD; + // SI - SSE 1 & 2 scalar instructions -class SI o, Format F, dag outs, dag ins, string asm, list pattern> - : I { - let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], - !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2])); +class SI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I { + let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512], + !if(hasVEXPrefix /* VEX */, [UseAVX], + !if(!eq(Prefix, __xs.Prefix), [UseSSE1], + !if(!eq(Prefix, __xd.Prefix), [UseSSE2], + !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1]))))); // AVX instructions have a 'v' prefix in the mnemonic let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); @@ -280,10 +370,11 @@ class SI o, Format F, dag outs, dag ins, string asm, list pattern> // SIi8 - SSE 1 & 2 scalar instructions class SIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8 { - let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], - !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2])); + list pattern, InstrItinClass itin = NoItinerary> + : Ii8 { + let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512], + !if(hasVEXPrefix /* VEX */, [UseAVX], + !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]))); // AVX instructions have a 'v' prefix in the mnemonic let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); @@ -291,24 +382,33 @@ class SIi8 o, Format F, dag outs, dag ins, string asm, // PI - SSE 1 & 2 packed instructions class PI o, Format F, dag outs, dag ins, string asm, list pattern, - Domain d> - : I { - let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], - !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1])); + InstrItinClass itin, Domain d> + : I { + let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512], + !if(hasVEXPrefix /* VEX */, [HasAVX], + !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1]))); // AVX instructions have a 'v' prefix in the mnemonic let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); } +// MMXPI - SSE 1 & 2 packed instructions with MMX operands +class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, + InstrItinClass itin, Domain d> + : I { + let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]); +} + // PIi8 - SSE 1 & 2 packed instructions with immediate class PIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d> - : Ii8 { - let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX], - !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1])); + list pattern, InstrItinClass itin, Domain d> + : Ii8 { + let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512], + !if(hasVEXPrefix /* VEX */, [HasAVX], + !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1]))); // AVX instructions have a 'v' prefix in the mnemonic - let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm); + let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm); } // SSE1 Instruction Templates: @@ -317,98 +417,141 @@ class PIi8 o, Format F, dag outs, dag ins, string asm, // PSI - SSE1 instructions with TB prefix. // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. // VSSI - SSE1 instructions with XS prefix in AVX form. -// VPSI - SSE1 instructions with TB prefix in AVX form. +// VPSI - SSE1 instructions with TB prefix in AVX form, packed single. -class SSI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, XS, Requires<[HasSSE1]>; +class SSI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, XS, Requires<[UseSSE1]>; class SSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[HasSSE1]>; -class PSI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, - Requires<[HasSSE1]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XS, Requires<[UseSSE1]>; +class PSI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, + Requires<[UseSSE1]>; class PSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TB, - Requires<[HasSSE1]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TB, + Requires<[UseSSE1]>; class VSSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, + list pattern, InstrItinClass itin = NoItinerary> + : I, XS, Requires<[HasAVX]>; class VPSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, TB, + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, Requires<[HasAVX]>; // SSE2 Instruction Templates: // // SDI - SSE2 instructions with XD prefix. // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. +// S2SI - SSE2 instructions with XS prefix. // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. -// PDI - SSE2 instructions with TB and OpSize prefixes. -// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. -// VSDI - SSE2 instructions with XD prefix in AVX form. -// VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form. - -class SDI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, XD, Requires<[HasSSE2]>; +// PDI - SSE2 instructions with PD prefix, packed double domain. +// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. +// VSDI - SSE2 scalar instructions with XD prefix in AVX form. +// VPDI - SSE2 vector instructions with PD prefix in AVX form, +// packed double domain. +// VS2I - SSE2 scalar instructions with PD prefix in AVX form. +// S2I - SSE2 scalar instructions with PD prefix. +// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as +// MMX operands. +// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as +// MMX operands. + +class SDI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, XD, Requires<[UseSSE2]>; class SDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XD, Requires<[HasSSE2]>; -class SSDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[HasSSE2]>; -class PDI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, OpSize, - Requires<[HasSSE2]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XD, Requires<[UseSSE2]>; +class S2SI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, XS, Requires<[UseSSE2]>; +class S2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XS, Requires<[UseSSE2]>; +class PDI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, + Requires<[UseSSE2]>; class PDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TB, OpSize, - Requires<[HasSSE2]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, PD, + Requires<[UseSSE2]>; class VSDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XD, + list pattern, InstrItinClass itin = NoItinerary> + : I, XD, + Requires<[UseAVX]>; +class VS2SI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, XS, Requires<[HasAVX]>; class VPDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, TB, - OpSize, Requires<[HasAVX]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, + PD, Requires<[HasAVX]>; +class VS2I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, + Requires<[UseAVX]>; +class S2I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, Requires<[UseSSE2]>; +class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XD, Requires<[HasSSE2]>; +class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XS, Requires<[HasSSE2]>; // SSE3 Instruction Templates: // -// S3I - SSE3 instructions with TB and OpSize prefixes. +// S3I - SSE3 instructions with PD prefixes. // S3SI - SSE3 instructions with XS prefix. // S3DI - SSE3 instructions with XD prefix. class S3SI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XS, - Requires<[HasSSE3]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, XS, + Requires<[UseSSE3]>; class S3DI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, XD, - Requires<[HasSSE3]>; -class S3I o, Format F, dag outs, dag ins, string asm, list pattern> - : I, TB, OpSize, - Requires<[HasSSE3]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, XD, + Requires<[UseSSE3]>; +class S3I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, + Requires<[UseSSE3]>; // SSSE3 Instruction Templates: // // SS38I - SSSE3 instructions with T8 prefix. // SS3AI - SSSE3 instructions with TA prefix. +// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. +// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. // // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version -// uses the MMX registers. We put those instructions here because they better -// fit into the SSSE3 instruction category rather than the MMX category. +// uses the MMX registers. The 64-bit versions are grouped with the MMX +// classes. They need to be enabled even if AVX is enabled. class SS38I o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, T8, - Requires<[HasSSSE3]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, T8PD, + Requires<[UseSSSE3]>; class SS3AI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TA, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + Requires<[UseSSSE3]>; +class MMXSS38I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, T8, + Requires<[HasSSSE3]>; +class MMXSS3AI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TA, Requires<[HasSSSE3]>; // SSE4.1 Instruction Templates: @@ -417,176 +560,265 @@ class SS3AI o, Format F, dag outs, dag ins, string asm, // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. // class SS48I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8, - Requires<[HasSSE41]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, T8PD, + Requires<[UseSSE41]>; class SS4AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TA, - Requires<[HasSSE41]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + Requires<[UseSSE41]>; // SSE4.2 Instruction Templates: // // SS428I - SSE 4.2 instructions with T8 prefix. class SS428I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8, - Requires<[HasSSE42]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, T8PD, + Requires<[UseSSE42]>; // SS42FI - SSE 4.2 instructions with T8XD prefix. +// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns. class SS42FI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8XD, Requires<[HasSSE42orAVX]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, T8XD, Requires<[HasSSE42]>; // SS42AI = SSE 4.2 instructions with TA prefix class SS42AI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TA, - Requires<[HasSSE42]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + Requires<[UseSSE42]>; // AVX Instruction Templates: // Instructions introduced in AVX (no SSE equivalent forms) // -// AVX8I - AVX instructions with T8 and OpSize prefix. -// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8. +// AVX8I - AVX instructions with T8PD prefix. +// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. class AVX8I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8, OpSize, + list pattern, InstrItinClass itin = NoItinerary> + : I, T8PD, Requires<[HasAVX]>; class AVXAIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TA, OpSize, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, Requires<[HasAVX]>; // AVX2 Instruction Templates: // Instructions introduced in AVX2 (no SSE equivalent forms) // -// AVX28I - AVX2 instructions with T8 and OpSize prefix. -// AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8. +// AVX28I - AVX2 instructions with T8PD prefix. +// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. class AVX28I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, T8, OpSize, + list pattern, InstrItinClass itin = NoItinerary> + : I, T8PD, Requires<[HasAVX2]>; class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TA, OpSize, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, Requires<[HasAVX2]>; + +// AVX-512 Instruction Templates: +// Instructions introduced in AVX-512 (no SSE equivalent forms) +// +// AVX5128I - AVX-512 instructions with T8PD prefix. +// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. +// AVX512PDI - AVX-512 instructions with PD, double packed. +// AVX512PSI - AVX-512 instructions with TB, single packed. +// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. +// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. +// AVX512BI - AVX-512 instructions with PD, int packed domain. +// AVX512SI - AVX-512 scalar instructions with PD prefix. + +class AVX5128I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, T8PD, + Requires<[HasAVX512]>; +class AVX512XS8I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, T8XS, + Requires<[HasAVX512]>; +class AVX512XSI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, XS, + Requires<[HasAVX512]>; +class AVX512XDI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, XD, + Requires<[HasAVX512]>; +class AVX512BI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, + Requires<[HasAVX512]>; +class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, PD, + Requires<[HasAVX512]>; +class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + Requires<[HasAVX512]>; +class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TB, + Requires<[HasAVX512]>; +class AVX512PDI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, + Requires<[HasAVX512]>; +class AVX512PSI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, + Requires<[HasAVX512]>; +class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d, InstrItinClass itin = NoItinerary> + : Ii8, TB, Requires<[HasAVX512]>; +class AVX512PI o, Format F, dag outs, dag ins, string asm, + list pattern, Domain d, InstrItinClass itin = NoItinerary> + : I, TB, Requires<[HasAVX512]>; +class AVX512FMA3 o, Format F, dag outs, dag ins, string asm, + listpattern, InstrItinClass itin = NoItinerary> + : I, T8PD, + EVEX_4V, Requires<[HasAVX512]>; + // AES Instruction Templates: // // AES8I // These use the same encoding as the SSE4.2 T8 and TA encodings. class AES8I o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8, - Requires<[HasSSE2, HasAES]>; + listpattern, InstrItinClass itin = IIC_AES> + : I, T8PD, + Requires<[HasAES]>; class AESAI o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TA, - Requires<[HasSSE2, HasAES]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + Requires<[HasAES]>; -// CLMUL Instruction Templates -class CLMULIi8 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8, TA, - OpSize, Requires<[HasSSE2, HasCLMUL]>; +// PCLMUL Instruction Templates +class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + Requires<[HasPCLMUL]>; -class AVXCLMULIi8 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8, TA, - OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>; +class AVXPCLMULIi8 o, Format F, dag outs, dag ins, string asm, + listpattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + VEX_4V, Requires<[HasAVX, HasPCLMUL]>; // FMA3 Instruction Templates class FMA3 o, Format F, dag outs, dag ins, string asm, - listpattern> - : I, T8, - OpSize, VEX_4V, Requires<[HasFMA3]>; + listpattern, InstrItinClass itin = NoItinerary> + : I, T8PD, + VEX_4V, FMASC, Requires<[HasFMA]>; // FMA4 Instruction Templates class FMA4 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8, TA, - OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>; + listpattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>; // XOP 2, 3 and 4 Operand Instruction Template class IXOP o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, + list pattern, InstrItinClass itin = NoItinerary> + : I, XOP, XOP9, Requires<[HasXOP]>; // XOP 2, 3 and 4 Operand Instruction Templates with imm byte class IXOPi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XOP, XOP8, Requires<[HasXOP]>; // XOP 5 operand instruction (VEX encoding!) class IXOP5 o, Format F, dag outs, dag ins, string asm, - listpattern> - : Ii8, TA, - OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; + listpattern, InstrItinClass itin = NoItinerary> + : Ii8, TAPD, + VEX_4V, VEX_I8IMM, Requires<[HasXOP]>; // X86-64 Instruction templates... // -class RI o, Format F, dag outs, dag ins, string asm, list pattern> - : I, REX_W; +class RI o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, REX_W; class RIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, REX_W; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, REX_W; +class RIi16 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii16, REX_W; class RIi32 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii32, REX_W; + list pattern, InstrItinClass itin = NoItinerary> + : Ii32, REX_W; +class RIi32S o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : Ii32S, REX_W; class RIi64 o, Format f, dag outs, dag ins, string asm, - list pattern> - : X86Inst, REX_W { + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst, REX_W { + let Pattern = pattern; + let CodeSize = 3; +} + +class RIi64_NOREX o, Format f, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class RSSI o, Format F, dag outs, dag ins, string asm, - list pattern> - : SSI, REX_W; + list pattern, InstrItinClass itin = NoItinerary> + : SSI, REX_W; class RSDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : SDI, REX_W; + list pattern, InstrItinClass itin = NoItinerary> + : SDI, REX_W; class RPDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : PDI, REX_W; + list pattern, InstrItinClass itin = NoItinerary> + : PDI, REX_W; class VRPDI o, Format F, dag outs, dag ins, string asm, - list pattern> - : VPDI, VEX_W; + list pattern, InstrItinClass itin = NoItinerary> + : VPDI, VEX_W; +class RS2I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : S2I, REX_W; +class VRS2I o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : VS2I, VEX_W; // MMX Instruction templates // // MMXI - MMX instructions with TB prefix. +// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. -// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. +// MMX2I - MMX / SSE2 instructions with PD prefix. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. class MMXI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, TB, Requires<[HasMMX]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, Requires<[HasMMX]>; +class MMXI32 o, Format F, dag outs, dag ins, string asm, + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, Requires<[HasMMX,Not64BitMode]>; class MMXI64 o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, TB, Requires<[HasMMX,In64BitMode]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, Requires<[HasMMX,In64BitMode]>; class MMXRI o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, TB, REX_W, Requires<[HasMMX]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, TB, REX_W, Requires<[HasMMX]>; class MMX2I o, Format F, dag outs, dag ins, string asm, - list pattern> - : I, TB, OpSize, Requires<[HasMMX]>; + list pattern, InstrItinClass itin = NoItinerary> + : I, PD, Requires<[HasMMX]>; class MMXIi8 o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, TB, Requires<[HasMMX]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, TB, Requires<[HasMMX]>; class MMXID o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XD, Requires<[HasMMX]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XD, Requires<[HasMMX]>; class MMXIS o, Format F, dag outs, dag ins, string asm, - list pattern> - : Ii8, XS, Requires<[HasMMX]>; + list pattern, InstrItinClass itin = NoItinerary> + : Ii8, XS, Requires<[HasMMX]>;